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5G, Video and SDNs – High Volume Drivers for Photonic Systems-on-Chip (PSoC)

5G, Video and SDNs – High Volume Drivers for Photonic Systems-on-Chip (PSoC)
by Mitch Heins on 05-24-2016 at 7:00 am
Categories: Silicon Photonics

The move towards 5G networks with demands for decreased latency ( 100 devices/m[SUP]2[/SUP]), and the desire to flexibly configure and integrate mobile, fixed, optical and satellite telecommunications is putting tremendous pressure on the design of next generation telecom equipment. Silicon photonics promises to be the most viable solution to the growing need for communication networks with increased flexibility, processing capacity and bandwidth density while at the same time delivering reduced cost, power consumption and footprint.

A team from Ericsson Research in Pisa, Italy, captured their thoughts on what next generation optical transport networks will look like in chapter 15 of the recently published book, Silicon Photonics III. Their opinion is that next generation optical networks must be capable of performing dynamic rearrangement of bandwidth while optimizing resource utilization and power consumption. Furthermore, they believe this will be enabled by highly flexible transport nodes in conjunction with an intelligent control and management plane based on software-defined networking (SDN). A high level view of the current optical transport network is depicted in Fig 15.12 and is divided into four segments.

[LIST=1]

  • Access networks, including radio area networks (RANs) with front-haul networks of centralized radio equipment controllers servicing a cloud of distributed radio equipment and back-haul networks where traffic from the front-haul radio base stations is collected on wavelength division multiplexed (WDM) rings.
  • Metro-Aggregation networks, that concentrates and distributes traffic from/to the back-haul access networks. Typical capacity of this segment is in the 100’s of Gbps range.
  • Metro-Core networks, that interconnects nodes in large metropolitan areas with distances between nodes of up to 600 km and node capacities from 100’s of Gbps to a few 10’s of Tbps.
  • Core networks, that interconnects many metro segments with distances of 1000’s of km and node capacities beyond 10 Tbs up to 100Tbs.

    The higher volumes of switches that promise to drive integrated silicon photonics are in the metro-aggregation and access transport nodes. To support 5G and associated multi-directional video traffic that is coming, an all-optical switching layer must be implemented based on scalable, high capacity and transparent switching subsystems. At the heart of each node is a multi-directional ROADM (re-configurable optical add/drop multiplexer) whose function is to add and/or drop a certain number of WDM channels carrying local traffic from data centers or client switching equipment to/from the main networks. Highly flexible optical switching nodes are needed with the following characteristics:

    • Full remote re-configuration without the need for any manual intervention
    • Automated control and light-path set-up
    • Capability of re-configuring the light-paths in sub-milliseconds for on-the-fly connection restoration

    Conventional ROADM switches only provide flexibility to reconfigure input/output communications of the switch in the main network. However, the add/drop functionality that enables connections from nodes to local resources are currently rigidly assigned and can only be changed by manually re-wiring the connections. Additionally, these wavelength selective switches (WSS) are currently made using discreet high-performance free-space optics that are both costly and bulky. These existing switches are too expensive to move into the higher-volume access and metro-aggregation networks and represent new opportunity for integrated silicon photonic solutions.

    Next generation ROADMs built using integrated silicon photonics will have the ability to not only be re-configurable at the local level but they will also be colorless, directionless and contention-less (CDC). With these new switches it will be possible through SDNs, without any manual intervention, to change the configuration of add/drop wavelength channels to/from any direction (direction-less), independent of the transponder wavelengths (color-less), while allowing multiple signals with the same wavelength to be handled by the same add/drop structure (contention-less). Silicon photonic-based CDC-ROADMs will give the operator the ability to optimize resource utilization, reconfigure network bandwidth according to the variation of traffic patterns depending on time of day and day of week usage and support rerouting functions in case of network faults in a cost effective way. The CDC-ROADMs will make use of new blocks in the Add/Drop sections of the switch called transponder aggregators (TPAs). TPAs will distribute and select the multiplexed signals before filtering the individual channels by the use of tunable filters and add flexibility to the exact point of the optical node where the older ROADMs lacked it.

    One instance of this new architecture is being put into reality through a project known as IRIS, funded by the European Union’s Seventh Framework Programme. IRIS will implement a complete TPA optical switching subsystem using a monolithic integration of all functions on one Photonic System-on-Chip (PSoC) IC.

    Make no mistake, integrated silicon photonics is coming. It’s not a question of “if” but only a question of “when”. The drive towards bidirectional on-demand video and the push to 5G networks with millions of mobile devices and sensors will be the forcing function that brings silicon photonics into the volumes that will get the attention of every foundry.

    • Posted on

    5G, Video and SDNs – High Volume Drivers for Photonic Systems-on-Chip (PSoC)

    5G, Video and SDNs – High Volume Drivers for Photonic Systems-on-Chip (PSoC)
    by Mitch Heins on 05-24-2016 at 7:00 am
    Categories: Silicon Photonics

    The move towards 5G networks with demands for decreased latency ( 100 devices/m[SUP]2[/SUP]), and the desire to flexibly configure and integrate mobile, fixed, optical and satellite telecommunications is putting tremendous pressure on the design of next generation telecom equipment. Silicon photonics promises to be the most viable solution to the growing need for communication networks with increased flexibility, processing capacity and bandwidth density while at the same time delivering reduced cost, power consumption and footprint.

    A team from Ericsson Research in Pisa, Italy, captured their thoughts on what next generation optical transport networks will look like in chapter 15 of the recently published book, Silicon Photonics III. Their opinion is that next generation optical networks must be capable of performing dynamic rearrangement of bandwidth while optimizing resource utilization and power consumption. Furthermore, they believe this will be enabled by highly flexible transport nodes in conjunction with an intelligent control and management plane based on software-defined networking (SDN). A high level view of the current optical transport network is depicted in Fig 15.12 and is divided into four segments.

    [LIST=1]

  • Access networks, including radio area networks (RANs) with front-haul networks of centralized radio equipment controllers servicing a cloud of distributed radio equipment and back-haul networks where traffic from the front-haul radio base stations is collected on wavelength division multiplexed (WDM) rings.
  • Metro-Aggregation networks, that concentrates and distributes traffic from/to the back-haul access networks. Typical capacity of this segment is in the 100’s of Gbps range.
  • Metro-Core networks, that interconnects nodes in large metropolitan areas with distances between nodes of up to 600 km and node capacities from 100’s of Gbps to a few 10’s of Tbps.
  • Core networks, that interconnects many metro segments with distances of 1000’s of km and node capacities beyond 10 Tbs up to 100Tbs.

    The higher volumes of switches that promise to drive integrated silicon photonics are in the metro-aggregation and access transport nodes. To support 5G and associated multi-directional video traffic that is coming, an all-optical switching layer must be implemented based on scalable, high capacity and transparent switching subsystems. At the heart of each node is a multi-directional ROADM (re-configurable optical add/drop multiplexer) whose function is to add and/or drop a certain number of WDM channels carrying local traffic from data centers or client switching equipment to/from the main networks. Highly flexible optical switching nodes are needed with the following characteristics:

    • Full remote re-configuration without the need for any manual intervention
    • Automated control and light-path set-up
    • Capability of re-configuring the light-paths in sub-milliseconds for on-the-fly connection restoration

    Conventional ROADM switches only provide flexibility to reconfigure input/output communications of the switch in the main network. However, the add/drop functionality that enables connections from nodes to local resources are currently rigidly assigned and can only be changed by manually re-wiring the connections. Additionally, these wavelength selective switches (WSS) are currently made using discreet high-performance free-space optics that are both costly and bulky. These existing switches are too expensive to move into the higher-volume access and metro-aggregation networks and represent new opportunity for integrated silicon photonic solutions.

    Next generation ROADMs built using integrated silicon photonics will have the ability to not only be re-configurable at the local level but they will also be colorless, directionless and contention-less (CDC). With these new switches it will be possible through SDNs, without any manual intervention, to change the configuration of add/drop wavelength channels to/from any direction (direction-less), independent of the transponder wavelengths (color-less), while allowing multiple signals with the same wavelength to be handled by the same add/drop structure (contention-less). Silicon photonic-based CDC-ROADMs will give the operator the ability to optimize resource utilization, reconfigure network bandwidth according to the variation of traffic patterns depending on time of day and day of week usage and support rerouting functions in case of network faults in a cost effective way. The CDC-ROADMs will make use of new blocks in the Add/Drop sections of the switch called transponder aggregators (TPAs). TPAs will distribute and select the multiplexed signals before filtering the individual channels by the use of tunable filters and add flexibility to the exact point of the optical node where the older ROADMs lacked it.

    One instance of this new architecture is being put into reality through a project known as IRIS, funded by the European Union’s Seventh Framework Programme. IRIS will implement a complete TPA optical switching subsystem using a monolithic integration of all functions on one Photonic System-on-Chip (PSoC) IC.

    Make no mistake, integrated silicon photonics is coming. It’s not a question of “if” but only a question of “when”. The drive towards bidirectional on-demand video and the push to 5G networks with millions of mobile devices and sensors will be the forcing function that brings silicon photonics into the volumes that will get the attention of every foundry.

    • Posted on

    Testing IGBTs before they go into EVs

    Testing IGBTs before they go into EVs
    by Don Dingee on 05-23-2016 at 4:00 pm
    Categories: Automotive, EDA, Siemens EDA

    In the pages of SemiWiki, we are usually talking about what to do with billions of really small transistors – for a change of pace today, we’ll discuss what to do with a few really big ones. Mentor Graphics has just announced their latest MicReD platform for thermal testing of IGBTs, experiencing a resurgence (pun intended) thanks to electric vehicles. Continue reading “Testing IGBTs before they go into EVs”

    Posted on

    What Does an MPW and a Pizza Have in Common?

    What Does an MPW and a Pizza Have in Common?
    by Daniel Nenni on 05-23-2016 at 12:00 pm
    Categories: EDA, eSilicon, Semiconductor Services, TSMC

    Design starts are critical to the growth of the semiconductor industry so enabling them is a common theme on SemiWiki. One thing we have not covered in detail is multi-project wafer services (MPW) which is the equivalent of ride sharing through the initial mask and wafer process. Larger semiconductor companies already do this internally but what about the rest of the world, especially budget constrained Universities? We need their design starts too!

    Let’s face it, the costs of mask sets are increasing with every node. Currently, a 6mm[SUP]2[/SUP] area tile at 28nm can cost more than $100,000 so why not share the ride with someone that has similar requirements? The bigger question is how do I find that special someone? Of course there is an app for that (think Tinder/Uber/AirBnB/etc… for an MPW).

    eSilicon MPW Explorer: Fast, Accurate Quotes
    Evaluate Options and Get Fast, Accurate Quotes for Multi-Project Wafer Shuttle Services. Quote and Compare: Free, Automated Online Multi-Project-Wafer Quote System Delivers Instant Pricing…

    Here are some recent examples:

    180nm MPW Sharing Platform:

    • Flavor: TSMC 180nm MS RF GP
    • Metal stack: 1P6M_4x1u (40KA top metal thickness)
    • I/O: 3.3V
    • MiM cap density (if used): 2fF/um[SUP]2[/SUP]
    • Price: $1,000/mm[SUP]2[/SUP]; 5mm[SUP]2[/SUP]minimum area

    40nm MPW Sharing Platform

    • Flavor: TSMC 40nm MS RF G
    • Metal stack: 1P10_7x1z1u
    • I/O: 1.8V
    • Price: $7,500/mm[SUP]2[/SUP]; 1mm[SUP]2[/SUP]minimum area

    eSilicon even hosts tapeout parties for Universities: MPW Tapeout Parties & eSilicon MPW Team (Arizona State University and Texas A&M January 2016, UCLA February 2016, University of Illinois, Urbana-Champaign March 2016, University of Minnesota April 2016).

    For you Millennials, the term tapeout comes from a prehistoric time when we used to stream the design data to magnetic tape reels that were then sent to photomask facilities for processing.

    eSilicon Multi-Project Wafer Service FAQ:

    What does the multi-project wafer (MPW) price include?
    Services included are listed in Appendix B of your MPW quote.

    Can I get my MPWs packaged?
    Yes, standard MPW die packages are available using our online form for quick cost comparisons. You can also package some of your die and receive the rest in bare die form if you like. If you are interested in other standard or custom IC packages, please contact the eSilicon sales manager assigned to you in your account confirmation email. We can probably help you. Please visit our Multi-Project Wafer Services overview page for an up-to-date list of our online MPW package offering.

    What about testing? Can I get my parts tested before delivery?
    Yes, testing services are available on request. Please contact the eSilicon sales manager assigned to you in your confirmation email for details.

    Can I find out when the various foundries run their MPWs?
    Yes, please, access the MPW schedules link on the top menu of the MPW Explorer interface.

    Can I cancel an MPW reservation?
    Yes, MPW reservations can be canceled. The process and associated fees, if any, are as described in Section 5 of Appendix D of your MPW quote.

    Do I need an export certification?
    It depends on the application. eSilicon will provide you with a very simple questionnaire to determine what, if anything, you need. This form will soon be online.

    On the quote request form, what is “MPW tile size?”
    “MPW tile size” is the minimum block size for an MPW order at a specific foundry and technology. For example, at TSMC 65GP, the minimum is 12mm2. Normally, if a customer orders an MPW with a 6.1mm2 die area at TSMC 65GP, they will be invoiced for a 12mm2 die area.

    Is there any way to reduce the “MPW tile size”
    Yes, eSilicon has developed a worldwide MPW sharing program. We can work with you to find other customers to share the cost of the MPW tile of your choice. Please visit our MPW Sharing Page to see the latest sharing opportunities.

    Can eSilicon offer MPWs from other foundries or technologies besides the ones listed?
    Yes, we are always working to add new foundries. Contact us at STAR@eSilicon.com with the foundry you’re interested in and we’ll give you the status.

    Sign Up Log In

    About eSilicon
    eSilicon guides customers through a fast, accurate, transparent, low-risk ASIC journey, from concept to volume production. Explore your options online with eSilicon STAR tools, engage with eSilicon experts, and take advantage of eSilicon semiconductor design, custom IP and IC manufacturing solutions through a flexible engagement model. eSilicon serves a wide variety of markets including the communications, computer, consumer, industrial products and medical segments. Get the data, decision-making power and technology you need for first-time-right results. www.esilicon.com

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    "Re-Inventing" Tapeout Sign-off — Applying Big Data Techniques to Electrical Analysis

    "Re-Inventing" Tapeout Sign-off — Applying Big Data Techniques to Electrical Analysis
    by Tom Dillinger on 05-23-2016 at 7:00 am
    Categories: Ansys, Inc., EDA

    A common SoC design methodology in current use starts with preparation of the physical floorplan — e.g., block/pin placement, global clock domain and bus signal planning, developing the global/local power distribution (and dynamic power domain management techniques). Decoupling capacitor estimated densities and insertion methods are defined. From this initial plan, individual IP block implementations are pursued, using margins for local power voltage drop and dynamic noise. As the IP evolves, updates to the floorplan are made, based upon improved insights on block area, pin locations, global routing demand, etc. A key milestone is the first integration of the IP into a full-chip model.

    Electrical analysis is now undertaken on the integrated model to investigate global issues, utilizing functional activity operating mode (and mode switching) patterns:

    • (dynamic and static) I*R drop on power/gnd nets
    • thermal mapping (e.g., identification of hot spots, generation of self-heating data)
    • electromigration

    The chip integration engineering team is often faced with a dilemma. The dataset size of the full-chip parasitic model is large, and increasing with each new process node. The compute resources required to perform these analyses are demanding — with current tool algorithms, a single “integration server” in the data center (with maximum memory installed) is drained of other jobs and allocated to the task. The runtime for these analyses is typically several days each — the design version snapshot used is likely already out-of-date before the jobs complete, necessitating a version sync-up/merge to effect any requisite changes from the analysis results.

    The final integration is intended to provide tapeout sign-off quality results. The design database is frozen, with only judiciously-selected ECO’s allowed. Ideally, issues from prior full-chip electrical analyses have been resolved, but inevitably the convergence of late functional bug fixes, timing closure updates, and power dissipation optimizations will require a final, detailed sign-off analysis. Again, the demand for integration server compute resources — and, especially, the overall throughput for any ECO iterations — will be extreme. The sign-off DRC/DFM/DFY jobs running concurrently on the frozen database add to the compute demand pressures.

    In the future, this path to sign-off will become increasingly difficult, if not intractable. The trends in parasitic dataset size, the server memory constraints, and the analysis throughput requirements are all asserting pressure on this flow. Methods to compress the parasitic network model may assist with the resources required, at a potential loss of accuracy. With the requirement to reduce supply voltage and power dissipation, and with the greater electromigration and thermal challenges of advanced process nodes, the accuracy demands are even more stringent. Alternatively, to save resources, the integration engineer could opt to skip some of the operating modes where dynamic analysis is performed. Yet, the application requirements of an increasingly diverse set of markets demand more comprehensive analysis coverage, not less (e.g., automotive, medical and healthcare, mil/aero). Clearly, the SoC design industry is at a crossroads.

    I recently had the opportunity to review these concerns with Aveek Sarker, VP Sales and Support, and Ravi Ravikumar, Senior Marketing Manager, with the Semiconductor Business Unit at Ansys. Their enthusiasm for a new Ansys product strategy and emerging tools was contagious.

    Ansys recently announced the SeaScapeplatform for electrical analysis tool development. Aveek said, “The big data analytics industry has addressed how to distribute, or shard, large datasets across many individual cores, each with a relatively small amount of local memory. The programming models are in place to apply map/reduce algorithms to this distributed dataset, collecting final results. We have leveraged this model, and the technology developed by a recent Ansys acquisition, Gear Design Solutions, to apply these techniques to full-chip electrical analysis. We know that future designs will require an analysis architecture that is extremely scalable. We are already seeing models approaching 10TB in size.”

    The domain of chip electrical analysis is more complex than executing an SQL query on a big data model. Ansys had to develop new solvers — e.g., a distributed graph solver, a full distributed matrix solver, and data allocation methods to both fit within the allocated memory per core while minimizing inter-machine communications. And, whereas big data analytic results are typically numerical, SoC electrical analysis requires visual insights and feedback — Ansys also developed a thin client viewer to this distributed database.

    SeaScape will be the application development platform for a set of multi-domain, multi-physics solutions from Ansys. The first product application available on this platform is SeaHawk, the distributed equivalent to the industry-leading RedHawk for SoC power distribution analysis.

    It was at this point in our discussion where Aveek really challenged my way of thinking about chip integration and signoff — he posed the following provoking questions. “Using your existing IT data center and grid infrastructure, what if full-chip electrical analysis was completed in hours, rather than days? As an example, a 16nm SoC design from an early SeaHawk customer with 1B model elements recently completed full static and transient power distribution analysis in 5 hours.”

    He continued, “What if integration engineers and unit/core implementation engineers had a much tighter optimization loop between them? Other early customers have provided feedback that they are able to more easily optimize the power distribution, no longer imposing a conservative, uniform global grid pushed down from the initial floorplan using conservative margins for the voltage drop budget. Their result was a reduction in die area.”

    There is definitely a requirement to address the growing complexity of full-chip electrical (and thermal) models, while maintaining accurate analysis and efficient throughput. Ansys has adapted the infrastructure developed for big data analytics to build a distributed database management system for electronic application development, to address this demand.

    More than that, however, Aveek said, “We feel we have the capability to re-invent sign-off.” If the arduous, multi-day task of full-chip electrical analysis is reduced to an optimization loop that can be run regularly on the integration model, final electrical signoff could be greatly simplified. He may indeed be right.

    Please follow these links for more information onSeaScapeand SeaHawk.

    If you will be attending DAC 2016, please explore the Ansys DAC presentations on this new platform and product — more information on the Ansys DAC program is available here.

    -chipguy

    Related Blog: Rebooting EDA

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    Rebooting EDA

    Rebooting EDA
    by Bernard Murphy on 05-23-2016 at 7:00 am
    Categories: Ansys, Inc., EDA

    In the 35 years since commercial EDA went mainstream a lot of advances have been made but the fundamental architecture and even the philosophy of tooling have really not advanced at all. Tools are designed around individual tasks – analysis and optimization within a specific domain – under the assumption that variability within other domains can be held constant, or approximated through margins or, if unavoidable, can be folded into the calculation at the expense of decreased capacity and performance.

    The last option is becoming less practical as Moore’s law is slowing. When problems get harder, we have to split them up into smaller pieces and we have to accept more limitations on what we can build and how it can be used. But these limitations come from assuming we have to do all our calculation in one tool. Suppose it was possible to co-analyze across multiple domains without this constraint and, more importantly, suppose that would get us to a significantly better result – faster, cheaper, lower power and more reliable. Have we not been doing that simply because we didn’t know it could be done?

    Ansys is leading the charge to make this possible through their SeaScape platform, and to do that they have fundamentally changed that single-objective EDA architecture. First they have made it possible to do multi-domain analysis and optimization across very diverse domains. We already know that if we want to find best solutions in a multi-dimensional problem, searching one dimension at a time will give you some improvement but almost certainly not the greatest possible improvement. SeaScape makes it possible to look at multiple dimensions together, which means we can find those globally optimal solutions.

    Second, Seascape doesn’t try to fix the problem by pushing more functionality into monolithic tools; that approach is inherently self-limiting. Think about physical design – it already looks at geometry, timing, power dissipation and signal integrity; doing all of this already limits capacity sufficiently that large designs have to be partitioned. It’s not realistic to assume that to all these functions you can also add IR-drop, EM and other analyses dependent on dynamic use-case scenarios. SeaScape instead uses Big Data techniques to mine multi-domain simulation data (power, timing, package characteristics and more) to provide real-time feedback.

    And third, to get scalability of analysis, SeaScape turns traditional EDA architecture inside-out. In the classical EDA approach, you start with your tool and then you work on making it multi-threaded (you might also work on additional task partitioning). But all of this is a tool-centric optimization – what you do for one tool doesn’t necessarily benefit other tools, especially if they are in different domains. Seascape instead provides an intrinsically scalable foundation for applications. It does this with a variant on the Big Data MapReduce concept, adapted to handle the distributed LSF/Linux server networks and EDA datatypes (layout, simulation, ..) and databases common in this domain.

    Ansys isn’t positioning to replace the entire EDA toolchain. SeaScape-based analytics complement existing well-known logical and physical design tools. Those tools will just do a better job working with Ansys applications built on SeaScape. Meantime Ansys will continue to advance this capability to build further optimizations up into the package and system levels, complementing the multi-physics analysis they already provide for mechanical, electromagnetics and fluidics design. Since that’s where more of the electronics industry focus is going these days, that seems like a smart move.

    To learn more about SeaScape, click HERE. To learn more about about how Ansys has applied SeaScape to their new SeaHawk product, click HERE. ChipGuy has a blog about SeaHawkwhich goes into more detail on application to redefining signoff. And to get a live update and an opportunity to question the experts on what next-generation EDA products can do for you, register for Ansys suite sessions at DAC (in-design and best practices, kicking off June 6[SUP]th[/SUP] in Austin) HERE.

    More articles by Bernard…

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    Google TPU Another Step in a Shifting Semiconductor Landscape

    Google TPU Another Step in a Shifting Semiconductor Landscape
    by Bernard Murphy on 05-22-2016 at 4:00 pm
    Categories: EDA

    Markets work when consumers of a widget don’t feel there is significant differentiated value in making their own and would rather get lowest possible cost from experienced widget makers who can amortize their investment over high-volume sales to many customers. But that changes when a large consumer finds they can increase differentiated value if they build their own.

    A case in point is a rather large speed bump for what had seemed like boundless potential for GPU growth around deep learning/neural net applications. That speed bump is a Google announcement of their Tensor Processing Unit (TPU) which is a dedicated accelerator for learning. This doesn’t mean the market goes away for GPUs in general or GPUs applied to learning. But when one of the largest companies in the world, who are deploying this function in their datacenters/cloud, announces they have this function covered themselves – that’s a speed bump for GPU makers.

    TPUs are designed to accelerate learning in TensorFlow in applications like StreetView, RankBrain and voice recognition for translating voicemails to text, among other applications. Because the design team understands the applications they apparently have been able to reduce precision, allowing more operations to be packed into a given area, leading to greater performance. No magic – they just have done what we all would do if we didn’t have to design a general-purpose solution.

    Google also said that they have no intention of selling TPUs to anyone else. Why would they – this gives them a technical advantage. And what used to be a barrier for smaller ventures building their own chips – cost, building expertise and so on – is pocket-change for Google.

    I suspect this is another step in a trend, not an isolated case. As Moore’s law slows, accelerators will rise again in popularity; as new needs appear in big data, machine learning, fintech, it’s not unreasonable to expect more in-house development. This won’t just be for Google. Facebook, Amazon, Netflix and other 800 pound gorillas will be looking for every advantage they can find. General market hardware will still have a place but not around the bleeding edge, especially when much of the software in these domains is now open-source.

    Again, I’m not saying the merchant semiconductor market goes away. They can still sell to PC makers, automakers, some (though maybe not all?) IoT device makers and other existing consumers; perhaps also to the gorillas in some applications. But when new large dollar volume opportunities go internal in some of the largest tech companies, that’s an important shift.

    You could look at this as a bad thing or a good thing. Maybe not so good if you want to stay with the (old) status quo in semiconductor design. But actually pretty good if you’re a design engineer looking for leading-edge opportunities. The jobs aren’t going away – they’re just shifting to different companies.

    You can read more HERE.

    More articles by Bernard…

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    Ride Hailing is Not Ride Sharing

    Ride Hailing is Not Ride Sharing
    by Roger C. Lanctot on 05-22-2016 at 12:00 pm
    Categories: Automotive

    There are many misconceptions about ride sharing as journalists and analysts are wont to refer to Uber, Lyft, DiDi and the rest. Conceived as a means to increase asset utilization by allowing drivers to pick up passengers along their way, ride sharing services instantly became ride hailing services directly competing with taxis and displacing the use of rental cars.

    As services such as Uber and Lyft have grown, their founders and collaborating journalists and analysts foster claims that vehicle sales are being or will be negatively impacted. If these services were true to their names and indeed offered ride sharing it might be rational to expect a decline in vehicle sales, but the reality is that the displacement of taxis and rental cars has failed to stem the ascent of new vehicle sales.

    In fact, the rise in new vehicle sales is especially impressive given the dual factors of millennials eschewing new car purchases (according to surveys and estimates by those same analysts and journalists) and new vehicles continuing to last longer and longer – now upwards of 11 years. In other words existing cars lasting longer and young people – mainly in urban areas – turning away from cars and driver’s licenses ought to be putting a damper on vehicle demand, but car sales keep growing.
    It’s a sad but true reality. Cars resist displacement. You can make them more expensive to own, park and drive, and people keep buying them, parking them and driving them – ever more slowly as more and more cars clog streets all over the world.

    There is something Malthusian afoot here. It is a well-known principle of traffic that we cannot build our way out of this mess of too many vehicles on the road. And we are fooling ourselves if we think Uber, Lyft and DiDi are going to dim demand.

    But if so called ride sharing services actually represented ride sharing there might be some hope. The services that are or will have an impact on vehicle sales are those that focus on carpooling such as BlaBlaCar, Uberpool and Via, among others.

    Cities, states and the Federal government in the U.S. – along with governments elsewhere in the world – are increasingly looking to commuters as a target for traffic consolidation. The latest rule making out of the U.S. Department of Transportation’s Federal Highway Administration is targeted at measuring travel times for commuters and truck drivers in the interest of establishing more reliable measures of congestion and emissions.

    The heart of the matter is the predictability of the behavior patterns of commuter populations and the public interest served by helping commuters traveling along similar routes to more easily coordinate their transportation decisions. The data already exists regarding the most heavily traveled routes within cities. The goal now is to identify the most heavily traveled routes coming into and out of the city.
    Via used historical limousine and taxi trip data in New York City to set up its true ride sharing proposition – multiple passengers at $5-$7/ride along predetermined routes. Multiple cities in the U.S. already have slug lines to help commuters take advantage of high-occupancy-vehicle (HOV) lanes into and out of major cities.

    Carpooling – a.k.a. ride sharing – is the new frontier of congestion reduction. Critics have been lining up to castigate Apple for its $1B investment in DiDi in China noting that ride hailing services from DiDi to Uber are in a money-burning battle for market share. It’s not at all clear that billions of dollars in value will be realized at the other end of that bonfire.

    But companies such as Via and BlaBlaCar that are actually able to get people to share vehicles – actually share rides – offer the twin advantages to municipalities of taking cars off the road and increasing human being throughput in existing cars on existing vehicle arteries. The only alternative strategy that even comes close is the growing number of departments of transportation that are looking at HOV lanes for self-driving cars capable of driving more closely together in so-called platoons.

    Focusing on commuters has the added advantage of creating a concentrated target market for timely traffic information and advertising. Of course, a car full of commuters isn’t necessarily interested in listening to the same commercial message – but if those commuters aren’t doing the driving they can be reached individually on their mobile devices.

    Transportation network companies focused on commuters have the potential to reduce vehicle demand and ease traffic congestion by increasing the utilization of vehicles already on the road. It will be a measure of car company commitment to change to see which car makers work toward investing in, partnering with or creating their own carpooling solutions.

    Mercedes-Benz Research & Development has partnered with Via. Volvo has invested in RidePal. A car company investing in carpooling is courting its own irrelevance in a ride sharing future. Now that’s what I call taking a risk.

    Roger C. Lanctot is Associate Director in the Global Automotive Practice at Strategy Analytics. More details about Strategy Analytics can be found here: https://www.strategyanalytics.com/access-services/automotive#.VuGdXfkrKUk

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    Where are the Entrepreneurs?

    Where are the Entrepreneurs?
    by Randy Smith on 05-22-2016 at 10:00 am
    Categories: EDA, IoT, IP, Mobile

    This week I attended the UpWest Labs event in San Francisco. UpWest Labs provides seed funding and incubation for a wide range of domains including Enterprise Software, Internet of Things, Infrastructure Technologies, Artificial Intelligence, Consumer Applications, Drones, Cyber Security, Augmented Reality / Virtual Reality, and Marketplaces. Uniquely, UpWest seeks out entrepreneurs in Israel and helps them gain a foothold and build momentum in the US. It is a formula which seems to be thriving.

    I visited Israel last year to speak on a couple panels, one an electronics industry event and the other an event at the engineering school of Bar Ilan University. At both events I was struck by the energy, enthusiasm and creativity of the local engineers attending the event. As I went about my week I learned that there are hundreds of high-tech start-ups in Israel attacking a diverse array of markets and challenges. Within the semiconductor and EDA community, we have not seen such a large number of start-ups in a very long time. It was quite refreshing.

    The UpWest event was hosted at UpWest investment, HoneyBook’s SF headquarters. HoneyBook’s mission statement claims they are on a mission to connect the different parts of the events industry by reimagining the way creative professionals work with their colleagues and clients. For anyone planning an event, HoneyBook’s goal is to organize your job(s) seamlessly, so you can focus on what you do best: creating unforgettable moments. While it is not as complicated as the wide array of problems solved by EDA tools, it is valuable. HoneyBook was only founded in 2013, already has over 60 employees and is profitable. Also note that BVA (where I am now an advisor), a recruiting firm that staffs and invests in start-ups, has built and invested in multiple UpWest deals, including Clicktale, and CoMeet.

    A quick look at the portfolio of UpWest Labs will reveal many interesting companies, including some with a high-tech flavor. One of these at this that caught my eye at the event was, AR-Cadia. AR-Cadia’s CEO and founder, Teddy Bercovitz, gave me a demonstration of some mobile apps that were using the AR-Cadia platform. “AR” here stands for augmented reality. Augmented reality glasses can display additional information to the wearer while letting them still see their environment. This has enormous possible uses. Two examples are in the medical field giving doctors the ability to see different images or scans superimposed over the person’s body, or inventory management by showing the organization or location of products within a warehouse. AR-Cadia has built a platform that allows mobile app developers to support a wide array of AR glasses from many manufacturers without needing to write drivers for each manufacturer – a fantastic idea that may dramatically accelerate this new market.

    Alas, there were no EDA start-ups present, although I did see Jacques Benkoski, former CEO of Monterey Design Systems and current USVP partner, in attendance. I also saw some other VCs at the event who invested in EDA 15 or 20 years ago. Many believe that the heyday of EDA start-ups is over, never to return again. The economics are certainly different now. Larger EDA exits seem to take more than 10 years. The exits are mostly confined to selling the business to one of the major EDA companies who can then deploy the new technology through their much larger sales channels. This leads most people familiar with the industry to conclude that EDA start-up companies should not raise more than $6M over their lifetime in order to have a worthwhile exit. These start-ups also need to have products in a niche or underserved space, or have a defensible breakthrough technology in an existing tool area – both are difficult.

    I was recently heartened to see a new EDA company – SnapEDA. The CEO of SnapEDA, Natasha Baker, is young, energetic and passionate about being in EDA. In years past I was always complaining at EDAC (now ESDA) meetings that we were not spending the effort to attract enough young engineers into EDA to even have an EDA community in the future. I had nightmares of rolling down the aisles at DAC in 25 years and only seeing participants in wheelchairs and walkers. Natasha and SnapEDA give me hope that my nightmares will not come true.

    Randy Smith is an advisor atBrown Venture Associates (BVA). Randy and BVA are experienced masters of team building. As a former EDA and semiconductor IP executive, Randy has repeatedly built winning teams. BVA has been doing the same for more than 20 years while building a proprietary recruiting methodology that is geared for the modern recruiting environment. BVA also has invested in 50+ companies with 20+ liquidity events – the teams they build, win.

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    Donald Trump’s demand that Apple must make iPhones in the U.S. actually isn’t that crazy

    Donald Trump’s demand that Apple must make iPhones in the U.S. actually isn’t that crazy
    by Vivek Wadhwa on 05-21-2016 at 7:00 am
    Categories: Mobile

    Donald Trump has promised that “we’re gonna get Apple to start building their damn computers and things in this country, instead of in other countries.” He said this ata speech at Virginia’s Liberty University andseveralother events. It is very likely that he is not serious; Trump tends to say things he couldn’t possibly mean. But he did raise an intriguing question about whether Apple — and other American companies — could bring manufacturing back to the United States.

    When American companies moved manufacturing to China, it was all about cost. China’s wages were amongst the lowest in the world and its government provided subsidies and turned a blind eye to labor abuse and environmental destruction. Things have changed. China’s labor, real estate, and energy costs have increased to the point that theyare comparable to some parts of the United States. Subsidies are harder to get and Chinese labor is not tolerating the abuse that it once did. China is now a more expensive place to manufacture than Indonesia, Thailand, Mexico, and Indiaaccording to Boston Consulting Group.

    Add to this the efforts by the Chinese government to spur indigenous innovation — by forcing foreign companies to reveal their intellectual property and use local suppliers—and you have strong motivation to relocate manufacturing.

    But Apple is by no means looking to exit from China, its second largest market. It justannounced an investment of $1 billion in Uber’s rival Didi Chuxing. It clearly saw a large market opportunity and a way to appease the Chinese government.

    Technology is, however, changing the labor-cost equation even more and China is becoming unpredictable because of its faltering economy. It may make sense for Apple to locate some of its manufacturing closer to other markets just to protect itself from this uncertainty.

    What is changing the labor situation is robotics. Robots can now do the same manufacturing jobsas humans — for a fraction of the cost. A new generation, from companies such as Rethink Robotics of Boston, ABB of Switzerland, and Universal Robots of Denmark, are dexterous enough to thread a needle and nimble enough to work beside humans. They can do repetitive and boring circuit board assembly and pack boxes. These robots cost less than $40,000 to purchase andas little as a dollar per hour to operate. And unlike human workers, they will work 24-hour shifts without complaining.

    The hurdle in relocating manufacturing for any company such as Apple is the tie to the chain of suppliers of its products’ electronics components. The key question therefore is: how dependent is Apple on its China supply chain?

    In 2015, the supply chain for Apple’s products consisted of 198 global companies with 759 subsidiaries — so this is quite complex. Seamus Grimes of National University of Ireland and Yutao Sun of Dalian University of China studied each of these subsidiaries and interviewed executives of those located in China. The objective of their research was to advise China on how it could move further up the value chain and cause foreign companies to give it more of their intellectual property. The paperthey published, however, provides another interesting insight: into how few of Apple’s technology suppliers are actually Chinese.

    The authors researched each of the 759 subsidiaries and categorized the electronics components into core, non-core, and assembly-related, with the high-cost, intellectual-property dependent technologies being designated as core. They learned that 336, or 44.2 percent, of these subsidiaries were manufacturing in China; 115 were in Taiwan; and 84 in Europe or the United States.

    When the researchers looked into the ownership of subsidiaries that were manufacturing in China, they found that only 3.95 percent were Chinese. And only 2.2 percent of the core component suppliers were Chinese. The largest proportion, 32.7 percent, were Japanese; 28.5 percent were American; 19.0 percent were Taiwanese; and 6.5 percent were European.

    To put it simply, more than half of the components of Apple’s products are imported into China and practically none of the important, core, technologies are made by Chinese companies. Foreign companies do not trust China and nearly all of the intellectual property in Apple’s products originates from outside it.

    This means that the value chains could be shifted over time. This begs the question: what it would cost to move manufacturing to the United States?

    For this, it may be best to look at what Apple’s manufacturing partner Foxconn is doing in India. The Economic Timesreports that Foxconn is finalizing negotiations to build a $10 billion facility to manufacture iPhones in India. The report anticipates it will take 18 months to get this operational.

    India does have a labor cost advantage over the U.S. but robots could eliminate this. Similar manufacturing facilities could be set up in the United States, product by product.

    Of course, this will not be easy and there are many risks. But it certainly is possible for Apple to bring manufacturing back to the United States. If Apple can do this, so can most other companies; their value chains are a lot less complex than Apple’s.

    So it may turn out that for once, Donald Trump’s rant isn’t so crazy.

    Here is an interview on CNBCs Squawk Box with Becky Quick. For more, follow me on Twitter: @wadhwa and visit my website: www.wadhwa.com.