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Are Standard Cell Libs, Memories and Mixed-signal IP Availabe at 7nm FF?

Are Standard Cell Libs, Memories and Mixed-signal IP Availabe at 7nm FF?
by Eric Esteve on 05-05-2016 at 7:00 am
Categories: EDA, FinFET, IP, Synopsys

More than 500 designers (562) have responded to a survey made in 2015 by Synopsys. Answering to the question “What is the fastest clock speed of your design?” 56% have mentioned a clock higher than 500 MHz (and still 40% higher than 1 GHz). If you compare with the results obtained 10 years ago, the largest proportion of answers was for clock ranging between 100 MHz to 300 MHz.

That means that Moore’s law has been extremely effective during the last ten years, and also that for a high proportion of designs, speed improvement is a real need. These designs are the natural candidates to target FinFET technologies. From the graph below, you see that moving from 28nm (bulk) to 14nm FF can provide 45% faster frequency, at constant dynamic & leakage power, each step below, 10nm and 7nm, providing another 20% improvement.

Foundries like TSMC, Samsung or GlobalFoundries are in charge of the technology development and companies like Synopsys have to provide EDA tools and design enablement, foundation, memories and mixed-signal IP. Reading the presentation made by Navraj Nandra during the Silicon Valley SNUG last March will give you a very good understanding of the challenges linked with nodes like 7nm FF, and the way Synopsys has overcome these challenges to design standard cell libraries, memories and interface (mixed-signal) IP. These foundation IP had to be optimized for Power, Performance and Area for 14nm FF, 10nm FF and 7nm FF, just like it was done for now mature nodes, 65nm, 40nm or 28nm.

If you take the example of the RC associated with BEOL, the value per um is moving from 5 E-15 for 14nm FF, to 10.5 E-15 for 10nm FF and up to 21.6 E-15 for 7nm FF, or doubling for every node. Another challenge is the metal pitch, requiring double patterning below 40 nm. Moreover, you can’t just scale down the 10nm standard cell library to target 7nm, but you have to lower the fin count, called “Fin Depopulation”, to lower dynamic power while preserving speed and reducing standard cell density. You even can get an additional 20% speed improvement by using specialized cells & assist circuits and managing electrostatic control.

As well, you can’t just re-use memory compiler, as you have to create new embedded self-test and repair to address new 7nm defects, like process variation induced (fin height, fin pitch or lithography issues), systemic and random faults. Moreover, managing low resistance and parasitic line capacitance are becoming critical at 7 nm, remember that RC value is doubling at every node…

The above table gives you an overview of the many specialized cells developed by Synopsys for 7 nm, optimized for a combination of Performance, Power and Area to target CPU, GPU or DSP. The effort is worth to do, as, after decreasing both the metal pitch and the gate pitch, you benefit from the scaling factor, improving Area, exhibiting much higher Performance (speed improvement graph) and lower Power consumption: PPA has been optimized and this is the first consequence of Moore’s law.

Complexes, multicore SoC designed in 7 nm will certainly integrate CPUs, or GPUs or DSPs, and probably a combination of all these cores. When integrated in the system, such a SoC will interface with DRAM based on DDR3 or DDR4, or LPDDR3, 4 protocol, communicate thanks to USB 3.1 or PCI Express 4.0, to name a few. Before developing such complex IP, a vendor has to evaluate the market size (the TAM) to calculate the ROI and make the decision to invest in heavy development. From this well-known graphic built by Synopsys, we can evaluate the number of cumulated design starts per node, since the technology introduction. After zoom in the graphic, we come to about 200 design starts for 16/14 FF and 50 for 10 and 7nm. This sanity check is very positive, if the IP vendor can afford development cost and expect reasonable market share (usually, Synopsys enjoys in the 40-60% market share for interface IP), the ROI should be great.

From the presentation made at SNUG, we understand that developing for 7 nm interface IP like DDR4, PCIe 4.0 or USB 3.1 type C, to name a few, require satisfying more stringent requirements than for previous bulk-based technologies. The layout effort doubled, due to Restricted Design Rules (RDR) and multi-patterning. To address reliability and process variability issues for digital IP, RAS features has to be implemented for PCIe 4.0 or DDR4, through stronger data protection like parity or ECC in conjunction with protocol defined mechanism to detect and correct errors in the data path and RAMs. He will have to use event counters and statistics to monitor system availability and to leverage error injection and silicon debug capabilities to diagnose issues and validate system recovery. The result will be 30% improved area and power compared to previous FinFET nodes.

You can find many blogs talking about the end of Moore’s law, at least as Moore’s law used to be: faster and cheaper transistor when going down by one node. The introduction of FinFET based technologies is a way to continue Moore’s law by packing more transistors and cores in a SoC with higher performance and lower power. If you asking if there is a market for these FinFET nodes, the 200 design starts in 14/16 nm FinFET is the answer. The chip makers or OEM targeting fin FET need EDA tools, foundation IP (standard cell library and memories) and interface IP portfolio and Synopsys has demonstrated that they offer these down to 7 nm.

From Eric Esteve from IPNEST

You will also benefit from this video here.

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Body-biasing for ARM big or LITTLE in GF 22FDX

Body-biasing for ARM big or LITTLE in GF 22FDX
by Don Dingee on 05-04-2016 at 4:00 pm
Categories: FD-SOI, Foundries, GlobalFoundries

GLOBALFOUNDRIES has been evangelizing their 22FDX FD-SOI process for a few months; readers may have seen Tom Simon’s write-up of their preview at ARM TechCon. Dr. Joerg Winkler recently gave an updated webinar presentation of their approach in an implementation of ARM Cortex-A17 core.

By now, you’ve probably heard that 22FDX targets a cost/die comparable to 28SLP while offering a performance boost from its next-generation FD transistors. 22FDX also offers the ability to integrate RF features and an opportunity to reduce RF power consumption significantly.

Most of the story has focused on PPA (power-performance-area) enhancements, but I see two aspects of this people may have overlooked. To prove out the 22FDX process, GF decided to tape out a baseline implementation for comparison. The starting point was the same: a quad-core Cortex-A17 using the same processor core macro.


However, taking full advantage of 22FDX is not as simple as dropping in a 28SLP design. Details of body-bias routing come into play. We’ve seen the above picture before as well. One can apply reverse body-bias (RBB) to raise VT and lower leakage, or apply forward body-bias (FBB) to lower VT and increase maximum frequency. FBB uses a flipped-well architecture where the nMOS transistor sits on the N-well and the pMOS transistor sits on the P-well.

Winkler launches into an overview of how GF has teamed with Cadence on tools handling the details of body-biasing and other details of the 22FDX design flow. Philosophically, GF chose to implement one unified body-bias scenario for the Cortex-A17 baseline tests in 22FDX. They placed each of the cores on its own power domain, and brought in 5 pairs of body-bias nets with an outer ring approach (the white lines around the “non-CPU” block and the boundary of the four cores).


One of the interesting points is the body-bias networks are known to the design flow. GF leverages support for UPF in the Cadence platform (UPF scripts were heavily used), as well as multi-corner PVT and PVTB support. There is also discussion of the details of handling cache. In this implementation, there are 14 different L1 cache macros, and one L2 cache macro. Each has to be supported for periphery body-biasing and bitcell array body-biasing, leading to the need for 5 body-bias net pairs. The routing has to obey high-voltage spacing rules.

After the extensive discussion of how they added body-biasing to a quad-core Cortex-A17 in 22FDX, I got the distinct feeling that it is very hard to compare this big implementation apples-to-apples to the 28SLP baseline because no specific results were shared. Winkler switches to another story we’ve seen before, a PPA comparison on Cortex-A9 which is much simpler. The punchline of that story is for the same clock speed, the 22FDX version of the Cortex-A9 uses 45% less power and 45% less area – using RBB. One could choose to use FBB, and in that same 45% less area get 30% more frequency at the same power point.

That leads to what I think are the two main takeaways of 22FDX. To change the PPA target on bulk nodes, the implementation has to change. On 22FDX, using body-bias (possibly dynamically under software control) one can slide the same implementation up and down the power-frequency curve. Also, up front choices of either RBB or FBB can have a major impact – for example, in the same SoC on 22FDX a big Cortex-A17 cluster could use FBB for maximum performance, and a LITTLE Cortex-A9 cluster could use RBB for minimum power consumption.


You can see the entire GF webinar on 22FDX in the clear on YouTube:
How to Implement an ARM Cortex-A17 Processor in 22FDX FD-SOI Technology

There’s also much more information about 22FDX on the GF website. The investment in getting into 22FDX and having control over tuning an implementation using body-biasing puts it in a unique spot. Instead of just chasing smaller and smaller geometries, 22FDX captures the costs of a now-mature 28nm node with significant performance advantages.

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Eight Improvements for PCB Software

Eight Improvements for PCB Software
by Daniel Payne on 05-04-2016 at 12:00 pm
Categories: Cadence, EDA

I first met John Durbetaki at Intel in Aloha, Oregon and we both had a keen interest in the nascent personal computer industry. My first PC was made by Radio Shack and dubbed the TRS-80 which maxed out at 48KB of RAM. I kept watch on Durbetaki as he left Intel and formed his own company OrCAD in 1985 to serve the needs of PC-based CAD software. OrCAD started out with just schematic capture, but then added simulation and PCB layout tools, finally being acquired by Cadence in 1999. Last week I spoke with two folks at Cadence about what’s new with their PCB software, and they shared the eight latest improvements. Cadence divides up the PCB world into two different product lines based on design complexity: OrCAD for low-end designs, and Allegro for high-end designs.

Hemant Shah started out with an update on what’s new with Allegro, their PCB tools for enterprise users. The four latest improvements in Allegro 17.2-2016 are:

[LIST=1]

  • Advanced flex and rigid-flex designs
  • New concurrent team design option
  • Interoperable Allegro and Sigrity technology
  • Higher performance and capacity

    Flex
    A lot of our consumer electronics devices use flex and rigid-flex designs: watches, glasses, tablets, phones. By laying electronic components on top of flexible cable you can pack more features into a smaller space. This 17.2 release for Allegro lets you define stack-up by zones, perform DRC violations for flex layers and perform arc-aware routing.

    Concurrent Team Design
    Divide and conquer is a proven approach to getting more work done in a shorter time, and so now you can use Allegro in either an ad-hoc team design (no setup) or a structured team design (some setup). When you divide the PCB project between five designers, then routing can be done concurrently which saves up to 80% in time versus the old way of doing a combined routing.

    Allegro and Sigrity
    Cadence purchased Sigrity back in 2012 because of their signal integrity tools for PCB designers, and now this integrated technology ensures that your critical high-speed signals are meeting the performance criteria with features like:

    • Tabbed routing
    • Custom return path via structures
    • Extended in-design rules for backdrilled vias
    • PI (Power Integrity) for PCB designers

    Performance and Capacity
    The 17.2 release now supports a 64-bit OS, so RAM can be up to 18 Quintillion and database sizes up to 3GB. Any of your CPU-intensive applications will see performance gains. Two additional improvements are a new cross-section editor, and a new padstack editor.

    Up next was Kishore Karnane and he talked about four new improvements to the OrCAD 17.2 release:

    [LIST=1]

  • Design differencing in Capture
  • Advanced annotation and auto-referencing in Capture
  • PSpice for virtual prototyping
  • PCB Designer for advanced flex and rigid-flex designs

    The OrCAD tools are ideally suited for designs in the IoT marketplace because of the ease of use, productivity and low cost.

    Design Difference
    Often during the design process there have been multiple changes made, but you want to know how many changes and where each one is located. This graphical design difference feature will show you exactly what has changed, both logically and graphically, saving time so that you don’t have to attempt a manual comparison.

    Advanced Annotation
    In a PCB design every electrical component has a unique instance name, so you can either assign these instance names manually or use some automation. With OrCAD 17.2 you have plenty of automation for instances:

    PSpice for Virtual Prototyping
    IoT systems typically have analog sensors, processors, peripherals, etc. PSpice can simulate all of the mixed-signal sensors, then you can simulate your RTL and TLM with the Incisive simulator as shown below:

    You can even swap out your controller virtual platform with the actual hardware by using DMI through an Arduiono board.

    PCB Designer with flex
    Remember those new flex and rigid-flex features in Allegro? Well, you also get the same thing in OrCAD now. Teams that start a project with OrCAD can even decide to upgrade and use Allegro, because they’ve made this a scalable transition.

    Summary
    The PCB marketplace has changed dramatically since the 1980s and Cadence has kept up with current trends by offering two product lines in OrCADand Allegro, so choose the one that best fits your technical needs and budget.

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    Is Tesla Making Their Own CPUs?

    Is Tesla Making Their Own CPUs?
    by Daniel Nenni on 05-03-2016 at 4:00 pm
    Categories: Arm, Automotive

    One of the benefits of administering a leading semiconductor design enablement portal is that I get to see the traffic patterns then try and figure out what’s behind them. For example, a Cupertino domain has been reading all of our automotive content very thoroughly. We also get hits by Google.com, Amazon.com, and dozens of other Fortune 1000 domains from around the world that are not traditional semiconductor companies. Another more recent SemiWiki fan is a car company here in Silicon Valley who is consuming our semiconductor design enablement content. So you have to ask yourself, “Self, what in the heck is going on here?”

    In case you missed the news from Tesla back in January:

    Jim Keller is joining Tesla as Vice President of Autopilot Hardware Engineering. Jim will bring together the best internal and external hardware technologies to develop the safest, most advanced autopilot systems in the world.

    How good is Jim Keller? Jim does not have a LinkedIn profile but he does have a wiki page, that’s how good he is! Jim is a bit famous here in Silicon Valley for his work on the DEC Alpha, the AMD K7 and K8 architectures, and the ARM based Apple A4 and A5 SoCs. Jim and his team landed at Apple as a result of the P.A. Semi acquisition which you can read about in our book “Mobile Unleashed” chapter 7 “from Cupertino”:

    Dan Dobberpuhl, of StrongARM fame, formed fabless firm P. A. Semi in 2003 with industry veterans including Jim Keller and Pete Bannon. They embarked on research of Power Architecture, creating the PA6T core and the highly integrated PWRficient family of processors. PWRficient featured an advanced crossbar interconnect along with aggressive clock gating and power management. Its near-term roadmap had single and dual 2 GHz 64-bit cores. The approach delivered similar performance to an IBM PowerPC 970 – the Apple G5 – at a fraction of the power consumption. This made PWRficient well suited for laptops, or embedded applications… Unexpectedly, Apple bought P. A. Semi and many of its 150 employees in April 2008 for $278M…

    At Apple and P.A. Semi:

    Keller was most recently a director in the platform architecture group at Apple focusing on mobile products, where he architected several generations of mobile processors, including the chip families found in millions of Apple iPads, iPhones, iPods and Apple TVs. Prior to Apple, Keller was vice president of design for P.A. Semi, a fabless semiconductor design firm specializing in low-power mobile processors that was acquired by Apple in 2008. While there, he led the team responsible for building a powerful networking System on a Chip.

    In August of 2012, Jim went back to AMD to build a team and develop an ARM-based server processor (Opteron) which has just started shipping. Next, Jim’s team did a refresh of the x86 core architecture (Zen) which is being built on GF 14nm due out later this year. The latest data points (from SemiWiki and LinkedIn) show that quite a few members of his team from AMD have joined Jim at Tesla, which should make NVIDIA quite nervous since Tesla cars currently use NVIDIA chips.

    And that ends the latest episode of “As the Chip Turns”.

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    BLDC motor control kit targets power savings

    BLDC motor control kit targets power savings
    by Don Dingee on 05-03-2016 at 12:00 pm
    Categories: Foundries

    We tend to focus on connectivity and sensors for the IoT, however there is a third element to what I call the “Edge Device Triad” that is just as important: actuators. Making things move with microcontrollers (MCUs) is a science in and of itself. For small size and low weight combined with decent mechanical power, designers are opting for brushless DC (BLDC) motors in many applications.

    BLDC motor control is complex. There are numerous variables and approaches to deliver precise motion with efficiency. Fortunately, an ultra-low-power ARM processor core such as a Cortex-M0+ provides enough computational power to run advanced algorithms, and there are many Cortex-M0+ MCUs out there. The question for how good an MCU is at BLDC motor control comes down to how capable its integrated peripherals are, and how well performance can be visualized and optimized.
    Low power motor control isn’t just a nice thing to have – in some areas, regulation is moving in. I was recently at the IEEE Electronic Design Process Symposium in Monterey, and one of the examples cited was Japan’s Top Runner program. There are Top Runner energy consumption reports on every type of major home appliance and many smaller appliances. We were discussing printers, and that report calls for an efficiency improvement for devices shipped in FY2017 of 41.6% compared to the FY2007 baseline.

    Printers are just one application for BLDC motors. Many other common devices are turning to BLDC motor implementations, such as handheld power tools, personal appliances including shavers and toothbrushes, robotic vacuums, drones and remote control toys, low-voltage pumps, and more. Often these devices are battery powered, with recharging or battery replacement requirements a key metric in usability and overall customer satisfaction.

    Not all of us are motion control experts. Finding the right combination of pieces to quickly execute a BLDC motor control design can be challenging. Atmel, a wholly owned subsidiary of Microchip Technology Inc., has been at work kitting the pieces needed, starting with their SAMD21 MCU. We first covered this part about two years ago (in my blog “What’s not quite MCU, and not quite SoC?”), noting the high speed bus matrix and the deep roster of peripherals. The timer blocks support dead-time insertion and complimentary outputs needed for motor drive. The analog subsystem integrates accurate internal references for precision. A unique feature, the Atmel Event System, focuses on real-time reaction to events without imposing CPU interrupts.


    The SAMD21 is at the center of the new ATSAMD21BLDC24V-STK platform, pictured above. The kit hardware includes the MCU board, a 24V motor driver board, an AC/DC adapter for power, and a small BLDC motor.

    Software support for the ATSAMD21BDLC24V-STK is what takes the complexity away for designers. Atmel Studio comprehends the hardware for development and debug. Within the Atmel START and Atmel Software Framework are example projects dedicated to BLDC motor control. Full source code is provided for sensorless field-oriented control (FOC) and sensored block commutation, so developers can pull the kit out of the box and start talking to a motor. The Atmel Data Visualizer lets users control motor speed and direction while monitoring speed and power consumption via a GUI.


    Atmel is extending this motor control kit concept to other family members soon, including the SAMC21 and SAMD21L. They are also working on additional motor control algorithms, and a new high-voltage motor control interface with up to 400V drive capability. Atmel currently supports safety requirements with a certified IEC 60730 Class B library.

    We’ve been discussing the trend away from “just chips” (although those are really important) and toward more system-centric design enablement. We expect this to become table stakes, where MCU and SoC vendors will have to assemble and optimize hardware/software combinations for specific vertical applications to secure design-ins. It’s good to see Atmel supporting this part of my Edge Device Triad helping make actuators more efficient. Power savings add up quickly when scaled across millions of devices, and designers are well-served to be proactive in lowering power consumption.

    More on the Atmel ATSAMD21BDLC24V-STK is available online.

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    Here’s the advantage that keeps Silicon Valley ahead of the world

    Here’s the advantage that keeps Silicon Valley ahead of the world
    by Vivek Wadhwa on 05-03-2016 at 7:00 am
    Categories: General

    A trait shared by the fastest growing and most disruptive companies in history – Google, Amazon, Uber, AirBnb, and eBay – is that they aren’t focused on selling products, they are building platforms. The ability to leverage the network effects of a platform is something that the technology industry learned long ago – and perfected. It is what gives Silicon Valley an unfair advantage over competitors in every industry; something that is becoming increasingly important as all information becomes digitized.

    A platform isn’t a new concept, it is simply a way of building something that is open, inclusive, and has a strategic focus. Think of the difference between a roadside store and a shopping center. The mall has many advantages in size and scale and every store benefits from the marketing and promotion done by others. They share infrastructure and costs. The mall owner could have tried to have it all by building one big store, but it would have missed out on the opportunities to collect rent from everyone and benefit from the diverse crowds that the tenants attract.

    Apple learned this the hard way in the 1980s when it created the first versions of the Macintosh. It built its own proprietary, closed, hardware, operating system, and applications. Bill Gates, on the other hand, realized that key to power and profit was the operating system and a thriving ecosystem. He designed Microsoft Windows as an open system in which other players could provide the hardware and software. The more programs that ran on Windows, the more users wanted it, and therefore more developers created applications. Windows became a near monopoly the 90s—while Apple came close to bankruptcy.

    Fortunately for Apple, by 2007, Steve Jobs had figured out Microsoft’s advantage. He built the iPhone App Store and iTunes as open platforms on which other players could provide content. The top five mobile phone carriers—Nokia, Samsung, Motorola, Sony Ericsson, and LG—had owned 90 percent of the industry’s profits. Yet Apple was able to leap ahead and capture literally all of this.

    The power of platforms is explained in a new book, Platform Revolution: How Networked Markets are Transforming the Economy and How to Make Them Work for You, byGeoffrey Parker, Marshall Van Alstyne, and Sangeet Choudary. The authors show how platform businesses bring together producers and consumers in high-value exchanges in which the chief assets are information and interactions. These interactions are the creators of value, the sources of competitive advantage.

    Apple was able to connect app developers with app users in a market in which both sides gained value and paid it a tax. As the number of developers increased so did the number of users. This created the “network effect” — a process in which the value snowballs as more production attracts more consumption and more consumption leads to more production.

    Just as malls have linked consumers and merchants, newspapers have long linked subscribers and advertisers. What has changed is that technology has reduced the need to own infrastructure and assets and made it significantly cheaper to build and scale digital platforms.

    Traditional businesses, called “pipelines” by Parker, Van Alstyne, and Choudary, create value by controlling a linear series of processes. The inputs at one end of the value chain, materials provided by suppliers, undergo a series of transformations to make them worth more. Apple’s handset business was a classic pipeline, but when combined with the App Store, the marketplace that connects developers with users, it became a platform. As a platform it grew exponentially because of the network effects.
    The authors say that the move from pipeline to platform involves three key shifts:

    [LIST=1]

  • From resource control to orchestration. In the pipeline world, the key assets are tangible – such as mines and real estate. With platforms, the value is in the intellectual property and community. The network generates the ideas and data – the most valuable of all assets in the digital economy.
  • From internal optimization to external interaction. Pipeline businesses achieve efficiency by optimizing labor and processes. With platforms, the key is to facilitate greater interactions between producers and consumers. To improve effectiveness and efficiency, you must optimize the ecosystem itself.
  • Value the ecosystem rather than the individual. Rather than focusing on the value of a single customer as traditional businesses do, in the platform world it is all about expanding the total value of an expanding ecosystem in a circular, iterative, and feedback-driven process. This means that the metrics for measuring success must themselves change.

    Companies such as Walmart, Nike, John Deere, and GE are working towards building platforms in their industries. John Deere, for example wants to be a hub for agricultural products. But not every industry is ripe for platforms because the underlying technologies and regulations may not be there yet.

    In a paper in Harvard Business Review,on “transitional business platforms” Kellogg School of Management professor Robert Wolcott illustrates the problems that Netflix founder Reed Hastings had in 1997 in building a platform. Hastings had always wanted to provide on-demand video, but the technology infrastructure just wasn’t there when he needed it. So he started by building a DVDs-by-mail business — while he plotted a long-term strategy for today’s platform. According to Wolcott, Uber has a strategic intent of providing self-driving cars, but while the technology evolves it is managing with human drivers. It has built a platform that enables rapid evolution as technologies, consumer behaviors, and regulations change.

    Building platforms requires a vision, but does not require predicting the future. What you need is to understand the opportunity to build the mall instead of the store and be flexible in how you get there.

    For more, follow on Twitter: @wadhwa and visit my website: www.wadhwa.com

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    Cadence loads up on MACs for vision with CNNs

    Cadence loads up on MACs for vision with CNNs
    by Don Dingee on 05-02-2016 at 4:00 pm
    Categories: Cadence, IP, Mobile

    For vision DSP IP running convolutional neural networks (CNNs), a big driver of performance is increasing the bits processed per cycle with parallel MACs. Tom Simon did a great job in recent posts of introducing CNNs at a high level, so I’ll look at what is architecturally behind Cadence’s latest announcement: the Tensilica Vision P6 DSP. Continue reading “Cadence loads up on MACs for vision with CNNs”

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    How to Deal With Seven Design Closure Issues

    How to Deal With Seven Design Closure Issues
    by Tom Simon on 05-02-2016 at 12:00 pm
    Categories: Consensia, EDA

    The challenge of tracking design progress is a shared problem for individual designers, team leaders, and project managers. At each level the ability to step back from just reviewing error log files and seeing the arc of the whole design as it moves forward is valuable. The difficulty of seeing the whole picture is exacerbated when design teams for a project are scattered around the world. To better understand the nature of the problem, Consensia surveyed a number of their customers to uncover what had been their biggest delay factors in getting to design closure. They learned some pretty interesting things.

    First let’s back up and talk a little bit about Consensia. They are a channel partner with Dassault, which offers a suite of tools for managing design flows. A big part of the value of a design management system is the ability to track progress of the design process. Consensia delivers solutions based on Pinpoint, which offers a view of the design process that is accessible across design teams, project teams and geographies.

    So, what did they learn from the survey? First off, designs have a tendency to appear 95% done for about 30% of the design cycle. Another big hindrance is trying to figure out where to start when confronted with hundreds of timing violations. The next problem customers had encountered was being limited in the number of “what if” experiments they were able to try given looming tape out deadlines. Another issue that came up repeatedly was communication and time zone barriers between ASIC and layout designers. Late stage power and signal integrity issues also were mentioned. Rounding out the list was needing to take time away from design to prepare for design reviews and the necessity of tying up expensive and limited EDA tools just to view and brainstorm solutions to issues.

    Before talking about how these problems might be resolved, let’s dig in a bit and look at how Consensia’s Pinpoint works. It offers a tool agnostic design collaboration and analysis capability. Pinpoint can read design and layout data. It can parse and understand tool results from each step in the design flow. Most importantly it is web based and accessible by all the stake holders in the design process. Due to its ability to read reports and data from a variety of tools, it affords ways of looking at the design that are not available from the individual tools in the flow. Because it is collaborative the information it has aggregated can be seen and used across geographic and functional boundaries.

    Going back to the list of obstacles, using real metrics from tool runs visible, project status can be observed much more accurately. This should mean fewer surprises when project milestones are due. As for where to start when confronted with a mass of timing violations, Pinpoint’s timing report for the whole design can enable a structured approach to timing closure. Also visualization of violating paths on the layout can lead to design insights that can greatly facilitate resolutions.

    Pinpoint also lets engineers keep track of tool runs and their input data versions, making it easier to hone in on the best results. Because it is web based, Pinpoint allows full access to design analytics anywhere it is needed. This is a huge benefit when information on design progress and convergence is needed for design reviews and internal discussions. All of this is accomplished without the need to tie up EDA tool licenses just to review design status.

    Pinpoint presents the data from tool runs and design progress visually and interactively to help establish an extremely accurate assessment of all the open issues, making tracking design progress easier and more reliable. Detailed reports including timing and physical verification are available. Pinpoint also graphs design metrics over time, so that trends in the design are evident.

    Consensia heard feedback from their customers that they have seen savings of 12 to 18% in design time. It would seem that applying design aware analytics to the semiconductor design process is valuable. For more information on Pinpoint from Censensia, take a look at their website.

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    From Simulation to Emulation: 3 Steps to a Portable SystemVerilog/UVM Testbench

    From Simulation to Emulation: 3 Steps to a Portable SystemVerilog/UVM Testbench
    by Hans van der Schoot on 05-02-2016 at 7:00 am
    Categories: EDA, Siemens EDA

    If your team is building large, complex designs that require millions of clock cycles to fully verify, you need both simulation and emulation.

    Using emulation with simulation accelerates performance for dramatically reduced run times.
    Continue reading “From Simulation to Emulation: 3 Steps to a Portable SystemVerilog/UVM Testbench”

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    Mind The Gap – Boarding the Silicon Photonics Packaging Train

    Mind The Gap – Boarding the Silicon Photonics Packaging Train
    by Mitch Heins on 05-01-2016 at 8:00 pm
    Categories: Silicon Photonics


    I’ve been doing a lot of reading on silicon photonics lately and I’ve come to realize that while there is much written on the development of individual silicon photonic components and devices (modulators, photo detectors, optical amplifiers and such) that much of the cost and therefore chances of economic success of integrated photonics solutions resides not in the silicon but in packaging of these solutions. Before the photonics platform can be used photonic ICs (PICs) must be integrated to their electrical IC (EIC) counterparts and the rest of the system.

    One of the biggest challenges of this integration is getting light on and off the PIC from optical fiber. For integrated photonics this is typically done either through edge couplers or grating couplers as shown in figure 1. The tricky (and costly) part comes in ‘minding the gap’ between the relatively large optical mode of fiber to the very small optical mode of a SOI on-chip wave-guide. To put this into perspective, the diameter of a single-mode lensed telecom fiber for 1550nm light is ~3um. This must be matched up to a SOI-waveguide mode with dimensions of ~ 220nm x 450nm. That’s an area difference of almost 2 orders of magnitude (~7 million nm[SUP]2[/SUP] vs 99,000 nm[SUP]2[/SUP]). More challenging is that SOI wave-guides typically only support TE-polarized modes of light an    d the light coming in from a fiber is usually unknown and unstable requiring a mode convertor to clean up the signal before entering the waveguide. The 1db alignment tolerance for a typical edge-coupler is sub-micron (~ +/- 500nm) requiring time consuming and expensive active alignment during packaging. Additionally, these couplers usually require laser-welding to secure the lensed-fiber to the PIC as epoxy bonding suffers from small alignment drifts that would not be tolerable at these dimensions. With laser-welding comes the need for more expensive packages to mitigate thermal expansion on the optical alignment. Peter O’Brien and the packaging group from Tyndall National Institute in Cork, Ireland do a great job of explaining all of the nuances of this and more in chapter 7 of the book, Silicon Photonics III. The end result being that while edge couplers are the standard for the packaging of III-V laser devices and do a good job reducing insertion loss and giving more broadband coupling, they add a substantially increased packaging cost for integrated PICs due to their stringent alignment requirements.

    The alternative to edge couplers are grating couplers that use diffraction gratings to couple a near incident fiber-mode to the wave-guide mode (figure 2). They are typically designed as a 10um x 10um periodic array of trenches, partially etched into the silicon layer. The trenches are usually curved to focus the light to the SOI-waveguide reducing the need for long space-consuming taper structures and can be designed to do double duty by taking care of the required polarization cleanup. The 1db alignment tolerance for these couplers are ~ +/- 2.5um. While still challenging, the process of “minding the gap” here is greatly simplified and much less costly compared to edge couplers. Grating couplers have the added benefit that they are fully CMOS flow compatible and allow for wafer-scale optical access at any point on the PIC surface enabling inline testing and characterization of the PIC before dicing.

    The biggest issue with grating couplers is their relatively high insertion loss. A standard grating coupler in 220nm SOI is -3db which equates to a 50% reduction in the transmitted power. In MPW runs from imec and CEA-Leti, users have experienced insertion losses as high as -5db. Several research groups are working on this and have reported devices in the labs using bottom-reflectors that have insertion loss down to -1db but these devices have not yet seen production. The other major concern for grating couplers is the need for near incident light making for bulky and delicate vertical connections from fiber to the PIC. To “mind this gap”, a quasi-planar approach (figure 7.4) has been developed in which the fiber lies flat on the surface of the PIC with a 40[SUP]0[/SUP] polished facet that directs the fiber-mode onto the grating coupler at the correct angle. Due to their relaxed alignment constraints these connections can be made with less expensive epoxy bonding. This is especially helpful for fiber-array connections that have multiple fiber-channels in the same connector where you can amortize the cost to connect multiple channels across one alignment task. As an added bonus, grating couplers can also be used with VCSELs (vertical cavity surface-emitting lasers) that are directly flip-chipped and bonded over the PIC couplers.

    In the end, the best fiber-coupling solutions for a given PIC is strongly application and cost-dependent, but no matter what you do, to make your PIC design successful you’ll need to “mind the packaging gap” while boarding your silicon photonics train.