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TSMC Update at #53DAC!

TSMC Update at #53DAC!
by Daniel Nenni on 05-31-2016 at 4:00 pm
Categories: Events, FinFET, Foundries, TSMC

TSMC is having an interesting year for sure. I was at the TSMC Symposium in Hsinchu last week and everyone was talking about the new 16FFC process. Silicon is out and it is exceeding expectations leading some people (me included) to believe that TSMC 16FFC will be the next TSMC 28nm in regards to popularity. To be clear, 16FFC is currently the “BEST” process node in regards to PPPA (price, performance, power, and area) available today, absolutely.

The proof is in the pudding of course and that pudding will arrive via the iPhone 7 this fall and yes, I am buying an iPhone 7 Pro to match my iPad Pro which I use every day. Netflixing on an iPad Pro at 30,000+ feet, priceless! It should have a “TSMC Inside” sticker on it for sure.

Speaking of FinFETs, we have published 64 FinFET related blogs thus far starting with Tom Dillinger’s three part Introduction to FinFET Technology series. The total views for the SemiWiki FinFET blogs exceeds 500k which is a lot of reading. FinFET blogs also have low bounce rates and high time-on-page numbers which means they are very engaging. Designing with FinFETs is still a hot topic so there are certainly more blogs to come.

At DAC, TSMC pioneered the partner theater allowing the fabless semiconductor ecosystem to shine, and this year it will be no different. You can see the latest TSMC Theater schedule HERE. If you are looking for me on the DAC exhibit floor that would be a good place to start. Or wherever there is free food.

Speaking of free food, TSMC is also very busy with other DAC activities that should be of interest. You can see the agenda HERE and please note that it includes breakfast, lunch, and dinner presentations so you can also find me there enjoying the free food.

As a pre #53DAC “Designing with FinFET” primer you should catch the TSMC and Solido Collaborate for Variation-Aware Design of Memory and Standard Cell at Advanced Process Nodes webinar on Wed, June 1st, 2016 10:00 AM – 11:00 AM PDT. If the time does not work for you, sign up anyway and they will send you a link to the replay:

“Variation effects have an increasing impact on advanced process nodes, and at each, new sources of variation must be considered. Furthermore, increased competition is forcing tighter design margins to make high-performance, low-power, low-cost products. Designers must now do more variation analysis than ever to achieve these tighter margins, using advanced variation-aware technology for speed, accuracy and coverage to deliver competitive chips on schedule.

This webinar will discuss how TSMC and Solido collaborate to offer variation-aware design techniques for memory and standard cell with TSMC advanced processes using Solido’s new Variation Designer 4.”

And don’t forget that SemiWiki will again be hosting a DAC Networking reception on Wednesday night from 6:00pm to 7:00pm in the Trinity Street Foyer. This year we will be giving away copies of our new book “Prototypical”. My beautiful wife and I hope to see you there!

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Bringing Human-Like Intelligent Vision Processing to Low-Power Embedded Systems

Bringing Human-Like Intelligent Vision Processing to Low-Power Embedded Systems
by Daniel Nenni on 05-31-2016 at 12:00 pm
Categories: Ceva, IP

Semiconductor IP has always been one of the most interesting topics on SemiWiki. Since going online in January of 2011 there have been a total of 592 IP related blogs that have been viewed 2,581,118 times. 79 of those blogs have been about CEVA, the number one licensor of digital signal processing (DSP) IP for a wide range of power-efficient, intelligent, and connected devices for Mobile, consumer, automotive, industrial and IoT applications. You can see the full list of SemiWiki Semiconductor IP blogs HERE and CEVA blogs HERE. CEVA specific traffic on SemiWiki is second only to ARM in our IP category. CEVA is also very good at Infographics!

Bringing Human-Like Intelligent Vision Processing to Low-Power Embedded Systems

As you probably know, one of my strange hobbies is listening to quarterly investor calls of companies that I have intimate knowledge of. As an insider it is interesting to see if what I know matches up to what the company says publicly. Which brings us to CEVA, one of my favorite companies to watch because what they say actually matches what I know, absolutely.

CEVA had a great 2015 with:

  • Quarterly revenues of $16.1 million, up 16% year-over-year
  • Strong adoption of imaging & vision; five agreements for CEVA-XM4
  • Annual revenue growth of 17% year-over-year
  • Annual non-GAAP EPS growth of 51% year-over-year

Gideon Wertheizer, Chief Executive Officer, stated: “We are extremely pleased with our strong finish for the year, as both licensing and royalty revenues delivered year-over-year growth. In licensing, the adoption of our CEVA-XM4 imaging and vision DSP by five licensees during the quarter expands our footprint in the growing use of advanced camera processing in automotives, drones and smartphones. In royalties, our quarterly royalty revenues reached its highest total since 2012, driven by record CEVA-powered smartphone shipments of more than 92 million units.”

In Q1 2016 the CEVA success continues:

  • All time-high revenues of $16.5 million, up 19% year-over-year
  • GAAP and non-GAAP EPS growth of 350% and 113% year-over-year
  • Quarterly record of 35 million CEVA-powered LTE devices shipped

Yaniv Arieli, Chief Financial Officer of CEVA, stated: “In addition to another strong licensing quarter, our market share expansion in LTE continues, with a record thirty five million shipped units reported in the quarter, resulting in 31% year-over-year royalty revenue growth. Reflecting our confidence in our business, we repurchased approximately 180,000 shares of our common stock during the quarter for an aggregate consideration of approximately $3.4 million. At the end of the quarter, our cash balance, marketable securities and bank deposits totaled $137 million.”

You can meet with CEVA at the Design Automation Conference next week where they will be demonstrating in the BRITE Semiconductor booth (#1520). CEVA will show a new and exciting Deep Neural Network demo running on CEVA’s award winning Imaging Processor (CEVA-XM4). Hope to see you there!

About CEVA, Inc.
CEVA is the leading licensor of signal processing IP for a smarter, connected world. We partner with semiconductor companies and OEMs worldwide to create power-efficient, intelligent and connected devices for a range of end markets, including mobile, consumer, automotive, industrial and IoT. Our ultra-low-power IPs for vision, audio, communications and connectivity include comprehensive DSP-based platforms for LTE/LTE-A/5G baseband processing in handsets, infrastructure and machine-to-machine devices, computer vision and computational photography for any camera-enabled device, audio/voice/speech and ultra-low power always-on/sensing applications for multiple IoT markets. For connectivity, we offer the industry’s most widely adopted IPs for Bluetooth (BLE and Dual Mode), Wi-Fi (802.11a/b/g/n/ac up to 4×4) and serial storage (SATA and SAS). Visit us at www.ceva-dsp.com and follow us on Twitter, YouTube and LinkedIn.

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Why USB 3.1 Certification is a “Must Have”?

Why USB 3.1 Certification is a “Must Have”?
by Eric Esteve on 05-31-2016 at 7:00 am
Categories: IP, Synopsys

USB 3 protocol is now height years old, but USB 3.1 is much more recent (2014). The adoption behavior for USB protocol is unique, as USB 2.0 bandwidth (480 Mbps) is largely enough for certain applications. Nevertheless we have seen the sales for USB 3 IP passing the USB 2 in value during 2014, and the total USB IP segment becoming the largest of interfaces segment in 2015.

USB 3.x IP sales are constantly growing and we can expect applications relying on USB 3.0 (5 Gbps) to upgrade to USB 3.1 (10 Gbps). When deciding to integrate complex interface IP running at 10 Gbps, the first question coming in the selection process is: has this IP passed the qualification? Because we are talking about interface IP, you a priori don’t know the quality of the USB IP your chip will interface with. The only way to make sure that both function will smoothly communicate is the qualification process, supported by USB-IF. Synopsys has announced that their DesignWare USB 3.1 controller and PHY passed all protocol, electrical and interoperability tests to become the first IP to achieve USB-IF certification. As we will see in this paper, this long process is all but an easy trip.

USB 3.1 Gen 2 significantly increases the effective data rate to 10 Gbps for the ubiquitous USB protocol, while maintaining backward compatibility with USB 3.0 and 2.0. USB 3.1, in combination with USB Type-C and Power Delivery. We have to keep it mind that a modern (interface) IP is no more a simple bunch of source code RTL: complete USB 3.1 solution includes controller, PHY, verification IP, IP subsystems, IP prototyping kits and IP software development kits.

Controller: The preparation for compliance testing starts together with the project schedule definition, and will apply to every phase of the controller development, helping to drive the schedule and collaboration process with the engineering teams involved in deliverables such as the PHY, simulation verification IP (VIP) models and software drivers. The ASIC design engineers task become a compliance-driven design approach.

PHY: The PHY testchip silicon will be exhaustively verified within Synopsys laboratories before going to certification, thanks to the PHY architecture which allows for the transmitter (TX) and receiver (RX) of the PHY to be operated standalone, with pattern generators and pattern matchers incorporated into the PHY itself.

Verification IP (VIP): The verification phase of a complex protocol such as USB 3.1 Gen 2 represents a paramount effort where constrained random regression approaches can take considerable time to go through thousands upon thousands of coverage points. Parallel efforts focused on direct test scenarios that address compliance test simulation environments are actively sought after to improve the process. For example, the link layer compliance test is a perfect candidate for writing direct test cases.

IP Prototyping Kit: FPGA-based prototyping provides cycle-accurate, high-performance execution and real-world interface connectivity. When the controller has been integrated in FPGA, the PHY Testchip has been mounted on the same board, the full IP Prototyping Kit, pre-compliance testing can begin.

Although the Synopsys methodology minimizes roadblocks and accelerates processes, it is Synopsys’ array of industry-tested tools and prototyping environments, along with its experienced team, that results in IP validation, verification, and compliance (see above Figure). Synopsys has proven its methodology by being the first IP companies to achieve certification for USB 3.1 Gen2.

The DesignWare USB 3.1 Controller IP implements power management features, including standard USB power savings modes and controller hibernation. DesignWare USB 3.1 PHYs consume less than 50 mW power at 10 Gbps speeds in 14/16-nm FinFET process technologies. The IP supports the IEEE 1801 standard Unified Power Format (UPF) for low-power SoC design flows. The controllers are backward-compatible with DesignWare USB 3.0 software stacks and device class protocols. No doubt that the complete USB 3.1 solution from Synopsys will allow the company to keep his leading position in USB IP segment with more than 80% market share in 2015!

– See more about Synopsys certification strategy and process at: http://www.synopsys.com/Company/Publications/DWTB/Pages/dwtb-challenges-usb-certification-2016q2.aspx#sthash.j0wOVnaV.dpuf
– Synopsys PR about sertification: Synopsys’ 10 Gbps USB 3.1 IP First to Pass USB-IF Certification

From Eric Esteve from IPNEST

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Finding IoT patents that are not worthless and weak

Finding IoT patents that are not worthless and weak
by Don Dingee on 05-30-2016 at 4:00 pm
Categories: IoT

Is that an IoT patent application I see pinned to your desktop? A new analysis by technology intellectual property legal experts LexInnova confirms IoT patents are being generated rapidly – and looks at which classes of patents are likely to be worth something in acquisition or litigation. Continue reading “Finding IoT patents that are not worthless and weak”

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Arteris Unveils Solution for Heterogeneous Cache Coherent SOC’s

Arteris Unveils Solution for Heterogeneous Cache Coherent SOC’s
by Tom Simon on 05-30-2016 at 12:00 pm
Categories: Arteris, IP

Designing SOC’s for markets like automotive and mobile electronics requires taking advantage of every opportunity for optimization. One way to do this is through building a cache coherent system to boost speed and reduce power. Recently, NXP decided to go about this on their automotive MCU based SOC’s by using Arteris’ just-announced Ncore cache coherent interconnect. Let’s dig into the Arteris announcement to see what advantages there were for NXP in going this route.

In all likelihood, many of the blocks they were using already had a cache coherent interface, for instance something like the AMBA ACE from ARM. Nevertheless, it might be that not every IP block used in the design is using ACE – it could be a heterogeneous cache coherency environment. Even ARM appreciates that this can happen. ARM’s Charlene Marini, Vice President Segment Marketing states in the Arteris Ncore announcement that their collaboration with Arteris “will further drive innovation in heterogeneous cache coherent systems.”

Ncore can be configured to so that agents support a variety of cache coherency protocols. Ncore also can be configured to handle different numbers of ports on an individual IP and it supports different cache sizes on different agents. For IP that does not support local caching, nCore allows designers to add proxy caches for these IP blocks that will be fully coherent, thus providing improved performance to more of the SOC’s blocks that perform memory access.

Beyond the obvious benefit to non-cache IP of less time on fetches for cached data there are several less obvious advantages. The bridge agents used to interface to non-coherent IP blocks can do prefetching on initial reads to lower DRAM fetch overhead. Also writes can be gathered to make saving data to DRAM more efficient.

One of Ncore’s significant innovations is the addition of multiple snoop filters. Each snoop filter can be individually configured to be the optimal size. This is a more efficient system than relying on a single larger snoop filter.

Ncore is real estate efficient because it is distributed and requires fewer wires in routing channels. Building it on top of their FlexNoC transport IP makes closing timing easier and optimizes allocation of interconnect resources. The use of FlexNoC also permits mixing agents with different clock and power domains so it can further reduce system power consumption.

Anyone who has used FlexNoC knows it has a sophisticated user interface for SOC architects to assist in planning sizing and placement of data communication resources while taking into consideration timing, bandwidth, distance, area and power. FlexNoC is so efficient in using routing channels that communication and repeater logic can go in the channels with signal lines. This is in part due to careful consideration of layer assignment for the data lines and communications modules.

Ncore extends and coexists with FlexNoc and uses an integrated design planning platform, making the SOC architect’s job easier and providing more predictability to the overall process.

Arteris has broken new ground with Ncore, but history has favored that companies that focus on solving customer design problems instead of just providing products. Also it is good to see that they have been working with customers and have successes to report at their Ncore product announcement. More information and product details are available on the Arteris website.

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DRC Concept for IP Qualification and SoC Integration

DRC Concept for IP Qualification and SoC Integration
by Pawan Fangaria on 05-30-2016 at 7:00 am
Categories: EDA, Fractal Technologies

In the history of semiconductor design and manufacturing, the age-old concept of DRC rule-deck qualification for handshake between design and manufacturing still applies strongly to produce working silicon. In fact, DRC clean GDSII works as the de facto golden gate between a design and a foundry for manufacturing the chip for that design.

Today, we are designing at system-level, what we call SoCs. In an SoC, we are essentially interconnecting many different IPs together, and those IPs can be sourced in different formats from multiple vendors across the world. Looking at it from the top, the concept of ‘DRC clean layout at cell or macro level’ can be very well applied to error-free IP interconnection at the system level.

For an IP to be placed within an SoC without any error there must be a set of rules for IP qualification from the IP integrator’s perspective. These IP qualification rules can be used as golden handshake between the IP providers and the SoC integrators. These rules are framed based on the IP databases and formats used, tools applied for the design, internal consistency between the IP, design, and the tools, and so on. Like DRC for a particular technology, these IP rules for a particular design can mature over a period of time with continuous improvement.

So, do we have something in the market to ease and accelerate the IP integration process by providing a correct-by-construction IP which can be simply dragged and dropped into an SoC? Things are moving in the right direction with Fractal Technologiesadding Transport[SUP]TM[/SUP] formalism to their IP signoff solution along with their flagship product Crossfire[SUP]TM[/SUP].


Fractal Transport captures and exchanges IP qualification requirements, and provides input to Crossfire for IP sign-off between semiconductor design partners. The IP integrators use Transport formalism to specify their needs such as IP completeness (database, models, etc.), IP integrity (timing, power trend, cell elements, etc.), and IP integration (compatibility between IP and design tools, clock domains, etc.) in a formal way. By using Transport they can represent the IP qualification requirements in a generic way and maintain them to share with multiple IP providers.

The Transport maps the IP quality checks (that may be applied to qualify an IP) with the databases and models that are supplied with IP releases. This allows the IP integrators to capture the checks that are appropriate for various models in their IP release.

In Transport, the qualification rule-deck consists of classes and checks applied to those classes. A class is a collection of objects such as “all Liberty files”, “all noise-arcs”, and so on. Rules from the Crossfire rule-database are mapped to these classes to specify the individual checks in the actual instance of an IP release. Today, Crossfire defines about 250 different rules, each of which can be instantiated in Transport multiple times as different checks as part of different classes.

A key advantage of this concept is that the Transport qualification rule-deck can be continuously improved with repeated occurrences of particular design situations and re-used over multiple releases of IPs. The Transport and Crossfire are used together to detect errors in an IP, get them fixed, and signoff the IP. There is a mechanism in Transport to capture certain waiver specific to an IP. Also, the IP suppliers and integrators can decide for Transport deck to automatically capture exceptions for frequently occurring waivers, thus improving practical efficiency of Transport.

The Transport allows IP qualification rule-deck to become independent from the actual IP database or IP provider, thus letting it mature over time with new additions and modifications. A mature Transport rule-deck for a certain class of IPs can enable second sourcing of IPs without risk to the tape-out schedule.

This is a novel initiative from Fractal Technologies for IP qualification handshake between IP providers and integrators in an standardized way. Once this concept matures, it can open up a new chapter in the IP world for seamless integration of an IP into an SoC.

Fractal will be demonstrating the Transport technology along with the new capabilities in Crossfire at 53[SUP]rd[/SUP] DACin Austin, June 5-9, at their booth #1718. Stop by the booth to know more about this technology. Also, read their latest whitepaper HERE.

More Articles from Pawan

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Aart de Geus, Technomics and #53DAC

Aart de Geus, Technomics and #53DAC
by Daniel Payne on 05-29-2016 at 8:00 pm
Categories: Events, Synopsys

The number one EDA+IP vendor in our industry today is Synopsys, and their eloquent leader is Aart de Geus, so I expect that the Monday interview at #53DAC on June 6th will be well attended and worthwhile to witness in the DAC Pavilion, start time is 11:30AM, so arrive early to get a seat. One of Aart’s coined words is Technomics, the intersection of technology and economics, something quite relevant to Moore’s Law and the predictions of new silicon technology that is smaller, faster, lower power and cheaper to buy.

The Booth
One of the largest booths at DAC this year is from Synopsys, and in their theatre area you will enjoy hearing topics about:

  • Industry trends
  • FinFET
  • IoT
  • Automotive market

Special Events
There are eight events that you may choose to register for and attend, many of them with partners from the foundry and IP side of the business. I’ll be attending the circuit simulation luncheon on Monday.

Registration is required, just click the links above to get the process started.

Conference Sessions
Technologists will want to attend the dozens of conference sessions planned for Monday through Thursday at DAC this year. These sessions are presented by engineers at companies like:

[TABLE] style=”width: 500px”
|-
| ARM
| Breker Verification Systems
|-
| Design Rivers
| eSilicon
|-
| IBM Research
| Intel
|-
| Lattice Semi
| Leyden Technologies
|-
| MIPI Alliance
| National Chiao Tung University
|-
| NVIDIA
| Qualcomm
|-
| Samsung
| Sankalp Semi
|-
| Stanford University
| STMicroelectronics
|-

Partners & Standards
No EDA or IP vendor is an island, so having partners and using standards means that your technology fits into more flows. You’ll find Synopsys at DAC collaborating with many companies: Accellera

  • ARM
  • ChipEstimate.com
  • GLOBALFOUNDRIES
  • Samsung
  • SMIC
  • TSMC

Conclusion
You may have noticed the new tagline for Synopsys this year: Silicon to Software.DAC is certainly the biggest event for Synopsys on the silicon and semiconductor IP side of the business, however there are other conferences that they attend for the software side of the business.

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Six Reasons to Visit Cadence at #53DAC this Year in Austin

Six Reasons to Visit Cadence at #53DAC this Year in Austin
by Daniel Payne on 05-29-2016 at 4:00 pm
Categories: Cadence, EDA, Events

For bloggers like myself spending four days at #53DAC is almost a non-stop blur of activity, visiting EDA vendors, IP providers and foundries to learn about what’s happening in our semiconductor industry. Cadence is both an EDA vendor and IP provider, so DAC is a great showcase for them to tell us what’s new in 2016 and provide a roadmap of technology coming soon.
Continue reading “Six Reasons to Visit Cadence at #53DAC this Year in Austin”

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What the #3 EDA company is showing at #53DAC this year

What the #3 EDA company is showing at #53DAC this year
by Daniel Payne on 05-29-2016 at 12:00 pm
Categories: Events, Siemens EDA

I live in Tualatin, Oregon just a few miles away from the corporate headquarters of the #3 EDA company in the world, Mentor Graphics. Since DAC is fast approaching, I thought it would be useful to give you a quick overview of what Mentor is going to be talking about in Austin, Texas during June 5-9.
Continue reading “What the #3 EDA company is showing at #53DAC this year”