CEVA Dolphin Weninar SemiWiki 800x100 260419 (1)
Semiconductor Expert Forum

Posted on

My #53DAC Must See List!

My #53DAC Must See List!
by Daniel Nenni on 06-04-2016 at 7:00 am
Categories: Events

It may be hard to believe but this happens to be my thirty third Design Automation Conference. Where does the time go? Three of my kids are out of college and the last one is getting close. That is where my time has gone. The conference itself started in 1964 but my first one was in 1984 in Albuquerque, New Mexico. In fact, that was the year DAC went to the dark side and allowed sales and marketing people with booths, demos, and giveaways. The rest as they say is history, and a very colorful history indeed!

While some misinformed people say that this year there is nothing new in EDA, I seriously disagree. This year we have a disruptive technology that will change the way semiconductors are designed, absolutely!


SeaScape Platform!
This year brings big data to EDA and I say it’s about time! I sat through one of the pre-DAC briefings and it was quite exciting. All power point slides, but ANSYS assured me that they have customers that will present real usage data. You can read more about it here from Bernard Murphy and Tom Dillinger:

Rebooting EDA

“Re-Inventing” Tapeout Sign-off — Applying Big Data Techniques to Electrical Analysis

And you can speak directly to ANSYS and early customers:

To get a live update and an opportunity to question the experts on what next-generation EDA products can do for you, register for Ansys suite sessions at DAC (in-design and best practices, kicking off June 6[SUP]th[/SUP] in Austin) HERE. This will be the hottest ticket at #53DAC so reserve yours now.

Samsung Open Collaboration Theater
Samsung again has made a big investment in DAC featuring 36 different presentations for the 3 days (Mon-Wed). Details of presentations can be found at the Samsung DAC page. I gave the Samsung Theater “Best of Show” last year and I expect nothing less this year.

Samsung is also an active DAC presenter:

[LIST=1]

  • Monday 11:30am, Mentor Closed-Loop DFM Luncheon. KK Lin is presenting alongside with others
  • Tues 7:15am, SNPS breakfast event. Kelvin Low is presenting alongside with others (10nm focused)
  • Tues 1130am, SNPS Luncheon. Bonhyuck Koo (from Korea) will be presenting updates on Custom Compiler work.
  • Tues 3:30pm, ARM panel. Our packaging expert, Max Min will be on the panel
  • Tues 4pm, Mentor IoT panel. Kelvin Low will be on the panel
  • Wed 10:30am, SNPS Thought-leader sessions. Jay Um will be pesenting 28FDSOI for Automotive and IoT.
  • Wed 3:30pm, ARM panel. Kelvin Low will be on the panel on “IP re-use discussions”

    Silicon/Technology Art Show
    This is a new event at DAC and one which I think will be very entertaining. Entertaining because I am one of the judges and I’m color blind. Fortunately, my beautiful wife will be with me and she has a trained eye for colors and artsy stuff.

    The DAC Silicon/Technology Art Show will feature stunning images submitted by DAC attendees that demonstrate the beauty of everyday work in this industry. Submitted pieces will be judged in various categories and the winners for each category will be announced Wednesday, June 8 at 9:00am in Ballroom A. Awards include:

    • Best Visualization
    • Best Silicon Photo
    • Most Inspiring
    • Most Insightful
    • Most Artistic
    • Grand Prize- Best piece out of all categories

    Free “Prototypical” Book Giveaway!
    Don Dingee and I, in collaboration with S2C Inc., will be promoting our recently published book on FPGA Prototyping. This is SemiWiki’s third book in as many years and there will be more to come. Why FPGA Prototyping you ask? Simple, the semiconductor ecosystem is all about enabling design starts. As we all know it is much easier to raise money for your chip start-up if you have a working prototype and collaborating with experts will get you closer to working silicon for a minimum upfront investment.

    On Monday at 1:30pm I’ll join Don Dingee in the S2C booth #1928 for the debut of our new SemiWiki book “PROTOTYPICAL: The Emergence of FPGA-Based Prototyping for SoC Design”. We’ll be signing copies of the book (provided by S2C) and networking with attendees for a couple hours along with Mon-Ren Chene who penned the foreword.

    On Wednesday night SemiWiki will again host a book signing at the 6pm DAC reception in the Trinity Foyer. In addition to FREE food and FREE drinks, there will be FREE books (provided by S2C). The SemiWiki bloggers and my beautiful wife will be there, it would be a pleasure to meet you.

    “Mobile Unleashed” Book Giveaway!
    Solido Design Automation (booth #611) will be giving away copies of our book on the origin and evolution of ARM processors in our devices. The foreword is by Sir Robin Saxby and it currently has a 5 star rating on Amazon.com. There is a limited supply so only people who meet privately with Solido will get a signed copy. Rumor has it there will also be a copy of Mobile Unleashed in the Silvaco (booth #649) goody bag.

    Bottom line:     Hundreds of books will be given away for the greater good of the semiconductor ecosystem and we would be happy to sign them for you.

    • Posted on

    Blue Pearl adds RTL project transparency at #53DAC

    Blue Pearl adds RTL project transparency at #53DAC
    by Don Dingee on 06-03-2016 at 4:00 pm
    Categories: Blue Pearl Software, EDA, Events

    You’re an RTL pro. You know what’s inside your code, and how many bugs you’ve tracked down and exterminated along the development path, and how much work remains. So, why did the meeting notice that just popped up asking for a monthly management project review presentation ruin your day? Continue reading “Blue Pearl adds RTL project transparency at #53DAC”

    Posted on

    A Shot in the ARM for IoT

    A Shot in the ARM for IoT
    by Randy Smith on 06-03-2016 at 12:00 pm
    Categories: Arm, Events, IoT, IP

    I recently attended the IoT Developers Conference in Santa Clara, CA. There were clearly two major themes in the talks – security and low power. The volume market in IoT is in the edge node devices. These devices have two important characteristics. They acquire data which needs to be transmitted and they typically are battery-driven or even harvest their own energy. The need for security is clear if the data is sensitive (e.g., vehicle to vehicle communications, medical information, etc.) though not all applications require much security. The need for low power is also obvious for mobile or remote devices which are not plugged into a power outlet.

    A common paradigm for these edge node devices is to collect data through their sensors, store it, and then send it in packets either on demand or at some regular interval to a hub device. Of course there may also be a need for code storage, error logging, and still other storage requirements. Clearly these devices will need access to non-volatile memory. The catch is to use a memory device that also doesn’t eat up the entire power budget. Calls for such a solution, a low power non-volatile/flash memory device, have come from such industry leaders as ARM (ARM CEO Simon Segars quoted in EETimes) and Freescale (White Paper: What the Internet of Things (IoT) Needs to Become a Reality) .

    Adesto Technologies recently introduced its Ultra-Low Power Moneta™ Non-volatile Serial Memory (RM3000). This new product would seem to dramatically improve the situation for IoT system designers. The RM3000 series makes use of Adesto’s conductive bridging RAM (CBRAM) technology. They claim several advantages from using this technology amongst them, unlike flash memory there is no pre-erase requirement, it has much faster write operations (I saw a demo of this at IoT Dev Con), and it uses a much lower write voltages. Simplifying this it is faster and cheaper on the energy budget.

    This technology will start shipping as a packaged part in July 2016 in four densities – 32Kbit, 64Kbit, 128Kbit, and 256Kbit. Of course with my semiconductor IP background I had to ask if this would be coming in an IP form as well. Unfortunately, that is out on the more distant horizon. We need to keep in mind that these resistive RAMs require two extra masks which would complicate the delivery of such an IP. However, an aggressive fab might want to help accelerate the availability of this IP in its production processes. That might give significant advantage over their competition when it comes to an IoT offering.

    By now you must be wondering… how low-power is it? Really, really low. Here is what Adesto published with the new product announcement (Click on the picture below to enlarge it):

    The range of applications enabled by this technology is large but certainly would include a large range of medical devices, environment and security monitoring devices, data logging applications, and probably any device using harvested energy. In fact, I think the ultra-low power level made possible by these devices will enable applications we have not yet thought of, and that is really exciting. For emphasis, the ultra-deep power down state can go as low as 0.05 µW, with read power at 10 µW, and write power at 7.6 µW – that is quite low.

    Randy Smith is an advisor at Brown Venture Associates (BVA). Randy and BVA are experienced masters of team building. As a former EDA and semiconductor IP executive, Randy has repeatedly built winning teams. BVA has been doing the same for more than 20 years while building a proprietary recruiting methodology that is geared for the modern recruiting environment. BVA also has invested in 50+ companies with 20+ liquidity events – the teams they build, win.

    Posted on

    Reusable HW/SW Interface for Portable Stimulus

    Reusable HW/SW Interface for Portable Stimulus
    by Pawan Fangaria on 06-03-2016 at 7:00 am
    Categories: EDA, Events

    Although semiconductor community has ushered into the era of SoCs, the verification of SoCs is still broken. There is no single methodology or engine to verify a complete SoC; this results in duplication of efforts and resources for test creation and verification at multiple stages in the SoC development, albeit with different verification engines. Considering the breadth and depth of verification required for an SoC, there does not seem any other alternative than going through the rigorous process of verifying the SoC with multiple engines in different situations.

    Does that leave us spending exponentially in testing and verification of ever growing SoCs forever? It’s time we find innovative ways to curtail duplication at various levels of testing activities. What if the test-case generation is automated and reused across various SoC stages and verification engines? We would need automated and reusable hardware-software interfaces for actual execution of those test-cases too. So, where do we stand? The good news is that things in this direction are progressing more rapidly than I could anticipate.

    One of the goals of Accellera’s Portable Stimulus initiative is deploying software driven verification by enabling specification of test scenarios that are verification platform agnostic. The generation of test-cases from different scenarios can be automated and mapped to different verification platforms. This methodology seems promising for reuse of test scenarios at block, IP, and SoC level as well.

    A key consideration and complexity in the software driven verification methodology comes when a driver has to be implemented for actual execution of a test on a desired verification platform. This part of the hardware-software interface (HSI) development has remained largely manual. One can imagine the amount of resources, time, and effort being spent in this activity, duplicated for every environment as shown in the figure below:


    Vayavya Labshas proposed a novel methodology for automating the driver development. This methodology revolves around capturing the hardware-software interface specificationsand run-time specifications in standard formats and generating the drivers for multiple operating environments through automated tools. Automatic driver generation meets a critical need in ensuring the generated test cases run on different verification platforms seamlessly.

    Vayavya’s HSI technology is already in use in the electronic and the semiconductor verification industry. Customers have adopted Vayavya’s methodology in their flow where they transform their device specifications to Vayavya’s standard DPS (Device Programming Sequence) format. And by specifying run-time environment in a standard RTS (Runtime Specification) format and using Vayavya’s DDGen (a versatile tool for device driver generation) they can generate drivers for any operating environment such as SystemVerilog driver for verification, BareMetal C driver for validation, and SystemC driver for virtual platform. The generated SystemVerilog drivers are interoperable with UVM (Universal Verification Methodology). Customers treat the HSI specification as a golden specification without leaving any ambiguity in communication between various stakeholders in the team including architects, designers, verification and validation engineers, software engineers and so on.

    Also, the HSI methodology is being adopted in larger semiconductor ecosystem of software driven verification tools. While a standard representation enables specification of reusable test scenarios, HSI would additionally enable specification of reusable drivers, thus ensuring the execution of test on any desired verification platform. Vayavya is an active contributing member and is leading standardization of HSI in Portable Stimulus Working Group (PSWG) setup by Accellera.

    Cadenceis a leading player in the semiconductor EDA industry for software driven verification tools and methodology at system level. Perspec[SUP]TM[/SUP]System Verifier is a major contribution from Cadence for software driven verification. It provides a complete environment for generating system level test-cases from use-case specification.


    In the Perspec flow, actions of design components typically consist of an “exec body” that makes calls to driver APIs for test execution. Before Vayavya’s technology, users had to separately provide the driver implementation for different verification platforms. Vayavya introduced DDGen which takes programmer’s view of the device as input in DPS format and a few lines of code to define run-time environment in RTS format, and automatically generates drivers for different platforms.

    One can imagine how this level of automation for test-case generation and execution on multiple verification and validation platforms can enhance verification productivity by an order of magnitude. The DDGen integration with Perspec makes it easy and efficient to deploy for system level verification of SoCs. The Perspec – DDGen integrated solution for system level test-case generation and execution has been verified in a post-silicon environment on Zedboard consisting of Xilinx Zynq 7000 SoC.

    The Perspec – DDGen integration will be presented by Vayavya at 53[SUP]rd[/SUP] DAC in Cadence Theatre. Attend the following session to know more about Perspec System Verifier, DDGen and the new methodology for software driven verification –

    Date/Time: 7[SUP]th[/SUP] June 2016, 2 PM
    Venue: Cadence Theatre in 53[SUP]rd[/SUP] DAC at Austin, TX
    Topic: Software-Driven Validation: Using Perspec System Verifier and DDGen

    More Articles by Pawan

    Posted on

    IMEC Technology Forum (ITF) – Moving the Electronics Industry Forward

    IMEC Technology Forum (ITF) – Moving the Electronics Industry Forward
    by Scotten Jones on 06-02-2016 at 4:00 pm
    Categories: Events, FD-SOI, FinFET, Foundries, GlobalFoundries

    IMEC is a technology research center located in Belgium that is one of the premier semiconductor research centers in the world today. The IMEC Technology Forum (ITF) is a two-day event attended by approximately 1,000 people to showcase the work done by IMEC and their partners.

    Gary Patton is the Chief Technical Officer and Senior Vice President of Worldwide R&D at Global Foundries. Gary was part of a panel discussion during the “Scaling is dead. Long live scaling” session, he then delivered a keynote presentation entitled Moving the Electronics Industry Forward: Technology Enablers for the Next Wave of Growth and finally I had the opportunity to interview him. In this blog I will discuss Gary’s presentation and my follow up interview. I will blog about the panel discussion separately. I will start with Gary’s keynote and then discuss our interview which gave me an opportunity to follow up on some of the points from his talk and also touch base on Global Foundries progress since I last interviewed him in November 2015.

    My blog on our November 2015 interview is available here.

    Technology Enablers paper:
    Traditional growth drivers are flat, PCs are down and mobile growth has slowed. The semiconductor industry has gone through many transitions in the past. Corporate computing, military and telecommunications drove the industry from 1965 to 1985, from 1985 to 1995 it was the PC/smart client, from 1995 to 2005 we saw internet, gaming consoles and e-commerce, and from 2005 to 2015 we saw mobile as a driver. What will be the next driver? We have also seen technology transitions from bipolar to CMOS, the introduction of high-k metal gates (HKMG) and strain and then FinFETs have carried us for a few years and will carry us for a few more years.

    He thinks 5G will be as disruptive to mobile as data was. Mobile with 5G allows massive connectivity and video download and upload. Internet Of Things (IOT) wearables nearly doubled this year, it will fuel connectivity and 5G. Autonomous cars are coming, there is $350 of semiconductors in a car today, that will grow substantially. Autonomous cars can reduce the number of required cars and urban parking lots. IOT is projected to be $50 to $75 billion dollars in the 2019-2020 time frames. All of those devices will generate data that has to go into the cloud. Data volumes are increasing 25% per year and data centers double every three years.

    There is a need for innovation. It used to be that when you scaled down you got cost, performance and power but today you don’t get all that. You can still drive down cost but it is getting exponentially more expensive to develop. Most key technologies were in development for at least ten years. FinFET electrostatics are limited and will likely transition to nanowires and vertical FETs with FDSOI as an option for low power applications. Highly integrated optics will be needed for shorter copper lines.

    The transition to fully depleted FinFETs gave us lots of drive current for large chips, FDSOI is an option for low power. We need to optimize the power/cost trade off. A 14nm FinFET design is 2.5x the cost of a 28nm planar design. FDSOI gives a lower cost design option that you can forward bias for performance or reverse bias for power. You can dynamically control the bias with software and FDSOI provides easy integration of analog and RF.

    Photonics has moved from 180nm with integrated photonics to 90nm this year and 65nm interposers with integrated photonics are in the works.

    EUV will be in manufacturing by 2020 or sooner. Better power (200 watts has been shown), better photoresist sensitivity and pellicles, Gary expects 7nm to be a long lived node and EUV will be inserted when ready. I will discuss this more in the blog on the panel discussion but Gary noted that we may not take full advantage of the technology at least initially. Inserting EUV can reduce 30 masks to 10 masks and at 1.5 days per mask layer save 30 days of cycle time.

    He thinks packaging is a big opportunity. Over the time that silicon has improved by 1000x package sizes have been reduced by 3x.

    Collaboration will be key, Global Foundries is engaged with CNSE, IMEC, IBM, EDA and Universities. They have FDSOI, MRAM, RF-SOI and SiGe, FinFETs, Advanced Packaging and ASICs. They also have 5 manufacturing centers on 3 continents.

    Later the same day I got to sit down with Gary for a follow-up interview.

    As we discussed at our previous meeting in November 2015, Gary discussed that execution had been an issue in the past and they are really pushing hard on that. They have implemented a technology council to break down barriers, they also do milestone reviews where they bring in experts from around the company to do technology deep dives and that is really paying off. 22 FDSOI has hit all of its milestones and is ahead on yield. Full production is expected in 2017 with risk production at the end of 2016. 14nm is also hitting all of its milestones, yields are good and there are a ton of tape-outs. 14nm went into production earlier this year.

    They are working on 10nm but focused on 7nm. They haven’t announced whether they will do 10nm. He did mention that some customers have told them they will skip 10nm for 7nm. My understanding is that 10nm is a kind of intermediate node mostly targeted at Cell Phones Applications Processors. That isn’t a big segment for Global Foundries so personally I wouldn’t be surprised if they skipped 10nm and went right to 7nm, but Gary wouldn’t comment on this yet.

    One comment I found really interesting is they are using EUV for non-transistor layers to save development time by avoiding all the processing for multi-patterning. Cycle time is coming up a lot in discussions lately because of all of the process complexity we are seeing. He also noted that the bar is getting lower for EUV because you can take out so many multi-patterning cut/block masks with a single EUV exposure. He thinks EUV will be used at contact and via first and for block masks on metal layers. They are currently doing an 80 watt upgrade on the Albany EUV tool.

    The RF business is doing well and they are putting a lot of money into it. Gary just sent one of his best RF experts to Dresden to support RF on the 22FDx process. RF is very hard to do with FinFET because you can only add fins in discrete increments. They are working on a next generation FDSOI technology but haven’t put a number on it. He thinks 22nm FDSOI design costs are similar to 28nm design costs (versus 2.5x for 14nm FinFETs as mentioned above). FDSOI has lower capacitance than FinFETs and small IOT chips are capacitance dominated. They are getting a lot of interest. They are building up IP working with Invecas and ARM is really starting to focus on FDSOI.

    Their ASIC business is leveraging their 14LLP process and getting a lot of traction. 5G will touch many sites and will use a wide range of technologies, including 7nm.

    Global Foundries will do FinFETs for 7nm but he doesn’t think you can do FinFETs beyond 7nm. He thinks horizontal nanowires are next. There may be a “shrink” of 7nm FinFETs but the dimensions won’t shrink much, it may just be implementing EUV.

    Also read: IMEC Technology Forum (ITF) – EUV When, Not If

    Posted on

    iDRM – A Complete Design Rule Development System

    iDRM – A Complete Design Rule Development System
    by Daniel Nenni on 06-02-2016 at 12:00 pm
    Categories: EDA, Sage DA

    Design rules are at the heart of the interface between the foundry and semiconductor designers, which makes them so critical. Traditionally, design rules and DRC decks have been developed manually with no or little automation. Design rule definitions are written using WORD or other general purpose office tools, and DRC decks are programmed in an attempt to match that text definitions. This state of affairs leaves many challenges, such as:

    • How do you verify that the DRM (design rule manual) rule definition accurately represents the rule intent?
    • How do you ensure the definition is complete and unambiguous?
    • How do you verify that the DRC code exactly matches the DRM definition?

    So far, there have not been good solutions to these challenges, which resulted in a host of issues ranging from baffled designers, through delayed product ramps and all the way to product yield catastrophes.

    iDRM from Sage-DA
    Sage made its mission to tackle that problem and introduce automation to all stages of design rule development. This year at #53DAC they will demonstrate a complete system that connects all these dots: starting with design rule capture by the process integration team and delivering a compiled and verified DRC deck that accurately matches and represents the design rule intent.


    The iDRM system consists of:
    1. Design rule capture: GUI based rule entry tool which supports drawings, logic expressions, tables, etc.. Captured rules are executable and can check design examples right away to test the definitions and make sure they accurately express the intent.

    2. DRC reference: Once the rules are captured, iDRM becomes the reference checker for DRC deck developers and early access PDK users. The iDRM rule-set accurately represents the design rule intent. It becomes the executable reference for the development and verification of DRC decks.

    3. Electronic DRM: Once a set of rules has been captured, the user can view them in the form of an Electronic DRM, or use the tool to publish a traditional DRM copy. The design rule definitions in this DRM are formal, clear, unambiguous and complete.

    4. Compiled DRC deck: iDRM enables automatic generation of DRC code by associating DRC code snippets with template rule definitions. For each design rule, iDRM generates the corresponding DRC code using the correct information such as, conditions, layer definitions and all other details. This eliminates errors and ensures consistency between the DRC deck and the DRM.

    5. DRC deck verification and coverage: For each rule, the system automatically generates a set of passing and failing layout test cases. These test cases are used to test DRC code. iDRM also provides coverage metrics for these test cases.


    Additional functionality:
    6. Design Rule Extraction from existing layout: iDRM can extract design rules from a GDS data file and automatically create a design rule manual and DRC check for technologies that do not have proper design rule documentation.

    7. Pattern extraction and classification: iDRM can now scan an entire design and extract all existing patterns, sort them and build a complete pattern library for every layer or combination of layers. Using this pattern library, iDRM can then scan any new design and indicate unknown patterns that are not in the pattern library.

    Sign up for a demo at #53DAC and meet the Sage-DA team: http://www.sage-da.com/dac-2016.html

    Posted on

    Layout Pattern Matching for DRC, DFM, and Yield Improvement

    Layout Pattern Matching for DRC, DFM, and Yield Improvement
    by Tom Dillinger on 06-01-2016 at 12:00 pm
    Categories: EDA, Samsung Foundry, Siemens EDA

    It is truly amazing to consider the advances in microelectronic process development, using 193i photolithography. The figure below is a stark reminder of the difference between the illuminating wavelength and the final imaged geometries. This technology evolution has been enabled by continued investment in mask data generation (including multipatterning decomposition) and exposure optimizations, generally known as computational lithography.
    Continue reading “Layout Pattern Matching for DRC, DFM, and Yield Improvement”

    Posted on

    Go Native – With Methodics at DAC in Austin

    Go Native – With Methodics at DAC in Austin
    by Tom Simon on 06-01-2016 at 7:00 am
    Categories: EDA, Events, Perforce

    DAC is often a yearly reflection point for the companies that exhibit and attend. For the innovators it is an opportunity to look back and see a year of progress and development. Fortunately, this is the case for Methodics, which has had a strong year both in terms of business and technical development. Though, we easily see how these two things will frequently go hand-in-hand.

    Recently my former colleague Michael Munsey joined Methodics as VP of Business Development and Strategic Accounts. He shared with me some of the main points that Methoidics will be highlighting at DAC in Austin the week of June 6[SUP]th[/SUP]. As you know I have been writing about Methodics since last year, and during this time I have had a number of engaging conversations with their CEO Simon Butler. So most of what they are featuring this year may not come as a surprise.

    However, Methodics is leading this year by breaking the tedium of the ubiquitous DAC technical pitches with twice daily Hawaiian dance performances at their booth. Yes, of course there is an underlying message. Unlike the other vendors in the IP and data management space they rely on native integrations with the underlying revision control system. Their tagline is ”Go Native.” They are betting that it will help you remember that theirs is not a proprietary integration that locks in design data.

    To help them emphasize this message, they will also have representatives from Perforce with them in their booth at DAC. So this will be a good opportunity to learn more about adopting native Perforce.

    For IP lifecycle management Methodics offers ProjectIC, which I have written about recently. At DAC this year they will be announcing a new version, ProjectIC 2.0, with many new features and capabilities. The focus of this release is Platform Based Design. Along with this there is a performance speed up and richer API’s for enhancing the integration of ProjectIC into your design environment. Look at their website for a white paper that goes into greater detail on how ProjectIC 2.0 facilitates Platform Based Design.

    For heavy duty data and IP management needs, Methodics offers WarpStor, which is an unusual offering for a company in this space. WarpStor is a hardware appliance that optimizes access to the design data through the IP and data management system. The beauty of it is that it is transparent to the OS and uses the data already stored on existing file servers. At DAC this year Methodics will be talking at length about WarpStor and how it is used to optimize workspace size, bandwidth and overall storage needs.

    The other big news that Methodics will be talking about at DAC is their recent partnership with Magillum. The team at Magillum are experts on IP-XACT, otherwise known as IEEE 1685. IP-XACT is a concrete and standardized method of managing IP so that it can be stored, integrated and qualified systematically and in a way that makes it interoperable across different tool chains. IP-XACT is an excellent example of the application of XML to the semiconductor design space. Because Methodics focuses on IP lifecycle management, this partnership looks very synergistic.

    If you want to learn more about any of the topics mentioned above, or if you just want to get away from the humdrum of technology pitches and would rather see traditional Hawaiian dances, be sure to swing by the Methodics DAC booth during the week of June 6[SUP]th[/SUP] in Austin. Methodics talks further about their DAC offering and demos here on their website.