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Industry 4.0 Challenges Should Sound Familiar to Tech Companies

Industry 4.0 Challenges Should Sound Familiar to Tech Companies
by Raman Chitkara on 06-26-2016 at 7:00 am
Categories: IoT

Following a series of acquisitions, one manufacturer is planning to pivot from a business model based on hardware sales to one based on monthly fees for bundled hardware, software, service, and connectivity. Sensors, the cloud, wireless connectivity and data analytics all play a role in this new model. It is a massive undertaking for an industrial company, and a preview of the coming business transformation to Industry 4.0 that most industrial enterprises are likely to face.

The Industry 4.0 transformation is not just about a high level of automation of the factory but also about the digitization and integration of manufacturing operations and the supply chain, the digitization of product and service offerings, and the implementation of digital business models and direct customer contact, something generally non-existent today. It is about redesigning capabilities and operating models to take advantage of an array of digital technologies now reaching full maturity.

At the heart of Industry 4.0 is the Industrial Internet of Things (IIoT), which Gartner Research estimates will become a significantly larger market than the consumer IoT.

But if you think Industry 4.0 only applies to manufacturing companies, think again. Many of the same issues that confront manufacturers in Industry 4.0 are the same ones that confront software and other tech sector companies when they move to cloud-based, anything-as-a-platform (XaaS) subscription models.

In PwC’s recent “The Global Industry 4.0 Survey,” reported in the whitepaper, “Industry 4.0: Building the digital enterprise,” we found that industrial companies, like the one cited above, are just beginning to invest and take steps to transform themselves into digital enterprises in the Industry 4.0 mold. We know from public statements that some well-known names are moving fast in this direction—General Electric, Boeing, Honeywell and Caterpillar, to name a few.

Embracing the Digital Enterprise
According to the PwC survey of more than 2,000 industrial participants in nine sectors and 26 countries, these companies are going to look a lot different in five years. For example:

  • Respondents expect to significantly increase their portfolios of digital products and services; more than twice as many expect to be at an advanced level in this area by 2020 than today.
  • Almost three-quarters of companies expect to have highly digitised horizontal and vertical value-chain processes in five years.

Do these trends ring true for tech sector companies? I think they do. The survey also sheds light on some of the key hurdles to accomplishing digitization, including at least two that should resonate with the tech sector:

  • Survey respondents say the biggest implementation challenge isn’t the right technology, rather a lack of digital culture and skills. This finding is also consistent with PwC’s Digital IQ research, which for nine years has explored how organizations across industries can derive value from digital investments.
  • Despite the fact that sharpened data analytics skills are essential to Industry 4.0, 38% of respondents currently rely on selective, ad-hoc data analytics capabilities of single employees; another 9% have no significant capabilities at all.

The skills and talent issue was also a key finding of PwC’s Annual Global CEO survey for 2016, published earlier this year – and especially among the tech CEO sub sample in that survey. In the 2010 survey, 58% of tech CEOs said they were concerned about the availability of key skills. In this year’s survey, 80% said availability of talent is their top concern.


Some tech sector companies, especially software vendors that have or are transitioning to the XaaS model, are ahead of the industrial sector in becoming digital enterprises. Tech sector companies with hardware products – semiconductor and other electronics OEMs of all kinds – face essentially the same issues as industrials. (In fact, 10% of the participants in the survey were from the electronics industry segment.)

Tech Faces Similar Issues
The survey findings are worth a look by anyone in the tech sector, not only for parallels to their own experiences, but also to understand issues their industrial customers face. The tech sector can identify multiple opportunities for new or enhanced business in them.

The similarities between the tech sector and the industrial sector are not just evident. There’s a significant convergence between the two worlds, along with specific inter-linkages and inter-dependencies – for example, via IoT.

Whatever the sector, Industry 4.0 is based on interoperability, information transparency, technical assistance and decentralization and autonomous decision-making. These include multiple transitions for industrial companies – across sales, go-to-market, products and offerings that become enriched through addition of sensors and networking, and the associated impact on the end-to-end, order-to-cash cycle.
For tech sector companies, these transitions likely sound familiar as they are all being driven by the evolution of business models towards XaaS. For the foreseeable future, we anticipate that current business models will coexist alongside XaaS; this also means that technology companies must decide carefully on how much to invest in sustaining the current offerings and operating models, while also building for the future.

Tech companies need to consider the same actions recommended for industrial companies in the study. Specifically, they will want to map out their digital strategy;

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10 signs on the neural-net-based ADAS road

10 signs on the neural-net-based ADAS road
by Don Dingee on 06-24-2016 at 12:00 pm
Categories: Automotive, Cadence, IP

Every day I read stuff about the coming of fully autonomous vehicles, and it’s not every day we get a technologist’s view of the hurdles faced in getting there. Chris Rowen, CTO of Cadence’s IP group, gave one of the best presentations I’ve seen on ADAS technology and convolutional neural networks (CNNs) at #53DAC, pointing toward 10 signs on the road ahead. Continue reading “10 signs on the neural-net-based ADAS road”

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ARM and Mentor Enabling the Ecosystem for the Backbone of IoT

ARM and Mentor Enabling the Ecosystem for the Backbone of IoT
by Daniel Nenni on 06-24-2016 at 7:00 am
Categories: Arm, EDA, IoT, IP, Siemens EDA

Charlene Marini (VP of ARM Segment Marketing) did a nice presentation at the ARM/Mentor Summit last month at the Mentor HQ in Fremont. I just got the slides so let me give you a quick summary from my notes. It was a very good presentation on IoT and emulation which in my mind is the new simulation. I also attended an IoT panel at #53DAC that included Mentor, ARM, and Samsung so this will be a combo blog.

IoT has been the top trending term on SemiWiki for the past year mostly because everyone is trying to figure out what IoT really is and more importantly where the profits will come from. Please remember that IoT is a rebranded version of the Embedded Market. Intel changed their Embedded Group to IoT last year, right? So that is what IoT really is.


I think we can all agree that IoT will be a very large and diverse market (like embedded has always been) but one thing I think we are missing is that it will be a HUGELY competitive market. For perspective, let’s say that today 1 out of 10 chip designs make it into high volume production, which may be a bit optimistic. For the Internet of Things it will be closer to 1 out of 100 and I think I’m being very optimistic here. So when people say that mature process nodes are ideal for IoT I laugh out loud because your “mature node” design is going to fail against one using FD-SOI or FinFETs if power and performance are at all a consideration.

Quick question, when was the last time you were inside a 300mm and a 200mm fab? Just last year I toured a new 300mm fab and a “mature” node fab (130nm) and it was like time traveling. There is no way I’m putting an IoT design that my job or company may depend on through a back-in-time-machine but I digress…

Charlene’s presentation starts with the growth chart above. Whether you agree on the specific numbers or not, the growth rate between 15 billion and 28 billion devices 5 years from now is very believable in my opinion.

I think we can also agree with ARM that IoT will require:

  • Capacity and Latency (Automotive)
  • Scalability (Diversity)
  • Velocity (data transfer)
  • Agility (updatable)
  • Efficient Compute (everywhere)
  • Ecosystem (diversity and choice)


The most important point here is ecosystem of course and nobody does ecosystem better than ARM. That brings us to the second part of the Summit and that is verification with Mentor Graphics. Mentor and verification is like peanut butter and jelly, you rarely have one without the other.

Mentor and ARM have a long history of collaboration across a number of technology areas: Embedded, Simulation, Emulation, Test, etc… ARM also uses the Mentor Enterprise Verification Platform, including theVeloce andQuesta platforms, to verify new processor IP and system IP designs. Don’t forget, Mentor is also a fabless chip company and is responsible for the core silicon inside the Veloce emulators so they “walk the walk” as well as “talk the talk.”

Also Read: Army of Engineers on Site Only Masks Weakness

The verification challenge is well documented but, for effect, I will end with these three slides from Jean-Marie Brunet’s presentation: Shift Left: Networking, Mobile and Multimedia SoC Verification:


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Why is the IoT Catnip to Hackers?

Why is the IoT Catnip to Hackers?
by Bill McCabe on 06-23-2016 at 4:00 pm
Categories: Events, IoT, Security

The latest developments in IoT security will protect the companies that use them from disastrous hacks.Rob Enderle writing in CIO Magazine May 20 about a new security certification for IOT products lauded the new offering and cited other measures that responsible IoT businesses must take to secure the future of their companies. His opinion piece couldn’t come at a better time.

Those of us watching the IOT “back door” swing open to hackers have been wondering how and when a product certification like this would become industry standard. Underwriter Laboratory’s Cybersecurity Assurance Program (CAP) just might work. But it’s only a start.

The three-level certification process, according to Enderle, will work fine as long as it’s subject to a “rigorous audit process.” However, he also agrees that using a remote network hub with security stopgaps in place (which is what most are doing now) won’t do a thing to protect wireless devices.

Where we are now, where we need to go
During the NXP/FTF Technology Forum 2016, a group of panelists was asked if the Internet of Things was secure yet. What do you think they answered? Yes, they said, no.

Here’s the rub—and the same thing that Enderle writes about: The connected devices in cars, homes, phones need to have specialty security hardware to stop many attacks. Another missing link, according to Global Business Development Manager Damon Kachur at Symantec, is the need to institute “a massive education process compelling security providers to educate consumers on how to operate their devices securely.”

Using cryptography, requiring several rounds of authentication per day, and manufacturers hiring hackers to break into their IoT devices before they put them on the assembly line—these were also solutions that Forum panelists came up with to secure the IoT.

Horror stories averted?
The stories with the highest profiles are those that see connected cars taken over and crashed; cell phones hijacked and set on fire; and that Target breach, when hackers stole credit cards from Target headquarters using the building’s HVAC systems to get in. What else do we need to do, besides work on certification processes and make sure that before we build the next IoT device, we’ve protected it from hackers?

It’s clear that businesses engaged in the IoT revolution need to make security “job one”. There are heartening signs that this indeed is the case. A recent Accenture paper on IOT security claimed that “businesses surveyed by the World Economic Forum identified cyber-attack vulnerabilities as their most important IoT concern.” And an article last month in Forbes reported that venture capitalists are now “following the money” to underwrite cybersecurity start-ups: “Boston-based Lux Research says investment in “cyberphysical” security startups rose 78% to $228 million in 2015, and will increase to $400 million this year. The report cites rapid adoption of IoT tech, with the potential threats it brings in the area of internet connectivity in cars, homes and factories.”

Businesses that are eager to make money on the IOT without being willing to spend the money on securing it will be increasingly prone to customer data breaches and other high-profile disasters that will close their doors—and slow the adoption of IoT devices—and spending—for years to come. Smart companies need to make an investment in securing their latest IoT game changing use-case or product– or their customers and partners won’t want to make an investment in them.

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Bridging the Gap between Foundry and IC Design at #53DAC

Bridging the Gap between Foundry and IC Design at #53DAC
by Daniel Payne on 06-23-2016 at 12:00 pm
Categories: EDA, Events, Primarius

In our semiconductor ecosystem we often specialize the engineers and therefore EDA tools into separate silos like Foundry, front-end design, back-end design, tapeout, etc. What I discovered at #53DAC a few weeks ago was that some EDA companies actually bridge the gap between foundry engineers and IC designers with their tools. Proplus Design Solutions is one such company and I had the pleasure to talk with Lianfeng Yang about this.
Continue reading “Bridging the Gap between Foundry and IC Design at #53DAC”

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NVIDIA Extends Their Datacenter Performance Lead In Neural Network Computing

NVIDIA Extends Their Datacenter Performance Lead In Neural Network Computing
by Patrick Moorhead on 06-23-2016 at 7:00 am
Categories: EDA

At NVIDIA’s GPU Technology Conference (GTC) 2016 in San Jose, California the company announced products based on their latest GPU architecture, code-named Pascal. This conference is traditionally attended by some of the leading researchers in GPU-accelerated compute technologies and over the past few years has become increasingly focused on Deep Neural Networks (DNN). DNNs are the latest key to artificial intelligence (AI) and cognitive computing. Incredible strides have been made over the last three years in AI thanks to Graphics Processing Units (GPUs).

Companies like Google, Microsoft, IBM, Toyota, Baidu and others are looking at deep neural networks to help solve many of their complex analytical and data-rich problems. NVIDIA is helping these companies to harness the power of their GPUs to accelerate the deep learning these systems need to do. Thanks to NVIDIA’s early involvement in deep neural networks research and their latest GPU hardware, the company is in the driver’s seat right now when it comes to delivering silicon to accelerate deep neural networks.


Photo credit: Patrick Moorhead

The GP100 is for Deep Neural Networks
The newly announced GPU, named GP100 is the first of the Pascal family of GPUs from NVIDIA running on the 16nm FinFET process from TSMC and uses the company’s latest GPU architecture. The GP100 is designed first and foremost for the datacenter in an NVIDIA Tesla Compute card format which is for DNN, cloud, enterprise and other HPC purposes. I expect the GP100 will eventually find its way into the consumer market as a gaming card with many changes, but its primary purpose is to serve as an enterprise acceleration processor. Because of Pascal’s performance, power and software capabilities it will really start to challenge CPU-driven DNN. It also utilizes NVIDIA’s latest CUDA 8 programming language which has become the de-facto standard in GPU computing since it started nearly a decade ago.

Significant compute cluster performance increase via brute force
As has been made quite clear with IBM, Google and Baidu’s adoption of GPUs for DNN workloads, GPUs are currently a better choice versus FPGAs in training. FPGAs may still have a role, but they are likely more useful in production. The GP100 GPU itself is a 15.3 billion transistor chip built on TSMC’s 16nm FinFET process, NVIDIA is able to cram these 15.3 billion transistors on a 610mm^2 chip which is actually larger than the previous generation even though the previous generation was a 28nm chip. Pascal is effectively a full node shrink from the previous generation Maxwell which fit only 8 billion transistors into 601mm^2 effectively the same amount of space. Pascal also increases the amount of FP32 CUDA shader cores from 3072 to 3584 which is a pretty sizable increase and helps deliver 10 TFLOPS of performance.

The real important increase for HPC and datacenter comes in the FP64 CUDA cores which increase from 96 in Maxwell to 1792 in GP100. This increases the double precision capabilities of the Pascal GP100 from 213 GFLOPS to 5.3 TFLOPS, an absolutely massive increase. Maxwell itself was not very favored by those that needed double precision, so many stuck with Kepler generation Tesla cards if they needed double precision. That will change with the GP100 and Pascal architecture.


5 “miracles” to productize the NVIDIA P100 (credit: Patrick Moorhead)

Memory bandwidth, power enhancements via HBM2
The GP100 also uses High Bandwidth Memory 2 (HBM2) which is a new memory technology pioneered in GPUs first by AMD with their Fiji family of graphics cards with HBM. HBM2 brings additional bandwidth and capacity increases so that cards based on the GP100 can have 16GB of memory compared to Fiji which can only have 4GB per GPU. This new memory technology also gets stacked on-die with the GPU which saves significant power and space allowing GP100-based graphics cards to be significantly smaller and more power efficient. The P100 Tesla card with the GP100 GPU inside has 16GB of HBM2 which operates at a mind boggling 720 GB/s effectively removing memory from being the bottleneck in this GPU while also natively supporting ECC.

Scalability improvements via NVLink
NVIDIA didn’t stop with just a new architecture, 16nm FinFET and HBM2, they also introduced NVLink into their first GPU. NVLink is designed to help NVIDIA GPUs interface with one another at a much higher bandwidth and lower latency than PCIe 3 and to connect directly into IBM Power8+ and newer CPUs which also feature NVLink.

HPC enterprise datacenter leaders on-board
All of the HPC OEM leaders like Dell, IBM, HPE and Cray are all on board to implement the P100 Tesla card with the GP100 inside. There will be no shortage of demand for these cards inside the enterprise, it will be more important to see if they can successfully fill that demand.


OEM partners for P100 (Credit, Patrick Moorhead)

It’s very important to understand that this isn’t about the beginning of a kick the tires stage. We are beyond that and into deployment.

DGX-1 is the “rabbit” with supercomputer performance
It will take time for the OEMs to get their systems ready. To accelerate the speed of Pascal’s implementation in universities, enterprises, and cloud service providers, NVIDIA also announced a P100-based server appliance called the DGX-1.

The DGX-1 is a fully integrated solution that includes two Xeon processors and 7TB of SSD space as well as eight P100 Tesla cards in order to deliver the most performance per watt. This appliance is not intended to replace OEM solutions, but rather to allow people that want to start working on their DNNs using Pascal to do so sooner rather than later.

There’s a very good chance that many of NVIDIA’s customers for Pascal may end up designing their own solutions and NVIDIA is simply enabling early adopters to buy a DGX-1 to get ready for when OEM solutions are available at large scale. NVIDIA is selling one DGX-1 for $129,000 and will be delivering them this summer.

NVIDIA claims that a single DGX-1 appliance will replace 250 CPU-based nodes that would normally be used for DNN. In addition to replacing 250 CPU nodes, the company claims Pascal is 12X faster than the previous generation GPU in DNN. The DGX-1 delivers all of this performance in a compact 3U, 3200-watt server. This could amount to huge savings in space as well as overall cost for anyone looking to do serious DNN training.

Wrapping up
NVIDIA may have stumbled upon GPU accelerated DNN either by sheer luck, accident or the result of their close relationship And investment with the research community. Ultimately, it doesn’t matter what the answer is to the question because NVIDIA is clearly the leader in this space right now and it is proving to be a major driver of their technology focus. NVIDIA needs flawless execution on the GP100 for DNN and to deliver these GPUs and their software on time, if not early. CPUs currently own this space, but GPUs are extremely popular now but FPGAs want a piece of this, too. NVIDIA is in the driver’s seat right now but they cannot rest on their laurels and allow others to catch up to them. NVIDIA has a pretty well spread delivery roadmap leading all the way up to Q1 2017, so it will be critical which major design wins they get until then.

More from Moor Insights and Strategy

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Webinar alert – ARM and Enea explore NFV

Webinar alert – ARM and Enea explore NFV
by Don Dingee on 06-22-2016 at 4:00 pm
Categories: Arm, Events, IP

In the Open Source IP panel at 53DAC, we explored the idea of workload-optimized servers. One panelist observation stuck with me: if one chooses to deviate from the Intel-based norm in a data center, you essentially have to spray paint a line around any boxes that don’t comply. Continue reading “Webinar alert – ARM and Enea explore NFV”

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Semiconductor IP QA Standards Get a Boost at #53DAC

Semiconductor IP QA Standards Get a Boost at #53DAC
by Daniel Payne on 06-22-2016 at 12:00 pm
Categories: EDA, Events, Fractal Technologies

At the #53DAC earlier this month held in Austin, Texas I met up with Renee Donkers, the founder of Fractal Technologies. His company has been focused on improving the quality of semiconductor IP cells through the use of automated checking software. The highest area of growth in EDA as measured by the ESD Alliance is in the reusable IP cells being provided by IP vendors, so it makes sense that we really need an independent method for validating the quality of IP blocks and all of their files for correctness and consistency.
Continue reading “Semiconductor IP QA Standards Get a Boost at #53DAC”

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IBM Fires a Shot at Intel with its Latest POWER Roadmap

IBM Fires a Shot at Intel with its Latest POWER Roadmap
by Alan Radding on 06-22-2016 at 7:00 am
Categories: EDA

In case you worry that IBM will abandon hardware in the pursuit of its strategic initiatives focusing on cloud, mobile, analytics and more; well, stop worrying. With the announcement of its POWER Roadmap at the OpenPOWER Summitearlier this spring, it appears POWER will be around for years to come. But IBM is not abandoning the strategic initiatives either; the new Roadmap promises to support new types of workloads, such as real time analytics, Linux, hyperscale data centers, and more along with support for the current POWER workloads.



Pictured above: POWER9 Architecture, courtesy of IBM


Specifically, IBM is offering a denser roadmap, not tied to technology and not even tied solely to IBM. It draws on innovations from a handful of the members of the Open POWER Foundation as well as support from Google. The new roadmap also signals IBM’s intention to make a serious run at Intel’s near monopoly on enterprise server processors by offering comparable or better price, performance, and features.


Google, for example, reports porting many of its popular web services to run on Power systems; its toolchain has been updated to output code for x86, ARM, or Power architectures with the flip of a configuration flag. Google, which strives to be everything to everybody, now has a highly viable alternative to Intel in terms of performance and price with POWER. At the OpenPOWER Summit early in the spring, Google made it clear it plans to build scale-out server solutions based on OpenPower.


Don’t even think, however, that Google is abandoning Intel. The majority of its systems are Intel-oriented. Still, POWER and the OpenPOWER community will provide a directly competitive processing alternative. To underscore the situation Google and Rackspace announced they were working together on Power9 server blueprints for the Open Compute Project, designs that reportedly are compatible with the 48V Open Compute racks Google and Facebook, another hyperscale data center, already are working on.


Google represents another proof point that OpenPOWER is ready for hyperscale data centers. DancingDinosaur, however, really is interested most in what is coming from OpenPOWER that is new and sexy for enterprise data centers, since most DancingDinosaur readers are focused on the enterprise data center. Of course, they still need ever better performance and scalability too. In that regard OpenPOWER has much for them in the works.


For starters, POWER8 is currently delivered as a 12-core, 22nm processor. POWER9, expected in 2017, will be delivered as 14nm processor with 24 cores and CAPI and NVlink accelerators. That is sure to deliver more performance with greater energy efficiency. By 2018, the IBM roadmap shows POWER8/9 as a 10nm, maybe even 7nm, processor, based on the existing micro-architecture.


The real POWER future, arriving around 2020, will feature a new micro-architecture, sport new features and functions, and bring new technology. Expect much, if not almost all, of the new functions to come from various OpenPOWER Foundation partners, POWER9, only a year or so out, promises a wealth of improvements in speeds and feeds. Although intended to serve the traditional Power Server market, it also is expanding its analytics capabilities and bringing new deployment models for hyperscale, cloud, and technical computing through scale out deployment. This will include deployment in both clustered or multiple formats. It will feature a shorter pipeline, improved branch execution, and low latency on the die cache as well as PCI gen 4.

Expect a 3x bandwidth improvement with POWER9 over POWER8 and a 33% speed increase. POWER9 also will continue to speed hardware acceleration and support next gen NVlink, improved coherency, enhance CAPI, and introduce a 25 GPS high speed link. Although the 2-socket chip will remain, IBM suggests larger socket counts are coming. It will need that to compete with Intel.


As a data center manager, will a POWER9 machine change your data center dynamics? Maybe, you decide: a dual-socket Power9 server with 32 DDR4 memory slots, two NVlink slots, three PCIe gen-4 x16 slots, and a total 44 core count. That’s a lot of computing power in one rack.


Now IBM just has to crank out similar advances for the next z System (a z14 maybe?) through the Open Mainframe Project.

DancingDinosaur is Alan Radding, a veteran information technology analyst and writer. Please follow DancingDinosaur on Twitter, @mainframeblog. See more of his IT writing at technologywriter.com and here.

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ASML pays $3.1B for Hermes to get E-beam inspection

ASML pays $3.1B for Hermes to get E-beam inspection
by Robert Maire on 06-21-2016 at 7:00 am
Categories: Semiconductor Intelligence, Semiconductor Services

Cheap versus year ago but expensive on fundementals – Net negative for KLAC/LRCX & AMAT. ASML bought Hermes Microvision for much the same reason as the Cymer acquisition – to support EUV. ASML could have made a counter offer for KLAC (as we had suggested previously) but this obviously would have been much more expensive and risky from a regulatory perspective (as Lam has found out).

So ASML did the next best thing and bought the competitor that had beat KLAC in the market..Hermes. Though the acquisition is expensive it is a strong strategic move to shore up support for EUV infrastructure which desperately needs help for what has become embarrassingly late and so fraught with issues such that is survival has been questioned.

Cheap and expensive at the same time…
Relative to the crazy stock price that Hermes had reached a year ago, the acquisition price at half the peak price seems cheap by comparison but you have to remember that the price is 15 times revenues not earnings. The PE multiple paid is closer to 50.

Investors need to recall that the Taiwanese exchange is over priced as compared to the US exchanges with lots of Taiwanese dollars chasing a limited pot of equities.

The same logic holds true for over priced European equities (of which ASML is one) where European investors have a lot of cash chasing after relatively few tech companies.

In short, it is one overvalued company , ASML, buying an even more overvalued company , Hermes Microvision at eye popping valuations versus US based companies.

KLAC forced the issue…
When KLAC dropped its EUV mask inspection program, ASML lost a huge, critical piece of much needed infrastructure to make its EUV tool viable. Lam’s acquisition of KLAC sealed this fate as LAM gets benefit from multi patterning at EUV’s expense, and will scatter the ashes of the EUV reticle inspection tool.

ASML had essentially no choice but to buy the only significant , viable, alternative EUV mask inspection/metrology tool company to keep the infrastructure alive and accelerate it.

As we had pointed out in many articles it has become clear that now, finally after source and power issues are getting resolved, the industry is finally waking up to the fact that there is not enough EUV infrastructure and this acquisition is meant to insure and accelerate that deficiency.

Negative for AMAT and KLAC/LRCX…
As a standalone company Hermes has a harder time competing with both AMAT and KLAC. AMAT has a significant E beam tool and KLAC recently released its 5th generation optical tools. But as part of the much larger and essentially monopolistic ASML, with limitless pockets and market leverage Hermes will do much better.

We are also sure that now that ASML has become a competitor , whatever semblance of working with AMAT and KLAC ever existing will quickly vanish as ASML will obviously only work with and push their own product and try to choke off the AMAT and KLAC competitive products.

ASML has a lot of muscle and leverage to do this and hurt both competitors in the process. Bundling litho tools with the purchase of inspection tools would give an unfair advantage in the market.

Speaking of unfair advantage…
Though at first blush most people would assume an easy regulatory approval for the combination given the lack of overlap (as with Lam and KLAC) but we would point to the near monopolistic position of ASML in the litho market and along with it would come an ability to restrict competition of currently competitive metrology/inspection tools.

As with the KLAM combination its not the overlap that counts but the anti-competitive potential that the deal brings. Given that the deal has to be approved in the US, we would not be surprised if it gets a second request much as KLAM has. Because the deal will also come at the 11th hour in the current administration which is already not corporate friendly even in the US and its involving two foreign companies, it may make it even tougher.

From KLAM’s perspective “whats good for the goose is good for the gander” or perhaps misery loves company.

The semiconductor M&A lint roller, rolls along…
As we had said earlier this year, and at our recent industry SEMI keynote speech in Albany, we see no reason for the M&A pace to slow down. Though this deal seems to be driven more by desperation and need rather than economics (especially at this high a price), we think there are still many reason for M&A to continue….there are a lot of companies still left to roll up.

The stocks…
Even though ASML is paying a high price relative to the industry and its own valuation, the strategic value likely overwhelms the financial value and thus is a near term positive. However we think that this acquisition alone will not significantly alter the odds of EUV’s success and ASML still has much work to do. This Hermes acquisition is not as core to EUV as Cymer was. Long and short, we think investors would and should like the combination as it no doubt will help ASML. We would caution that the “arb spread” could be wide as approval may not be as easy as most initially think.

Although this is a negative for AMAT and its E beam aspirations it is more of a negative for the KLAM merger. The merger is already likely less attractive as they will likely be some remedies to get the deal done which will have a cost associated. Now KLA’s core business will be under direct attack from a much larger company, ASML, supporting a smaller company, Hermes, that had already done significant damage to KLAC’s market share and leadership in metrology/inspection. KLAC’s “flub” of the Ebeam market continues to be one of the few missteps the company made but a costly one that keeps coming back to haunt it. This problem will now become Lam’s problem…