“Data management tools? We use small teams doing small designs. Each project only has two or three designers. Everyone uses the same EDA tools. Why do we need another tool for collaboration?” Good question. If you enjoy frequent meetings and redoing work because someone didn’t understand the status of IP blocks, the answers may not interest you. Continue reading “3 Small-Team Design Productivity Challenges Managed”
Design starts are the lifeblood of the semiconductor industry which is why we have been following the eSilicon STAR Platform since its introduction with great anticipation. The STAR platform was first launched about three years ago. Today, there are over 1,300 registered STAR users in 52 countries around the world.
The ASIC business model is one of the reasons the fabless semiconductor ecosystem is what it is today, a force of nature. As an extension to the ASIC model, the STAR tools make it very easy to: Browse and try different IP, optimize your design, get quotes and compare with different foundry and IP options, and track your project online from start to finish. I guess the next step is a virtual reality interface so you can actually watch your design through the entire process?
The eSilicon[SUP]®[/SUP] STAR platform is an automated online secure environment that provides a self-service, transparent, accurate, real-time experience from IC design through volume ASIC production. The STAR online design virtualization platform helps you manage complexity and make the right decisions on your ASIC journey from concept to volume production.
Today eSilicon announced that STAR Navigator now includes automated, online quoting and purchasing capabilities for memory IP and IO libraries. I got a live demo last week and let me tell you I was seriously impressed! One click gets you IP silicon reports?!?!?!
Given that embedded memories are a big part of chip design the ability do “what if” scenarios based on power, performance, area, and price give the average ASIC designer a HUGE advantage. Seriously, thoroughly evaluating all possible memory options is often skipped due to time constraints and that can jeopardize the success of your ASIC.
“STAR Navigator simplifies the comparison of results across multiple technologies, architectures and other characteristics and takes the guesswork out of hitting PPA targets,” said Lisa Minwell, eSilicon’s senior director, IP marketing. “This goes much, much deeper than IP portals that serve as IP catalogs. Using STAR Navigator, designers can download front-end views, run simulations in their own environments and then purchase the back-end views of the IP and I/Os that best fit their design. The choice of optimized IP is now in the hands of the designer.”
By the way, I worked with Lisa Minwell at Virage Logic back in the day. Before spending 8 years at Virage, she spent 15 years at Motorola and has been at eSilicon for the past 5 years so yes Lisa knows IP, absolutely. In fact, tomorrow Lisa will present on HBM/2.5D at the TSMC Open Innovation Platform Ecosystem Forum 2016:
The next generation of high-performance computing, graphics and networking applications have increasing needs for bandwidth. High-bandwidth memory (HBM) combined with 2.5D technology offers a tremendous increase in capacity and performance. Increased capacity because of the stacked memory in a smaller area and increased performance because of the interposer and shorter signal routing. The interposer allows the integration of highly parallel connections to the memory stacks inside the package, therefore it is able to offer huge capacity and performance increases.
This presentation will highlight the silicon characteristics of eSilicon’s HBM PHY in TSMC’s CLN28HPC technology. The presentation will also highlight TSMC CoWoS technology as well as complex ASICs that use high-bandwidth memory.
The SemiWiki bloggers will be there in full force so stay tuned for in depth coverage. I hope to see you there!
About TSMC 2016 OIP Ecosystem Forum
The TSMC OIP Ecosystem Forum is a one-of-a-kind event that brings together the semiconductor design chain community and approximately 1,000 of director-level and above TSMC customer executives. The OIP Forum will feature a day-long, three-track technical conference along with an Ecosystem Pavilion that will host up to 80 member companies.
About eSilicon
eSilicon guides customers through a fast, accurate, transparent, low-risk ASIC journey, from concept to volume production. Explore your options online with eSilicon STAR tools, engage with eSilicon experts, and take advantage of eSilicon semiconductor design, custom IP and IC manufacturing solutions through a flexible engagement model. eSilicon serves a wide variety of markets including the automotive, communications, computer, consumer, industrial products and medical segments. Get the data, decision-making power and technology you need for first-time-right results. www.esilicon.com
Most of what you have read about design for low power has probably focused on mobile devices where power consumption constraints tend to outweigh performance objectives. These devices use aggressive power switching strategies, based on the reasonable assumption that parts or all of the device can be powered down at any given time and recovery times from power-down need only match reasonable human response times.
But what about the other end of the mobile or IoT ecosystem – the cloud? Servers have to deliver high performance, they have unpredictable loads and the economics of that business pushes to maximize utilization to the greatest extent possible. As far as power-down strategies are concerned, the minimum switchable unit is typically a whole server. Some datacenters power down servers during light loading (packing virtual machines onto a subset of available servers), but this doesn’t help reduce peak power, which is where a viable datacenter wants to be operating most of the time.
Historically, processor design teams have looked at power very late in design, when they can use gate-level netlists with accurate parasitics to get within ~5% of silicon measurements. That’s in part because power has not been a primary metric for processors (reasonable was OK) and in part because processor teams do a lot of hand-tuning for performance and power-saving techniques don’t usually help performance. The need for hand-tuning, by the way, applies even if you are using ARM cores if you’re shooting for GHz performance; check out what has gone into the high-performance ARM cores provided by the foundries.
But that’s changed. In servers, low power is not about battery life. It’s about:
For all these reasons, power has become increasingly important for servers but getting an estimate late in design obviously isn’t very helpful, especially if it can take 6-8 weeks to figure it out.
So what can be done if power-down strategies are off the table? Low-level clock-gating, manual or automated, is useful but many of those methods are used for second-order improvements and we want first-order help. That means we need to look at macro-level power-saving options with an understanding of architecture and intended usage. And that requires detailed use-case power analysis, over lots of use-cases. AMD has just published an article on how they went about reducing power in one of their server-class designs using ANSYS PowerArtist for power estimation at RTL where it was still practical to refine the design microarchitecture.
Estimating power while the design is still at RTL and being able to generate estimates in minutes is essential to making this practical. Also important to AMD was very fast turn-around and multiple types of visualization for what-if analysis. Again this is because the big savings won’t come from automated gating, they come from designers figuring out where and how to make improvements in line with typical usage. So isolating and understanding power hotspots, followed by fast iteration (minutes) to experiment with power-saving scenarios is critical. (I expect ANSYS’ Big Data analytics in Seascape to further enhance this value proposition in the future.)
It’s always interesting to hear a customer’s estimates of the impact of a tool. AMD said that using PowerArtist, they estimated that in idle-mode the design was using only 16% less power than when in full bandwidth mode and that more than 50% of this power was consumed by the clock distribution network alone. Hello opportunity for a first-order power reduction. Based on RTL analysis they were able to isolate areas where many cones of logic could be clock-gated. They also found, thanks to what they felt was quite accurate early RTL modeling of clock power distribution in PowerArtist, that they could in many cases move gating closer to the root in the clock tree, saving significant power consumption in the tree alone. In addition they found that flexibly adjusting the size of the queue based on queue utilization could reduce power. Between these factors, AMD was able to reduce idle power by 70% and also saw a significant improvement in active power.
Though not mentioned in the AMD article, you should also know that PowerArtist generates an RTL Power Model (RPM) which can be read directly into RedHawk or SeaHawk for power-aware power integrity, thermal and EM analysis. So ANSYS has you covered for everything you need in server power analysis – for power consumption and optimization, for integrity, for heating and for reliability. Pretty cool solution (pun intended).
Last week Renesas Electronics announced an agreement to acquire Intersil Corporation for US$3.22 billion. This follows July’s announcement that Analog Devices Inc. (ADI) will acquire Linear Technology Corp. (LTC) for $14.8 billion. These deals will cause a shakeup in the analog IC market. According to IC Insights ranking of analog IC suppliers for 2015, ADI was number four, LTC was number eight and Renesas was number ten. Comparing 2015 analog rankings with 1995, 20 years ago, reveals some interesting changes. The table below shows analog rankings from 1995 from Gartner (then known as Dataquest), 2015 rankings from IC Insights, and our Semiconductor Intelligence (SC-IQ) forecast of 2016 rankings.
Only three names from the 1995 list are on the 2015 list: STMicroelectronics (ST), Texas Instruments (TI), and Analog Devices (ADI). However, several of the analog businesses from 1995 are represented in 2015 under different names through various spin-offs, acquisitions and mergers.
Philips, number two in 1995, spun off its semiconductor business as NXP Semiconductors in 2006. NXP is number seven on the 2015 list.
National Semiconductor, number three in 1995, was acquired by TI in 2011, solidifying TI’s number one ranking. In 1995 National included Fairchild Semiconductor, which was spun off in 1997. TI also bolstered its analog position with acquisitions of Silicon Systems in 1996, Unitrode and Power Trends in 1999 and Burr-Brown in 2000.
Motorola (number four in 1995) divested its semiconductor businesses as ON Semiconductor in 1999 and Freescale Semiconductor in 2003. In 2015 ON Semiconductor agreed to acquire Fairchild, with completion expected within the few months. ON’s number nine 2015 ranking does not include Fairchild. NXP acquired Freescale in December 2015 (NXP’s 2015 number seven ranking includes Freescale).
Toshiba and Sanyo are both still in the analog business, but have dropped out of the top ten.
Siemens, number nine in 1995 spun off its semiconductor business as Infineon Technologies in 1999. Infineon was number two in 2015. Some of Infineon’s growth was due to the acquisition of International Rectifier in January 2015.
NEC (number ten in 1995) combined its semiconductor business, NEC Electronics, with Renesas Technology in 2010 to form Renesas Electronics. Renesas Technology was formed in 2003 as a joint venture of the semiconductor business of Mitsubishi (number 13 in the 1995 analog rankings) and Hitachi (number 16). Renesas was number ten in 2015.
Thus only three companies in the 2015 ranking do not have ties to companies in the 1995 ranking. Skyworks Solutions was formed in 2002 with the merger of Alpha Industries and Conexant’s wireless division. Maxim Integrated was not even in the top 20 in the 1995 analog rankings, but moved up to number six in 2015 with over 10 times the revenue of 1995. Much of Maxim’s growth was driven by acquisitions including Dallas Semiconductor and Volterra and product lines from Vitesse and Zilog. LTC was number 18 in 1995 and number 8 in 2015. LTC’s growth was primarily organic, with few acquisitions.
Maxim has been mentioned as both a potential acquisition target and a potential acquirer. Bloomberg reported in January 2016 that TI and ADI each investigated an acquisition of Maxim, but each company decided the price was too high. EE Times revealed in August that Maxim was in the bidding for Intersil before Renesas closed the deal.
What will the analog rankings look like when 2016 is over? TI will certainly remain number one with over $8 billion in analog revenue. ADI will move up to number two with over $4 billion in revenue including LTC. The ADI and LTC merger will not be completed until 2017, but we have combined their revenues in 2016 for comparison. Infineon and Skyworks should be three and four, but there is a chance Skyworks could pass Infineon. Maxim and NXP should remain six and seven. ON will add over $300 million in analog revenue with the Fairchild acquisition and move up from number nine to number eight. However, ON will not pass anybody, just move up one with elimination of LTC. Renesas will add over $500 million in analog revenue with the Intersil acquisition and move up from number 10 to number 9 (Renesas and Intersil are combined for comparison in 2016 even though the deal will not be complete until 2017).
The ADI and LTC combination will open up a spot in the top 10 in 2016. That spot should be taken by MediaTek, which added about $400 million in analog revenue with the acquisition of Richtek Technology in October 2015.
Intersil: the remnants of semiconductor pioneers.
The proposed acquisition of Intersil by Renesas will lead to the further disappearance of two pioneers in the semiconductor industry. Intersil was formed in 1999 when Harris Corporation spun off its semiconductor business. Harris had previously purchased the General Electric (GE) semiconductor business in 1988. The GE semiconductor business included RCA Solid State, which GE purchased from RCA in 1986. Harris began its semiconductor operation in 1967 with the purchase of Radiation Inc. Also in 1967 the original Intersil was founded by Jean Hoerni, one of the founders of Fairchild and the inventor of the planar process. GE bought Intersil in 1981. The Intersil name was revived with the 1999 spinoff from Harris.
GE and RCA were early leaders in semiconductors. GE was one of the original licensees of the AT&T transistor patent and RCA was an early licensee. The two companies also did significant semiconductor research on their own. The history of early GE and RCA research is detailed in the excellent Transistor History website created by Mark P D Burgess.
GE and RCA were leaders in consumer electronics and primarily used many of their semiconductors internally. They also sold on the merchant market. GE was a major supplier of discrete semiconductors in the 1960s. RCA was a top ten merchant semiconductor supplier in the mid-1970s.
After the Intersil acquisition, Renesas Electronics will contain the remnants of five companies which began semiconductor research in the 1940s and 1950s: GE, RCA, NEC, Hitachi and Mitsubishi.
It is a busy month for book signings but it is a pleasure to do it for the greater good of the semiconductor industry. It really is an honor to meet the people who keep our electronic devices on the leading edge of technology, absolutely.
The Linley Processor Conference is on September 27[SUP]th[/SUP]and 28[SUP]th[/SUP] at the Hyatt Regency Hotel in Santa Clara, right across the street from Levi Stadium for you sports fans. This is an in-depth embedded processor conference for communications, IoT, and advanced automotive systems.
Here are the keynotes:
Day One – September 27
Specialization Drives Processor Innovation
Linley Gwennap, Principal Analyst, The Linley Group
Day Two – September 28
How Virtualization is Changing Networking
Bruce Davie, CTP Networking, VMware
I’m sure we all know Linley so let’s check Bruce out:
Bruce Davie is CTO for Networking at VMware, and a Principal Engineer in the Networking and Security BU. He joined VMware as part of the Nicira acquisition, and focuses on network virtualization. He has over 25 years of networking industry experience, and was a Cisco Fellow prior to joining Nicira. At Cisco, he worked closely with leading service providers to enhance the capabilities of their networks. He led the team that developed multi-protocol label switching (MPLS) and contributed to the standards on IP quality of service. He has written over a dozen Internet RFCs and several networking textbooks. Bruce received his Ph. D. in computer science from the University of Edinburgh in 1988 and is an ACM Fellow.
SemiWiki bloggers Tom Simon, Don Dingee, and I will be covering this event so stay tuned for a more in-depth look at some of the presentations. In fact, quite a few of the companies SemiWiki has worked with over the years are presenting:
Session 1: IoT Edge
Intelligent edge devices create a buffer between numerous IoT clients and the rest of the Internet. To minimize the cost and power consumption of client devices, these IoT edge systems may offload complex protocols such as security. This session, moderated by The Linley Group senior analyst Loyd Case, will discuss potential threats to IoT security and provide hardware and software solutions to defend against these threats.
Protecting IoT Edge Devices from Malicious Physical and Software Attacks
Fergus Casey, Senior R&D Manager, ARC Processors, Synopsys
Session 5: SoC Connectivity
The number of IP blocks in a processor continues to rise. Many of these blocks perform some sort of processing, including CPUs, GPUs, DSPs, and image processors (ISPs). The newest trend is to connect these heterogeneous IP cores using a cache-coherent interconnect, simplifying data sharing. This session, moderated by The Linley Group senior analyst Tom Halfhill, will discuss network-on-a-chip (NoC) and other interconnect IP for complex SoC designs.
Building More Powerful Infrastructure SoCs from Edge to Cloud
Jeff Defilippi, Senior Product Manager, ARM
Coherency: The New Normal in SoCs
Anush Mohandass, Vice President, Marketing and Business Development, NetSpeed Systems
Implementing Cache-Coherent Hardware Acceleration for ADAS and Machine Learning
Matthew Mangan, Corporate Applications Engineer, Arteris
Session 9: Automotive and Vision
Advanced driver assistance systems (ADAS) are evolving from delivering hazard warnings, to active collision-avoidance, to fully autonomous driving. Specialized computer-vision IP cores coupled with deep-learning processors will provide the eyes and brains for future smart cars. This session, moderated by Mike Demler, senior analyst at The Linley Group, discusses new IP and SoC architectures for ADAS and other automotive applications.
A Neural-Network Oriented Vision DSP with Customized Hardware and Software Framework
Liran Bar, Director of Product Marketing, CEVA
High-Performance Vision Processors for HD Resolutions at Embedded Power Levels
Mike Thompson, Sr. Product Marketing Manager, ARC Processors, Synopsys
As Embedded Floating Point Becomes Ubiquitous, What Are Your Options?
Dror Maydan, Senior Group Director, Tensilica Software Group, Cadence
Following the sessions is a Q&A which is definitely worth your time. For more information: Linley Processor Conference 2016
The Past We Lived Through
The taxi industry has been a part of city and community landscapes since the “modern” taxicab first appeared on the streets of London in the late 1800’s. Since then, taxis have grown into a massive worldwide industry with strong regulation and protection in most jurisdictions. Such “rules” have limited competition while also minimizing any need to evolve, improve and innovate. Then along came something called Uber bringing with it an entirely new industry called “ride-sharing” and the taxi industry suddenly saw it’s protective glass house shattered to pieces overnight.
Shielded from competition with regulations limiting the number of cabs on the street while dictating fee structures, taxi company owners concentrated on revenue. This took its toll on service and fleet quality. Outside of hailing a taxi on the street, cab response times were unpredictable with long customer wait times being the norm. And often the cab itself was a poorly maintained vehicle with torn and dirty seats, squeaky breaks and a driver with no cab side manner.
The Present We’re Living With
Uber shows up with a simple app where customers are picked up in minutes by a clean, recent model and well-maintained car. Service is the focus, with well-dressed, polite drivers who gladly help with bags. Some even provide water, candy, and other extras to make the ride more pleasurable.
Wake up horn for the taxi industry!
They say disruption is often the most effective catalyst to force positive change, especially in an old, entrenched industry. You could say Uber drove in and massively disrupted the taxi business!
The Future As It Can BeYes, taxis still have a LARGE and powerful presence. The taxi industry IS NOT rolling over and falling into the scrap yard. We’re talking about an immense global business estimated to generate over $ 100 billion/year in revenue. Just in the United States, taxi industry numbers are staggering:
In my market alone, the Las Vegas taxi industry generated over $ 425 million in revenue in 2015 representing almost 28 million trips! Taxis are definitely sticking around!
Reinvention
Yes, it’s been hurt by ride-sharing. In some markets, ridership and driver income are down by up to 50% over the prior year. But fleet owners are wide awake, recognizing mistakes made, opportunities overlooked and are exploring ways to not only level the playing field with the ride-sharing companies but drive technologies that will help them gain the lead.
As Senior Vice President for IoE Connectivity at beamSmart, I have been working closely with taxi companies and regulatory bodies around the country. I can tell you this industry IS focused on bringing true technology into their members. While much of the buzz in this area has been around basic apps that look to deliver Uber-like functionality, the real solution for the taxi industry is a total end-to-end system that integrates dispatching, response, communication and safety into one platform. A product that beamSmart has already perfected.
beamAtaxi, the “Uber” of Licensed Taxis
Many tools find clock domain crossings (CDCs) in FPGA designs. Some don’t find the right ones since they don’t comprehend things like in-house synchronizer constructs. Some find too many based on misunderstanding intent, inaccurate constraints, and other factors that lead to noise. Continue reading “Up front phases improve CDC analysis”
As most of you know SemiWiki published a book which is a really nice history of the fabless semiconductor ecosystem. Thousands of people have copies, we have received many compliments on it, and we are very proud. As a thank you to all SemiWiki members I would like to offer a free electronic version of the book (PDF). You can access it via the attachment at the bottom of this wiki:
Fabless: The Transformation of the Semiconductor Industry
Only registered SemiWiki members can access this wiki so if you are not already a member please join as my guest: https://www.legacy.semiwiki.com/forum/register.php
For those of you who are “seasoned” semiconductor professionals this book will be a nice walk down memory lane. If you are less seasoned it will be a great read to get you up to speed on how we got to where we are today and where we are going tomorrow, absolutely.
Preface
The purpose of this book is to illustrate the magnificence of the fabless semiconductor ecosystem, and to give credit where credit is due. We trace the history of the semiconductor industry from both a technical and business perspective. We argue that the development of the fabless business model was a key enabler of the growth in semiconductors since the mid-1980s. Because business models, as much as the technology, are what keep us thrilled with new gadgets year after year, we focus on the evolution of the electronics business. We also invited key players in the industry to contribute chapters. These “In Their Own Words” chapters allow the heavyweights of the industry to tell their corporate history for themselves, focusing on the industry developments (both in technology and business models) that made them successful, and how they in turn drive the further evolution of the semiconductor industry.
The economics of designing a chip and getting it manufactured is similar to how the pharmaceutical industry gets a new drug to market. Getting to the stage that a drug can be shipped to your local pharmacy is enormously expensive. But once it’s done, you have something that can be manufactured for a few cents and sold for, perhaps, ten dollars. ICs are like that, although for different reasons. Getting an IC designed and manufactured is incredibly expensive, but then you have something that can be manufactured for a few dollars, and put into products that can be sold for hundreds of dollars. One way to look at it is that the first IC costs many millions of dollars—you only make a lot of money
if you sell a lot of them.
What we hope you learn from this book is that even though IC-based electronics are cheap and ubiquitous, they are not cheap or easy to make. It takes teams of hundreds of design engineers to design an IC, and a complex ecosystem of software, components, and services to make it happen. The fabs that physically manufacture the ICs cost more to build than a nuclear power plant. Yet year after year, for 40 years, the cost per transistor has decreased in a steady and predictable curve. There are many reasons for this cost reduction, and we argue that the fabless semiconductor business model is among the most important of those reasons over the past three decades. The next chapter is an introduction to the history of the semiconductor industry, including the invention of the basic building block of all modern digital devices, the transistor, the invention of the integrated circuit, and the businesses that developed around them.
Table of Contents
Chapter 1: The Semiconductor Century
Chapter 2: The ASIC Business
In Their Own Words: VLSI Technology
In Their Own Words: eSilicon Corporation
Chapter 3: The FPGA
In Their Own Words: Xilinx
Chapter 4: Moving To The Fabless Model
In Their Own Words: Chips And Technologies
Chapter 5: The Rise Of The Foundry
In Their Own Words: TSMC And Open Innovation Platform
In Their Own Words: GLOBALFOUNDRIES
Chapter 6: Electronic Design Automation
In Their Own Words: Mentor Graphics
In Their Own Words: Cadence Design Systems
In Their Own Words: Synopsys
Chapter 7: Intellectual Property
In Their Own Words: ARM
In Their Own Words: Imagination
Chapter 8: What’s Next For The Semiconductor Industry
On September 8, 2016 GLOBALFOUNDRIES (GF) announced their 12nm FDSOI technology node. On September 12th I had a chance to interview Greg Bartlett, GF Senior Vice President for the CMOS Business Unit (as a side note, GF has: RF SOI, ASIC and CMOS business units).
Continue reading “GLOBALFOUNDRIES Extends the FDSOI Roadmap”
This is the first in a series of CEO interviews and I thought semiconductor IP would be a great place to start. Xerxes Wania is the President and CEO of Sidense, a leading developer of Non-Volatile Memory (NVM) One-Time Programmable (OTP) IP cores. Sidense has been a part of SemiWiki since 2013 so we know them quite well. I hope the rest of the CEO interviews are as engaging as this one:
What are the challenges facing IP providers today?
A big challenge for any IP provider is understanding a particular customer’s requirements and providing the product and service to meet those requirements. Every IP implementation is in a different system environment, in other words, on a different chip. This means that we need to have a good system-level understanding of the customer’s design along with good communication with the customer to assist in their use of our IP.
This brings up a second problem – lack of an industry-wide quality standard for IP user acceptance of a piece of IP. Customers each have their own quality acceptance criteria, so at Sidense we have a good understanding of what this criteria is and work with the customer, as needed, to meet their requirements.
A specific issue facing providers of hardened IP (like OTP) is having qualified / proven IP available at the time the customer wants to tape out their design. This is compounded since customers want flexibility to move between foundries and fabs for price and or capacity reasons. Sidense addresses this issue by anticipating the intersection between its own roadmaps and that of the customer and by fostering close relationships with the foundries so it gets early access to Spice and PDK information.
What is driving the accelerating growth in OTP adoption?
Several factors; namely the continued growth of electronic-based products (and at only 2% world-wide GDP, there is still a lot of room for further growth) and increasing use of ICs in newer applications such as the Internet of Things and automotive. The latter brings its own challenges like compliance with new safety standards and higher temperature of operation. Chip designers are also realizing that there is not a “one size fits all” in memory. Embedded memory has many uses – code and key storage, analog and sensor calibration and trimming, device configuration, secure key storage and device identification. Our 1T-OTP memory has many benefits when compared to alternative NVM technologies – these include high security, high reliability, low implementation cost, low power and field programmability. Customers are recognizing the advantages of using our OTP in their chip designs in accelerated time to market and increased end-customer satisfaction.
2015 was a record year for M&A activity and it appears that 2016 has been picking up recently. How do all these Mergers and Acquisitions affect small IP providers like Sidense?
2015 was remarkable, not in the number of mergers and acquisitions – 30 – but in the total dollar amount – $102B. 2016 started more slowly, but the M&A pace has definitely picked up over the past few months. M&A activity is driven by several factors – economies of scale, access to new markets and technologies, financial advantages (i.e., cheap money for borrowing) and government regulations. When these factors are favorable, as is the case in 2015 and so far in 2016, M&A activity increases.
However, M&As are a mixed bag for the small IP company. If one of the M&A companies is a currently a customer, you might end up licensing the other company by default. Another scenario is that a company already has the technology you offer, or a strong bond with an alternative supplier, in this case you lose out.
Which markets do you feel offer the most and best opportunities for your NVM products over the next few years and why? Is there a killer app somewhere in these markets?
At Sidense, we see great potential in the mobile and automotive markets in both the near and long term. While cell phone sales have plateaued, they still represent very large markets, particularly in the APAC region and specifically in China, and India. Much of the expected growth in IoT depends on a mobile communication device to control and read IoT edge devices. As is the case with most Smart Connected devices security, high reliability and low power are important 1T-OTP attributes valued by our customers.
As for the automotive market, automotive electrification and autonomous vehicles are leading analysts to project a CAGR over the next 5-6 years of around 6%. PMICs for power controllers, displays and other automotive systems provide a huge opportunity for OTP, as does the ramping up of more complex infotainment and more rigorous safety standards. At Sidense, we have developed 1T-OTP macros for implementation in high voltage and BCD process nodes, as well as qualifying products up to the AEC-Q100 Grade 0 operating temperature specification of 150°C for “under the hood” and transmission systems. We are also working on meeting ISO-9001, ISO 26262 Functional Safety and other automotive requirements and standards for our OTP macros.
As for a “killer app,” I don’t think there is consensus on one or two in the foreseeable future. Some to keep an eye on, however, include Augmented Reality displays, Healthcare monitoring wearables, Smart Home controllers and Smart City management.
As IoT development continues to accelerate, security for IoT devices is lagging. What is Sidense doing to help enhance security for the ICs in which your 1T-OTP macros are embedded?
We are addressing IoT and other Smart Connected market-segment concerns in several ways. Within Sidense, along with the intrinsic highly secure properties of the 1T-OTP bit cell, which does not use charge storage to determine a bit-cell state and whose programming is irreversible, we have several ways of implementing anti-hacking mechanisms in our OTP macros to provide a secure NVM system architecture. These include de-layering protection, redundant and differential read modes, program locks, hidden address sectors and temperature compensation, just to name a few. We are also partnering with companies whose core competencies include securing silicon assets and have had our 1T-OTP security confirmed by multiple independent laboratories.
Autonomous cars are a hot topic. What do you see as the major challenges in bring a fully autonomous car to the market place and how can Sidense OTP help meet these challenges?
Autonomous vehicles are indeed a hot topic, but there are several obstacles to overcome. These include government compliance and automotive industry requirements (which are still in flux), various technical issues and driver attitudes (do I want to give up control of my car?). Even more than now security will be a concern as cars become more connected, car-to-car, car-to-person and car-to-cloud, as they become autonomous driving machines.
Sidense 1T-OTP will be used in many applications to store secure code and update it when necessary, store secure encryption keys, and trim and calibrate analog circuitry and the many sensors the vehicle will employ. As the number of sensors in a car continues to increase, and we feel that the move to autonomous vehicles will sharply increase the number of sensors per car, the need for secure, low power and reliable Sidense 1T-OTP will rise as well
What innovations are Sidense working on that you would like to share with SemiWiki subscribers?
It’s a great time to be at Sidense, there is a lot going on. And it is not just limited to new technology developments, but to the many changes related to being a successful and growing company. Recruitment, staff development, infrastructure, processes, and facilities all need careful consideration and deployment.
In response to some of your prior questions I hinted at some of the exciting developments underway here at Sidense: Developments that include low voltage operation, products capable of providing high reliability over elevated temperature and enabling advanced security features. But we should also not forget development at advanced nodes such as 16, 10 and 7nms. I could go on but will finish by saying the future looks bright and exciting for Sidense and our customers.
Also Read:
A Candid Conversation with the GlobalFoundries CEO!
