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Emulation as a Multi-User Shareable Resource

Emulation as a Multi-User Shareable Resource
by Bernard Murphy on 09-19-2016 at 7:00 am

One of the great advantages of emulation is that runtimes are much faster than for simulation – sufficiently fast that you can really debug hardware together with software for comprehensive use-case testing. A not so great aspect is that emulators are expensive and, until relatively recently, not particularly easy to share across concurrent projects. That tended to focus emulation use only on the biggest, baddest, highest-revenue project you had in the shop at any given time. Which wasn’t great for optimizing return on that sizeable investment (the emulator sits idle during test development and debug, before verification starts and after tapeout), or for justifying capacity increases for the next even bigger project.

In fairness, vendors have offered forms of multi-user support for many years, but not really what we have come to expect for general-purpose systems where we don’t really care who else is using the system, or how many people are using it or what kinds of jobs they are running. We expect the OS to manage loads and maximize utilization while providing a fair balance in prioritization. Of course emulators aren’t general-purpose computers, so advancing the technology to provide this level of support wasn’t trivial. But true support for multi-user concurrent job support on emulators is now available with sufficient capability that you can now think of emulation as a multi-tasking datacenter resource, right alongside the servers you use for more conventional software tasks.

But it still requires a bit more thought to effectively load datacenter emulation than it takes for those servers. Frank Schirrmeister (Mr. Emulation, among other things, at Cadence) has written a white-paper on what you need to think about to optimize workload mixes in a virtualized emulation environment. Frank breaks it down into four pieces: Build, Allocate, Run and Debug.

The tradeoff between build-time and run-time is a good test of how a given emulation solution will fit with your job mix. Some platforms emulate quickly but build takes a long time. These systems would work well in mixes where runs dominate compiles – where each design is setup once for many long regression tests before cycling to the next round of design fixes. That profile would not work as well in mixes where you have a more heterogeneous range of objectives and where you might cycle more frequently to design fixes.


When you want to emulate 😎 general-purpose load-sharing as closely as possible, allocation is an important consideration. Jobs don’t come in fixed sized at fixed times, they end at different times and they may have different priorities. A big part of effective utilization is managing these varying parameters effectively, for maximum utilization and maximum throughput. Doing that requires an OS which can manage queuing, prioritization, task swapping and all the other features you take for granted in a multi-tasking OS.

There’s another factor too – one you probably don’t even think about – the granularity of emulation resources. Emulation task sizes can’t drop to the low levels possible in a general-purpose system – these are specialized resources after all. But the smaller the minimum size that can be supported, the more completely you can pack the space on average, so the more jobs you can service (for a distributed set of tasks) per unit time. It’s a basic tiling problem – if you have a mix of job sizes, a finer granularity gives you better utilization.

Another consideration is how effectively you can debug. Debug in the emulation world is necessarily in batch – you couldn’t afford to have an emulator occupied but idling while you’re scratching your head over a bug. So you have to decide before you start a run what signals you want to probe and over what time windows. This being hardware, there will be some constraints on these factors, and a poorly-chosen debug list may mean you have to rerun after you figure out what signals you missed, possibly more than once if a bug is far-removed from the root-cause. Also important to consider is whether updating the debug list also requires a recompile, which will further increase turnaround time on a rerun. Yet another factor is whether increasing the size of debug lists may slow emulation. These factors together require a careful balance and planning of debug strategy to ensure overall effectiveness of emulation in your shop. In general, support for big debug lists and trace windows will reduce the need for overthinking emulation runs.

Finally, give a thought to how ROI can be further improved by strong interoperability between verification methods. These often require transitions between simulation, emulation and prototyping. For instance, there is growing interest in using emulation as a way to accelerate or more accurately model components in a simulation. Here the emulator, operating in slave mode to a master simulation, models a device in an ICE environment or in a virtual equivalent. Similarly, easy transitions between FPGA prototyping and emulation, and between emulation and simulation help you get the best out of both platforms by letting the verification team get quickly to a starting point where they can then switch to a platform which allows for more detailed debug. Again this interoperability is especially important when the fix cycle is relatively short so restarting from a checkpoint won’t often help.

To read Frank’s more detailed analysis, click HERE.

More articles by Bernard…


Digital – what is different about it?

Digital – what is different about it?
by Sudeep Kanjilal on 09-18-2016 at 4:00 pm

A very basic question, surely, but something that has been surprisingly difficult for many to answer coherently! There is no universally acceptable description or definition out there. Many use digital and mobile interchangeably, some more technology-minded define Digital by use of APIs (and differentiate it from ecommerce with an app-vs-browser distinction), and some define Digital based on operating system/runtime – digital is iOS and Android based ecosystem.

In my humble opinion, to get a proper definition, one needs a proper perspective. So, allow me to ‘zoom out’ and talk not in terms of decades, but millennia!
There have been, roughly speaking, 4 main revolutions that has driven human civilization forward from the stone-age to the current age:

  • Agriculture Revolution – lasted about 6 millennium. Powered primarily by human power, massive increases in calories-yield-per-acre (as compared to hunting), resulting in settlement and specialization of labor (productivity improvement).
  • Metallurgy Revolution – lasted about 3.5 millennium. Powered primarily by animal power and far better tools, significant increases in productivity, resulting in large empires
  • Industrial Revolution – lasted about 3.5 centuries. Powered by engines, another significant jump in productivity, resulting in global-spanning empires
  • Information Revolution – currently underway for the past 50 years.

The current Information Revolution, predicted to last at least another 100 years, has already proved immeasurably consequential for human civilization. It has established and powered an integrated global economy, reversed the power structure from strong unitary states (empires) to giving voice to billions of citizens, impacted and changed culture, turbo-charged innovations and enabled massive increase in human knowledge – 90% of all scientists that ever lived are alive today!
Digital is simply the next phase in this ongoing information revolution.

Its all about Information Asymmetry
So how does digital fit into the overall narrative of Information Revolution? How do we recognize it? What is the impact of this current ‘phase’? And how do we measure it?

Digital impacts our world, and especially culture and productivity, by correcting a very basic market failure – information asymmetry. Information asymmetry is a known case of failure in market economy, referring to situation where one of the party in a transaction has less information, and hence power, than the other party. As a result, the party with less information pays a penalty in terms of price, and as a result, market-clearing price is distorted.

At its core, Digitization generates data – the lifeblood of information revolution – but in a unique twist, spreads the data evenly.

Advances in computing accompanying (and driving) digitization spreads computing power evenly. This is, of course, a central trend across the entire information revolution cycle – advanced in underlying computing architecture and ecosystem from mainframe to client service to web ecosystem to distributed cloud-based on-demand handheld computing means computing power, resources and data is increasingly getting generated and consumed at the edge.

Advances in run-times – GUI to browser to api to bots – also empower the ‘edge of the network’. Trends in UI (man machine interaction) capabilities – from ‘text based command-line’ to ‘point-and-click GUI’ to ‘fat-client browsers’ to ‘multi-touch glass interface’ enabling a much deeper interaction to the coming ‘Augmented Reality’ based interface are all part of the overall digitization trend – of reducing information asymmetry.

This has profound implication on market efficiency, something that will play out over decades. Given that the world economy is about $80 trillion, a 10% improvement in price setting/market efficiency can release $8T each year into the economy – to drive further investments and growth.

We have already seen impact of this virtuous cycle in the past 2 decades – and as the new digital technologies permeates thru every sector of the economy over the next couple of decades, this cycle will kick in again.

New Business Models
Further, digital also fundamentally flips business models. For past several centuries (the industrial revolution), the core driver of productivity, profitability and business models was ‘economies of scale’. Basically, as firms gain scale, their cost-per-unit drops and thereby, gain a runaway effect of increasing scale thru reducing cost.

If one thinks carefully thru, there is however an element of information asymmetry that favors the larger firms viz-a-viz consumers. Larger firms leverage their scale to not only reduce cost, but also gain privileged access to resources and market data/prices.

Digitization not only reduces information asymmetry, it also enables new business models based on demand-size economies of scale – thru network effect. By generated and transmitting valuable commerce-intent data across network, digital savvy firms can leverage the same to create network economics, driven by Metcalf law (v = n^2) or even Reed’s law (v = 2^n) and can tip the market.
For example, in 2007, when iPhone was first introduced, 5 firms accounted for 95% of global phone market profits. Apple was just a new entrant, with no telecom related IP, no telecom supply chain, no core telecom technology, no carrier relationship (distribution network) and no experience of running a complex analog electronics based consumer devices (it is much harder than digital electronics devices). Yet, by 2015, itunes based network effect enabled Apple to ‘tip’ the market and garner 95% of global smart phone profit. Meanwhile, only one out of the previous 5 market leaders even survived!


IOT and Assisted Living

IOT and Assisted Living
by Bill McCabe on 09-18-2016 at 12:00 pm

It is most likely the you have heard the term “internet of things”or IOT in regards to everyday things such as our televisions and phones. That is not however where this new innovation is going to end. There has been a lot of talk about the IOT stepping into the healthcare industry with things like connected healthcare.

Another area where we can expect to see the IOT playing a large role is in assisted living. It is no secret that people are living longer than we ever have before. It has even been said that the first person to see the age 150 has already been born. It should come as no surprise then that nursing homes and senior assisted living facilities are full to bursting with elderly people whom are healthy but incapable or afraid to live on their own. The IOT could help with this.

We are all familiar with products such as Life Alert that have been used to give seniors a sense of security in their own home. These types of things allowed seniors to remain in their homes longer than before. They are not perfect though. The fact is that the technology behind these types of monitoring devices is out dated. It relies on a live person being available 24/7 to respond to the individuals call for help. What happens when the person in question does not have the capability of triggering the monitoring device though? This is where the IOT can step in.

Recently engineers have developed sensors that can be placed discreetly throughout the home. These sensors then monitor the resident’s movements and activities throughout the day. These sensors rely not on a live person monitoring them, but on algorithms and programming that over time learn the normal habits of the person living in the home. They monitor things such as…

  • location of the resident within the home
  • light sources being used
  • bed time and awakening time
  • television watching
  • cooking
  • bathroom usage
  • leaving the home and returning
  • heating or air conditioning temperature and adjustments

Then in the case of an emergency or variations to that pattern that do not fit the normal activity within the home can notify family members or medical professionals.

Another development is something similar to that of Life Alert but more sophisticated. Wireless vital sign monitors. These devices can notify first responders of medical emergencies such as stroke, heart attack and a loss of consciousness without the person suffering having to do anything at all. Further they could notify patients of an issue well before it actually happens, such as notifying a heart patients doctor that their heartrate has been erratic over a period of time, thus indicating that further investigation may be needed. It is not hard to see that very soon we could see the IOT playing a large role in the lives of our seniors, or anyone that needs some form of assistance.

For more information about IOT and Healthcare please check out our new website www.internetofthingsrecruiting.com


VHDL parameterized PWM controller

VHDL parameterized PWM controller
by Claudio Avi Chami on 09-18-2016 at 7:00 am

Digital outputs can either go ON or OFF. Analog signals, on the other side, can smoothly assume multiple values in a range. There is a technique that emulates analog behavior with a digital output. That technique is PWM, namely, Pulse Width Modulation. It can be implemented as pulses with varying ‘high’ and ‘low’ duration. However, one rather simple implementation is to take a fixed output frequency and vary only the duty cycle. If the pulses are fast enough compared to the response time of the system, a PWM is equivalent to a varying analog signal, whose amplitude is proportional to the duty cycle.
Continue reading “VHDL parameterized PWM controller”


KLAM Kommentary – Assessing the political landscape of approval

KLAM Kommentary – Assessing the political landscape of approval
by Robert Maire on 09-16-2016 at 12:00 pm

LRCX & KLAC’s merger continues to be closely watched given the recent turns and reversals we have seen which call into question the ability to get the deal done. The deal was announced in October of 2015 and we are on our second request from the DOJ and the deal will almost certainly go beyond the Oct 20th, one year deadline to get it done.

We still think that the probability of deal approval is over 50% but that the remedy and other potential business costs will likely increase making the deal less attractive than when first announced.

On Semiconductor and Fairchild – Throw the dog an IGBT bone……..
A good comparison to the KLAM deal is the $2.4B acquisition of the storied Fairchild Semiconductor by On Semiconductor. The deal was announced on Nov 18th of 2015, about a month after the KLAM deal was announced and much like the KLAM deal also got a second request from the DOJ in March.
The issue revolved around the IGBT (Insulated Gate Bipolar Transistor ) business’s when combined would exceed 60% market share in the automotive segment, which was a clear HSR issue.

Our observation is that while it is clear that its an HSR issue the amount of business involved is only about $25M per year which is not even a rounding error in the $2.4B deal. For the DOJ to care so much about so little gives you an idea about the state of affairs and current attitude about M&A deals inside the DOJ. Obviously every deal gets the microscope treatment and the DOJ obviously listens to every complaint even if its the auto industry which is hundreds of billions complaining about a component that costs relative pennies and is an even smaller rounding error on a rounding error in the industry.

On Semiconductor made it clear when the second request came out that they were willing to divest the IGBT business back in March and the deal was recently approved and ON Semi announced it had an agreement to divest the business.

Basically it took five months from agreeing to divest to find a buyer and get DOJ clearance.
In the case on ON Semiconductor, it was relatively easy for them to agree to throw the DOJ dog a small bone, the IGBT business, in order to win approval. It was far from crucial to the deal so it was a no brainer.

In the case of KLAM, however, the potential remedies are not small nor insignificant, and there is no small bone to throw the DOJ , only an arm or a leg, as the CD (critical dimension) or thin film businesses are key to the suite of products that KLA provides.

This obviously makes for interesting discussions and negotiations with the DOJ. The timing could get very long and border on AMAT/TEL timing if we compare that ON Semi was announced a month after KLAM and only just got approval of a simple divestiture. It implies that the deal could drag out along time.

For more info:
FTC IGBT Agreement
FTC anti competitive analysis

Comcast & Dreamworks…..Problems with the Panda…
Recently China’s MOFCOM (Ministry of Commerce, the equivalent of the FTC/DOJ) announced an investigation of the proposed $3.8B acquisition of Dreamworks, the animation studio that brought us notable classics such as Kung Fu Panda, by Comcast the cable giant. The deal was originally announced in April but recently MOFCOM said it received several anti-competitive complaints that triggered the investigation.

Given that China has made it a strategic goal to become a leader in semiconductor technology and has already been active in spending an alleged $100B war chest dedicated to the semiconductor industry we would imagine that MOFCOM may be even more interested in chips than cartoons…..

China has be rebuffed in several instances in buying US technology companies and was also rebuffed in its efforts to buy Fairchild with an offer higher than ON Semi.

There are small equipment companies in China like AMEC that both Applied and Lam have gone after in recent years.

China has also investigated and fined a dozen M&A deals this year alone for “gun jumping”, proceeding with a deal without prior approval. This suggests that China is already sensitive to M&A deals that are not in its national interest (and KLAM is certainly not).

The KLAM combination is likely scary as China has no domestic companies with similar technology to KLA. AMEC does compete with Lam and Applied but has been really held back by these larger competitors.KLAM likely really hits a very sensitive spot with Chinese regulators. The prospect of KLA and Lam getting together is a lot more scary to Chinese regulators than a fluffy Panda.

Uncertainty discounts and spreads….
The stocks of LRCX and KLAC have not suffered too much from the added uncertainty of the deal. We would continue to be owners of KLAC but think that LRCX is overdone over $90 especially given deal uncertainty.

There is likely near term risk with trickle down from the Apple announcement in addition.
As we have said from the very beginning when the deal was announced, it will take longer and cost more than predicted, and so far we have been correct…..

Every additional day that goes by increases costs and risks and reduces synergies. Much as Lam flourished while Applied and TEL were engaged so has Applied flourished while the KLAM engagement has gone on…..


Developing Countries – Unlikely Champions of IOT

Developing Countries – Unlikely Champions of IOT
by Bill McCabe on 09-16-2016 at 7:00 am

When considering any new or emerging technology, it can be easy to immediately think of the potential implementation in developed markets. After all, these are the markets where consumers have high purchasing power, and businesses and governments have strong credit lines and funding options. Well, wouldn’t it be a surprise to learn that the developing world will likely be responsible for almost half of all revenue generated by IoT? This is exactly what a 2015 report from the International Telecommunication Union stated, and if you look at trends and innovation around the world, there is evidence that supports the prediction.

Industry Leaders Recognize the Value of IoT in Developing Markets
Take India as an example. Although it is one of the largest countries by area, and the second most populous in the world, it is still considered to be a developing country by leading economists. Even so, there are some areas where India is a leader in IoT. In 2015, IBM selected the Indian city of Vizag as a winner in their Smarter Cities Challenge. This city wants to improve its disaster preparedness and response programs through the use of IoT technologies, and with the help of IBM, the government will work towards implementing a sensor based utility grid, improve citywide electronic communications, and develop an emergency command center that uses historical data and machine sensors to better predict and respond to natural disasters.

This program has the potential to attract foreign investment, create jobs, and save lives.

Markets That are Ideal for IoT Investment
One reason why developing nations are prime for IoT investment is because many of them can make immediate use of IoT technologies for critical applications. In the gridlocked Philippine region of Metro Manila, government agencies are using connected machines to monitor traffic in real time and provide public alerts. The metropolitan area is served by a number of CCTV systems and sensors that can be accessed through APIs, allowing for news stations and privately developed smartphone apps to provide instant updates to the general public.

Safety is also an issue in many developing countries, and again, we can use Metro Manila as an example. The region’s widely utilized MRT rail lines are often overcrowded and sometimes dangerous. With connected technology, members of the public can already access the MRT security CCTV feeds from smartphones and web browsers, allowing them to view real time platform video to help plan their daily commutes.

Perhaps one of the biggest advantages that developing countries have is that they are lacking in some areas of infrastructure. A developing city that now has the funds to invest in widespread water metering will have more incentive to use accurate and efficient machine driven meters. By contrast, a long developed city would have to weigh up the cost savings of an IoT based system, compared to the efficiency of their current metering system.

IoT Infrastructure Can Be Built on Existing Cellular Networks
Despite lack of infrastructure in some areas, LTE penetration is high in a number of developing economies, meaning that there is increased opportunity for bringing IoT services to corporations and the general public. India has LTE penetration throughout more than 50% of the population, which means that there is potential to connect more than half a billion people to the Internet of Things. China, which could be considered still developing in some provinces and cities, boasts LTE coverage across 76% of the mainland. That’s only two points behind the United States, and China has more than four times the population, allowing for massive opportunity in the consumer and public service IoT sectors.

While the developed world is no doubt leading in IoT innovation, developing countries will contribute significantly to revenue, adoption, and investment. With more than $6 trillion in worldwide IoT investment expected by 2020, developers and innovators cannot afford to ignore the world’s developing economies.

For more information please review our new website www.internetofthingsrecruiting.com


Market Trends Motivate a Shift-Left in Functional Verification

Market Trends Motivate a Shift-Left in Functional Verification
by Jean-Marie Brunet on 09-15-2016 at 4:00 pm

Today, in the context of functional verification, industry trends are based on the needs of prominent vertical markets. There is some overlap in what these markets need, but there are some use models that are very specific to each market.

We assert this because we have a lot of customers asking about emulation solutions not from the standpoint of methodology, but from the needs of their specific vertical market. These include networking, storage, mobile multimedia, and automotive.

We’re excited about the new things Veloce has to offer these customers. A primary force behind these is a shift-left in the verification flow. We provide the means for that shift-left to become a reality.

A shift-left means that a lot of things companies used to do late in the verification flow cycle they now do much earlier. It also means that hardware and software verification is done at the same time, using either a software stack or script to generate the traffic flow. This way it’s clear very early on that the hardware being implemented behaves correctly with the software being provided.

A shift-left greatly reduces the risk of designing very large systems and ICs. So this is obviously an overlapping need and advantage for all the vertical markets. In addition, we have other new solutions for these markets.

Let’s start with networking. The biggest networking companies in the world need greater capacity to emulate their designs. Their chips are very big, so they need an emulator like Veloce, which is still the only emulator that can do a billion-gate design in a single monolithic box. Our competitors need a couple of boxes connected together to do that. Further, because of Veloce’s capacity, performance, and flexible use models, it is the industry’s leading networking emulation solution.

Most networking companies validate their chips in the lab using an Ethernet tester. This involves a lot of connections and a lot of cables to make those connections. Traffic is applied to the silicon to verify that the behavior of that particular design is running at-speed and the traffic is generated and behaving correctly. But, the verification process cannot begin until silicon is available. And if there is a problem at this stage, it takes a great deal of work, time, and money to fix…if you can fix it at all.

In response to requests from networking companies, our R&D team collaborated with Ixia to create an emulator-friendly network verification solution that is fully integrated with Ixia‘s number one Ethernet tester. Rather than creating a testbench for a particular networking chip and compiling it along with the design on the emulator, we use, directly, the Ixia script. The result is a cleaner setup for verifying Ethernet traffic and a shift-left in the design cycle using a solution that puts together the two leaders in the networking verification space.

In the storage market, the trend is toward bigger die sizes. So again, there’s a need for capacity and virtualization. There’s also more and more software content on storage devices that needs to be verified. ICE is still extremely important for the storage vertical market because of all the external connections to physical memory, and so on. But they need an ICE environment that is deterministic (i.e., repeatable) so that thorough debug can be completed.

This is why we launched our Veloce Deterministic ICE App in early 2016. With Veloce Deterministic ICE we have provided something in the ICE environment that is far better than anything our competitors can do. We made the ICE environment deterministic, so you can repeat the behavior of what you are verifying and therefore fix any bugs.

For the mobile multimedia market, we see two recent trends. Power is extremely important. They want to know if the chip is using what they are predicting in terms of power, rather than finding that problem on the board, which is way too late to fix. The Veloce Power App that was launch in 2015 has been very successful as a solution to this problem, including earning an EDA industry award.

The second trend for mobile multimedia companies is the need to verify hardware within the full software context of the application. Their end customers evaluate their chips by running something like an AnTuTu Benchmark. Based on the performance and metrics report they get on that benchmark, they’ll know if their chip performed correctly. So a shift-left is called for again because mobile multimedia companies want to validate their chip, not only from a testbench perspective, but within the full software context.

Finally, another big story in 2016 is the automotive market. Mentor has been very strong in the automotive market for system and ICs, so we have a lot of customer experience and knowledge and methodology and IP in this domain, and we are now seeing how emulation fits into the total solution. For example, advanced driver assistance systems (ADAS) must adhere to specific methodology requirements to verify that the chip is ISO 26262 Compliance. This requires a lot of full-system simulation and a lot of coverage performed on the chip. And this requires the capacity and performance of emulation and a shift-left in the verification flow.

To find out how your company can benefit from a shift-left emulation flow powered by the Veloce emulation platform and Veloce Apps, check out mentor.com. A good place to start is our whitepaper focusing on the networking market, Accelerating Networking Products to Market Using Ethernet VirtuaLAB.


GlobalFoundries Roadmap Update 2016!

GlobalFoundries Roadmap Update 2016!
by Daniel Nenni on 09-15-2016 at 11:00 am

I attended a lunch yesterday with GlobalFoundries CEO Sanjay Jha (formerly of Qualcomm), SVP Gregg Barltlett (Motorola/GF), and CTO Gary Patton (IBM). Having followed GF from the very beginning I can tell you without a shadow of a doubt that GF has transformed from a collection of companies (AMD, Chartered, IBM) to a fully integrated pure-play foundry.

There were a dozen other media people in attendance who will cover the bullet points presented so let me comment on the leadership aspect. Having met Sanjay, Gregg, and Gary multiple times separately, I found it very interesting to see them interact as a team.

You have to remember these gentlemen come from very different backgrounds and experiences but one thing I can tell you is that they truly worked in harmony during this event which is not always the case with other companies. In my opinion the credit goes to Sanjay as he is an exceptional leader and knows the semiconductor industry from the very top (end product) down to the very bottom (device level), absolutely.

In fact, I would put Sanjay in my current top 10 Semiconductor CEOs list with Hock Tan, Jen-Hsun Huang, MK Tsai, Morris Chang, Amit Gupta, Joe Costello, Lip-Bu Tan, Wally Rhines, and Aart de Geus.

In my opinion, under Sanjay’s leadership GF will become an industry leader versus follower. The FDX family of processes is a clear example. GF will be the only pure-play foundry to deliver leading edge processes using both FinFET and FD-SOI technology which I think is astounding. So, while the other foundries are trying to fit every design into a FinFET, GF gives us a choice between high performance and lower power and lower cost.

Okay, back to the presentation, GF is rolling out their 22FDX (FD-SOI) process and announced a 12FDX process. 22FDX is competitive with 14nm and 12FDX is targeted at 10nm FinFET processes. As we all know, FD-SOI enables lower cost and lower power chips and GF will be the only pure-play foundry with sub 28nm FD-SOI process technologies.

In regards to FinFETS, the good news is that GlobalFoundries and AMD are scheduled to start 7nm production in 2018 which means AMD could have 7nm chips a full year before Intel. The bad news is that TSMC will start 7nm production in 2017 which means other fabless companies (ARM based server chips for example) will have 7nm chips 6 months before AMD. TSMC and Intel also have the advantage of a 10nm process yield learning experience that GF and AMD do not since they skipped 10nm, so there is an additional risk of delay.

It will be interesting to see how TSMC and Samsung respond to this. The TSMC OIP Ecosystem Forum is next week so we will find out then but today I saw a new and improved GlobalFoundries (GF 2.0) and am quite impressed with their progress.


Intel Stratix 10 MX FPGA Highlights

Intel Stratix 10 MX FPGA Highlights
by Claudio Avi Chami on 09-15-2016 at 7:00 am

These days, FPGAs are fairly complex pieces of silicon. Being that the case, it would take several articles even to put a summary of the features embedded in high-end FPGA devices. Hence, in this article, I will concentrate in just one feature, namely, the new embedded memory blocks of the recently released Intel-Altera Stratix 10([SUP]1[/SUP]).

Even medium sized FPGAs include quite a big quantity of memory blocks. For example, Altera’s Cyclone V family includes memory blocks in the range of 1.4 to 12.2 Mbits ([SUP]2[/SUP]). These memory blocks are not concentrated in a single spot but distributed over all the FPGA silicon, to reduce routing complexity when connecting the memories to the FPGA logic blocks. These memory blocks find plenty of uses: buffers, FIFOs, filters, fast memory/cache for embedded processors, register banks, etc.

As useful as these banks are, they are light-years away, size-related, compared to today’s DDR memory banks. Well, this has changed completely with the release of Stratix 10 MX, since these devices embed DDR memory banks. Intel’s acquisition of Altera has had many consequences, one of them being the merging of technologies from both firms. The Stratix 10 MX includes Intel’s Embedded Multi-die Interconnect Bridge (EMIB) technology, to interconnect between the FPGA fabric and the DDR memory blocks.

The DDR memory blocks used on the FPGA are 3D stacked blocks, integrating high speed data channels, dubbed HMB2 – High Memory Bandwidth. The HMB2 3D memory is connected to the FPGA core through parallel channels. Each channel can provide a bandwidth of 16Gbps, multiplied by 16 channels, give a total bandwidth of 256Gbps.

Moreover, the memory is separated in up to 4 “tiles”, each one connected with its own 16 data channels. The total bandwith for four tiles is of 1Tbps. Compare this number with current BW from a DDR1600 memory bank, which is in the order of 100Gbps, or even DDR2133, which provides around 140Gbps.

Currently available Stratix devices have embedded memory banks ranging from 4 to 16 GByte. In case you were wondering, these new memories do not replace the aforementioned static memory banks. Stratix MX 10 devices have between 86 to 127 Mbit in static memory blocks.

Other advantages of the integrated memory blocks, compared to current distributed solutions ([SUP]3[/SUP]), include lower power consumption and reduction of the real estate on board, as well as a reduction in PCB interconnection complexity.

The availability of these new devices promises to change the architecture for solutions that are currently dominated by CPUs and/or GPUs, like database management, cyber security, genetic algorithms and deep machine learning. For an example regarding this last category, please refer to my article: FPGAs and Deep Machine Learning

My blog: FPGA Site

References:
Stratix 10 MX Devices Solve the Memory Bandwidth Challenge
Altera’s 3D System-in-Package Technology
Stratix 10 MX Product Overview Table

Image Source:
Stratix MX10 blocks – Intel/Altera

Notes:
(1) – Altera and Xilinx are the major players on the FPGA arena. Last year (2015) Altera was acquired by Intel.
(2) – These numbers can be increased a bit more, around 15%, by converting some of the ALM logic blocks onto memory blocks.
(3) – A typical distributed solution is based on separated CPU, FPGA and memory SODIMM cards, compared to the Stratix MX10 solution that includes CPU (ARM Cortex), FPGA, and memory on a single package.