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CEO Interview: Sean Park of Point2 Technology

CEO Interview: Sean Park of Point2 Technology
by Daniel Nenni on 10-25-2024 at 6:00 am

Sean Park scaled

Sean Park is a seasoned executive with over 25 years of experience in the semiconductors, wireless, and networking market. Throughout his career, Sean has held several leadership positions at prominent technology companies, including IDT, TeraSquare, and Marvell Semiconductor. As the CEO, CTO, and Founder at TeraSquare, Sean was responsible for leading the company’s strategic direction and overseeing its day-to-day operations. He also served as a Director at Marvell, where he provided invaluable guidance and expertise to help the company achieve its goals. He holds a Ph.D. in Electrical Engineering from the University of Washington and also attended Seoul National University.

Tell us about your company?

Founded in 2016, Point2 Technology designs and manufactures ultra-low power, low-latency, and scalable interconnect mixed-signal SoC solutions. Headquartered in San Jose, California, Point2 is bringing interconnect technology to extend the reach of copper cabling and introducing an innovative technology to the market – e-Tube – that better addresses the terabit network bandwidth requirements inside the next-generation Artificial Intelligence (AI) / Machine Learning (ML) datacenters.

What problems are you solving?

Today’s datacenters rely on 400 gigabit (400G) Ethernet network devices that are transitioning to 800G. Point2’s UltraWireTM Smart Retimers are purposed-built for active electrical cables (AECs) to extend the copper cable reach required for in-rack and adjacent rack applications. AECs built with Point2’s UltraWireTM Smart Retimers consumes 40% less power and are 75% lower in latency. As AI/ML applications drive datacenters to 1.6T speeds and beyond, yesterday’s copper and optical interconnects, cannot scale to the future terabit requirements. Typically, optical technologies offer the speed and the bandwidth required but are expensive and power-hungry with temperature variability and reliability issues. Copper, the most cost-effective option, experiences significant signal loss at higher speeds with limited cable reach. Finding the optimal solution to overcome the limitations of these two technologies – scalable bandwidth, low power consumption, low latency, and at comparable cost to copper – is a daunting challenge for the datacenters. e-Tube is the answer.

What is e-Tube?

e-Tube is a scalable interconnect technology platform using RF data transmission through a plastic dielectric waveguide made of common plastic material, such as Low-Density Polyethylene (LDPE). Active RF cables (ARCs) built with e-Tube technology provides the ultra-low latency, energy-efficient, interconnect solution that is ideal for top-of-rack (ToR) to Smart NIC, ToR to ToR, and accelerator-to-accelerator connectivity in AI/ML data centers. e-Tube eliminates the fundamental limitations of copper at terabit speeds by supporting up to 7m cable reach with 50% of the cable bulk and 20% of the weight at a similar cost structure. Compared to optical cabling, e-Tube consumes 50% less power, with latency that is three orders in magnitude lower, at 50% lower in cost, and without temperature variability and reliability issues. This scalable technology is the ideal replacement for copper cabling for AI/ML in-rack and adjacent-rack applications.

What application areas are your strongest?

Point2’s expertise is in mixed-signal interconnect SoC designs with the lowest power and latency. Starting with our UltraWireTM Smart Retimers for 400G and 800G AECs that typically consume 40% less power and 75% less latency compared to other DSP-based Retimer solutions. Our cable partners have used these advantages to design and deploy AECs with hyperscalers and enterprises for switch-to-server and accelerator-to-accelerator connectivity for in-rack and adjacent-rack connectivity. With AI/ML data centers transitioning to terabit speeds, development for 1.6T and 3.2T ARCs is underway to address future AI/ML workloads. e-Tube technology is also expected to expand into ‘inside the box’ for chip-to-front panel and backplane applications with tighter integration with accelerator and switch ASIC manufacturers. This approach will deliver the higher interconnect bandwidth and port density required to keep up with future AI/ML accelerator speeds.

What keeps your customers up at night?

Over the next few years, AI/ML data centers must overcome three challenges simultaneously: 1) deliver better performance to meet soaring bandwidth demand; 2) contain costs while expanding in performance and complexity; 3) continue improving energy efficiency. It is this trifecta of challenges that keeps network operators up at night.

What is next for Point2 and the development of e-Tube?

The most important interconnect attributes are scalability, energy efficiency, low latency, and affordability. As the AI/ML workload evolves rapidly—pushing the limits on data rates with trillions of calculations being processed every second—it is vitally crucial that cabling interconnects support this rapid growth. Network requirements of 1.6T and 3.2T are approaching fast, and the industry must have the proper infrastructure to meet this demand while seamlessly adapting to new data rates. Our commitment is to continue to develop innovative interconnects that scale at the pace of the AI accelerators while achieving best-in-class energy efficiency and affordability required for mass deployment for the next-generation AI/ML datacenters.

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From Space-Central to Space-Time Balanced – A Perspective for Moore’s Law 2.0 and A Holistic Paradigm for Emergence

From Space-Central to Space-Time Balanced – A Perspective for Moore’s Law 2.0 and A Holistic Paradigm for Emergence
by Daniel Nenni on 10-24-2024 at 4:00 pm

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A friend of SemiWiki published an article on Moore’s Law in IEEE that I think is worth reading:

IEEE Signal Processing Magazine, Vol. 41, Issue 4.

The topic of Moore’s Law is of paramount importance, reaching almost the entire field of electronics (and the semiconductor industry). In the course of six decades, for the first time, this article proposes a strategic change from “Space-Central” to “Space-Time Balanced” for this “law”. It also challenges contemporary AI practices by arguing that consciousness cannot arise from the current reductionist paradigm (the first paradigm). By promoting a second paradigm of holistic nature, the term of Moore’s Law 2.0 is coined as its emblem.

The abstract of this article is enclosed as follows.

The history of electronics is studied from physical and evolutionary viewpoints, identifying a crisis of “space overexploitation”. This space-central practice is signified by Moore’s Law, the 1.0 version. Electronics is also examined in philosophical stand, leading to an awareness that a paradigm is formed around late 1940s. It is recognized that this paradigm is of reductionist nature and consciousness is not ready to emerge wherein. A new paradigm is suggested that diverts from the space-central practice to the foresight of putting space and time on equal footing. By better utilizing time, it offers a detour from the space crisis. Moreover, the paradigm is prepared for holism by balancing the roles of space and time. Integrating the entwined narratives of physical, evolutionary, and philosophical, an argument is made that, after decades of adventure, electronics is due for an overhaul. The two foundational pillars, space and time, ought to be used more meticulously to rectify the electronics edifice. This perspective of shifting from space-central to balanced space-time is proposed as Moore’s Law 2.0 and is embodied as second paradigm, a holistic one. The aim is to transcend reductionism to holism, paving the way for the likely emergence of consciousness.

The Outline of this article is given below:

First Paradigm: Space-Central Moores Law 1.0

Electronics’ history is reviewed. It is opined that a paradigm is formed circa the late 1940’s and Moore’s Law later becomes its mark. The quintessence is to make the basic processing unit ever smaller and assemble ever more of such units into a given space for higher processing capability.

Reflection: Physical, Evolutionary and Philosophical Aspects of Electronics

Electronics is examined under the scopes of physics, evolution, and philosophy. Useful insights are extracted that are used to guide the strategic discussions for future advance.

Edifice of Electronics: Transistor & Signal as Base and Space & Time as Pillars

The field of electronics is virtualized as an edifice. Its foundation is established on transistor and signal. Its two pillars are space and time. The show of signal processing is played by the transistor and signal on the stage sustained by space and time.

Overexploitation of Space: Heading into A Crisis

After decades of ruthless exploitation, the potential from space is exhausted and we are diving into a crisis. Two obstacles are firmly erected by quantum limit and the second law of thermodynamics, impenetrable however sophisticated our engineering skill will be.

Impotence of Logic Based Computing: Consciousness-less

The current electronics edifice is established on the bedrock of symbolic logic. Consciousness is unfortunately beyond the reach of logic and thus is not expected to emerge from this paradigm. Contemporary AI technologies are unable to address this fundamental deficiency.

More Is Different: Second Paradigm of Space and Time on Equal Stand

A new paradigm is proposed where space and time are valued equally. It offers a detour from the space crisis. With the awareness of space and time as vital notions for cognition, this paradigm is prepared for something deeper than the complexity grown out of the sheer increase in number of transistors.

Next Stage of Moores Law: from 1.0 of Space-Central and Reductionist AI to 2.0 of Holism

The space crisis and reductionist AI are ramifications of Moore’s Law, the 1.0 version. After decades of endeavor, it is time for us to ponder the electronics deeper and question the existing paradigm for its efficacy. This is reasoned as the motive for Moore’s Law 2.0, a holistic paradigm made for circumventing the space crisis and seeking of true intelligence.

The full article can be found in IEEE Xplore:

From Space-Central to Space-Time Balanced: A Perspective for Moore’s Law 2.0 and a Holistic Paradigm for Emergence [Perspectives] | IEEE Journals & Magazine | IEEE Xplore

The article can also be found here if you cannot access IEEE Xplore

(PDF) From Space-Central to Space-Time Balanced: A Perspective for Moore’s Law 2.0 and a Holistic Paradigm for Emergence [Perspectives] (researchgate.net)

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AI Semiconductor Market

AI Semiconductor Market
by Bill Jewell on 10-24-2024 at 2:00 pm

AI Semiconductor Market 2024

AI (artificial intelligence) is widely cited as a growth driver for the technology industry, including semiconductors. While AI is in its early stages, opinions vary on whether it will become common in the next few years. A McKinsey study from May 2024 showed 72% of organizations have adopted AI in at least one business function. These organizations saw the risks in AI as inaccuracy (63%), intellectual property infringement (52%) and cybersecurity (51%).

In the U.S., may consumers have concerns about AI. A Pew Research Center survey in 2023 revealed that the majority of people were more concerned than excited about AI (52%), 36% were equally excited and concerned, and only 10% were more excited than concerned. 60% of respondents were uncomfortable with the use of AI in healthcare. An AAA survey in March 2024 showed 66% of people in the U.S. were afraid of self-driving cars while only 9% would trust them.

Nevertheless, AI is here to stay and will have a major effect on the global economy in the near future. AI will have a significant impact on the semiconductor industry. A Gartner report from May 2024 estimated worldwide

AI IC revenue at $54 billion in 2023, $71 billion in 2024 and $92 billion on 2025. Forecasts of the compound annual growth rate (CAGR) of AI ICs over the next several years range from 20% (MarketsandMarkets) to 41% (DataHorizzon Research).

The AI IC market has undergone explosive growth in the last few years. NVIDIA is the dominant AI IC company. The revenue of its Data Center division, which includes most of NVIDIA’s AI, more than tripled from $15 billion in fiscal year 2023 (calendar year 2022) to $48 billion in fiscal 2024 (calendar 2023). It will likely double in fiscal 2025 (calendar 2024) to over $100 billion. We estimate NVIDIA’s AI IC revenue will be about $96 billion, most of the revenue from its Data Center division. NVIDIA’s latest AI graphics processor will sell for between $30,000 and $40,000 according to CEO Jensen Huang.

NVIDIA’s AI revenue includes its AI processors as well as memory included on the circuit board. SK Hynix has been NVIDIAs primary supplier of high bandwidth memory (HDM) used for AI. Micron Technology and Samsung are also HDM suppliers. The memory cost for NVIDIA will amount to several billion dollars in 2024.

AMD, the next largest supplier, projects $4.5 billion in AI IC revenue in 2024. Intel expects $500 million in AI IC revenue in 2024. AIMultiple Research lists eighteen additional companies which have announced AI ICs. These include cloud service providers (AWS, Alphabet, IBM and Alibaba), mobile AI IC providers (Apple, Huawei, MediaTek, Qualcomm and Samsung) and startups (SambaNova Systems, Cerebras Systems, Graphcore, Grog and Mythic).

We at Semiconductor Intelligence estimate the global AI IC market in 2024 at $110 billion. NVIDIA dominates with $96 billion in revenue and 87% market share. AMD is $4.5 billion, and Intel is $0.5 billion. Apple is estimated at $3 billion based on the AI processors in its iPhone 16 models. Samsung’s AI-enabled Galaxy S24 should generate about $1 billion in AI IC revenue for its primary supplier, Qualcomm. Other companies are just getting started in the market and are estimated at a total of $5 billion.

The $110 billion AI IC market in 2024 will account for 18% of the total semiconductor market based on the WSTS June 2024 forecast. Using a relatively conservative projection of a 20% CAGR for AI ICs over the next five years results in a $273 billion market in 2029. We project the long-term growth rate of the semiconductor market at a 7% CAGR, reaching $856 billion in 2029. AI ICs would then account for 31.9% of the total semiconductor market. AI ICs will not be totally additive to the semiconductor market. AI ICs will replace many of the current processors used in data centers, PCs, smartphones and automobiles.

Semiconductor Intelligence is a consulting firm providing market analysis, market insights and company analysis for anyone involved in the semiconductor industry – manufacturers, designers, foundries, suppliers, users or investors. Please contact me if you would like further information.

Bill Jewell
Semiconductor Intelligence, LLC
billjewell@sc-iq.com

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The RISC-V and Open-Source Functional Verification Challenge

The RISC-V and Open-Source Functional Verification Challenge
by Daniel Nenni on 10-24-2024 at 10:00 am

Semiwiki Blog Post #1 Image #1

Most of the RISC-V action at the end of June was at the RISC-V Summit Europe, but not all. In fact, a group of well-informed and opinionated experts took over the Pavilion stage at the Design Automation Conference to discuss functional verification challenges for RISC-V and open-source IP.

Technology Journalist Ron Wilson and Contributing Editor to the Ojo-Yoshida Report moderated the panel with Jean-Marie Brunet, Vice President and General Manager of Hardware-Assisted Verification at Siemens; Ty Garibay, President of Condor Computing; Darren Jones, Distinguished Engineer and Solution Architect with Andes Technology; and Josh Scheid, Head of Design Verification at Ventana Microsystems.

Their discussion is broken into a three-part blog post series starting with selecting a RISC-V IP block from a third-party vendor and investigating its functional verification process.

Wilson: Assuming a designer is going to use a CPU core in an SoC and not modify the RTL or add custom instructions, is there any difference in the functional verification process for licensing a core from Arm or licensing a RISC-V core from an established vendor? What about downloading an open-source core that seems to work? Do they have the same verification flow or are there differences?

Scheid: A designer will use the same selection criteria and have the same integration experience for RISC-V as Arm and other instruction set architectures. The RISC-V software support is the challenge because everything is open source, mostly coming from upstream and open-source areas, not necessarily proprietary tool chains from the vendors.

Ventana uses standard open specification protocols on how to integrate with other products. Verification IP support is available from multiple vendors to make this experience similar to others.

Garibay: The big difference is using a core from true open source. The expectation for that core would be different. In general, a designer paying for IP can assume some amount of energy and effort put into the verification of the CPU core itself that enables a less painful delivery of the IP and integrated at the SoC level.

I would have a different expectation between any true open-source IP versus something licensed from an established design house. An ISA is an ISA. What matters is the design team and the company that stands behind it more than the ISA itself relative to the user experience.

Jones: I agree. It’s less about RISC-V versus Arm and more about the quality of the licensed IP. In fact, I would remind anyone who’s building an SoC that includes some number of IP, CPU, PCIe, USB: they are paying for verification. A designer can go out and find free RTL for almost anything by looking on Google.

Basing a company’s product (and potentially the company’s future) on a key IP block, it must be from a company that can stand behind it. That’s the verification as well as support.

Acquiring IP can be separated into three options –– Arm versus RISC-V versus something found on Google. Something found on Google is risky. Between Arm and the various RISC-V vendors, it’s more about the company’s reputation and good design flow. It’s less about RISC-V versus Arm.

Wilson: It’s almost a matter of buying a partner who’s been through this versus you’re on your own?

Garibay: Absolutely. You certainly want to have a vendor that has a partnership attitude.

Brunet: Yes. It’s all about verification. As a provider of hardware-assisted verification, RISC-V is a dream come true. Arm has a large compute subsystem providing a complex environment fully verified that is broad and sophisticated in the compute environment and paid for by users. RISC-V-based designers are going to have to verify much more of the interaction between the netlist, the hardware and the software stack.

Software stack verification is the big challenge as well as scaling the RTL of the device. That’s common for designers as soon as they do big checks. Verification is the biggest bottleneck and the size of the RISC-V software stack and software ecosystem is still not at the same level as Arm. Therefore, it’s putting even more pressure on the ability to verify not only the processor, the capacity of the processing unit, but integrating with the IP that is PCIe, CXL and so on. That’s a far greater verification challenge.

Wilson: RISC-V has respected vendors and so many extensions that sometimes are not so subtly different. Does that complicate the verification problem, or does it simplify it by narrowing the scope?

Scheid: The number of extensions is the wrong thing to focus on. Arm uses the term features and many dozens of those within its Arm versions. The number of ratified extensions was around 50 something. It gets scary if there’s a big list. Going forward, designers are going to focus more on what RISC-V is working on in terms of profiles. We’re talking about advanced processors at one level, microcontrollers at another and then a time-ordered series of improvements in terms of what extensions are supported in that profile. That’s going to be easier to focus on in terms of selecting IP, the support for that profile and still allow optionality between the different implementations. It won’t be as confusing as a list of extensions.

Wilson: Do you see open-source verification IP converging around those?

Scheid: The value of having fewer combinations supported is going to circle around itself. Everyone involved from the implementers to the verification IP providers to the software system aren’t going to look at that combinatorial explosion favorably. Some who have tight constraints will want to choose arbitrary combinations. The vast majority are going to focus around working with the rest of the ecosystem to focus on those profiles and focus on that.

Garibay: The specification of the profiles is a big leap forward for the RISC-V community to allow for the establishment of software compatibility baselines such that there is at least the promise of vendor interoperability for full stack software. Designers should have a baseline and then accept it as customization or as optional sub-architectures.

The fun part about RISC-V right now is not the number of different features being added to the specification. It is the pace. Over the last two years and probably going forward for the next year, RISC-V has been on a rapid pace adding features that are needed. Features that are the right set of features to expand the viability of the architecture of high-performance computing. We need them and it has dramatically inflated the design space and the verification space. Really, we’re just getting to the same point where Arm and x86 are now and probably have been for years. It’s just a dramatic rate of change for RISC-V coming from a much simpler base.

Jones: I’m not sure it’s the right question. If I’m the SoC designer and have an option, I can take a 32-bit floating point or a 64-bit floating point. If I go with RISC-V and it’s 64-bit, it must have 32-bit. By having extensions, RISC-V benefits from the history of x86, MIPS, SPARC and Arm.

What I mean to say is, if I’m the SoC designer, I don’t have to verify the CPU. My CPU vendor has to verify it. That’s fair and I will choose a high-quality vendor. When I talk about verification on my SoC design, I’m talking about connecting the bus properly, assigning address spaces correctly and routing properly throughout my SoC design. The SoC designer has to verify that the software running on the CPU is correct. There again, I benefit from the standard that is RISC-V.

When I started out, MIPS had a problem because each MIPS vendor had a different multiply accumulate instruction (MAC) because MIPS didn’t have a MAC. Software vendors were charging each MIPS vendor $100,000 to port their compiler to it. The first vendor got his money’s worth. Everybody else got that same compiler for $100,000. MIPS figured this out, standardized, and everyone was happy. RISC-V avoids those kinds of problems.

Wilson: Do you see extensions as an advantage?

Jones: Yes, because RISC-V can be implemented as a small microcontroller that doesn’t have all the other features that a small core does not require. Arm does this too, though it doesn’t call it an extension. An Arm core is available without a floating-point unit. I would go so far as to say that the number of pages in the Arm ISA and the number of pages in the various extensions of the RISC-ISA are probably similar. RISC-V’s may be shorter.

Garibay: Aggressively standardizing is getting ahead of the problem that we saw in the past with different architectures where designers tried to implement the same function five different ways and come back with a standard. Four designers are going to be upset. It’s great to see the RISC-V organization leading in this way and paving the road. The challenge is to make sure we fill all the holes.

Brunet: I don’t see software stack interoperability happening for RISC-V. It’s a complex challenge and probably the main reason why it is not taking off. A few companies that have a complete chip entirely RISC-V are using it. Most are large, complete subsystems or compute subsystems that are mainly Arm and some cores with well-defined functionality that is RISC-V. Few are completely RISC-V. Is it architecturally the main reason or is it because of the software stack?

Jones: I’ve done a totally RISC-V chip myself. I also know a number of AI chips are completely RISC-V. The difference for these successes is that, in general, those software stacks are not intended to be exposed to the end user. They’re almost 100% proprietary. Given that, a designer can manage the novelty of the RISC-V software stack. Exporting that as an ecosystem to users is the challenge that RISC-V has and what the profiles are intended to enable going forward. We’re at the beginning.

End of Part I

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Sarcina Democratizes 2.5D Package Design with Bump Pitch Transformers

Sarcina Democratizes 2.5D Package Design with Bump Pitch Transformers
by Mike Gianfagna on 10-24-2024 at 6:00 am

Sarcina Democratizes 2.5D Package Design with Bump Pitch Transformers

2.5D package design is rapidly finding its stride in a wide variety of applications, including AI. While there are still many challenges to its widespread adoption, the chiplet approach is becoming more popular compared to monolithic design. However, the required market to create a chiplet ecosystem is still under development. As package design complexity continues to rise, system partitioning, verification, and power management remain critical and challenging to fulfill. Additionally, package design presents secondary problems, including thermal and mechanical stress constraints, which, combined with the sheer cost of the package, make the design of advanced packages very challenging.

Advanced packaging is the domain of Sarcina Technology. Recent announcements from the company have illustrated how these challenges can be overcome. Let’s see how Sarcina democratizes 2.5D package design with something called Bump Pitch Transformers.

What is a Bump Pitch Transformer?

If you are a sci-fi movie buff, the term “transformer” might bring to mind something interesting, but it’s not relevant to the innovation discussed here for 2.5D package design. What Sarcina is addressing is the cost and complexity of the package for 2.5D designs.

Current advanced 2.5D packaging uses a substrate to transpose a chip’s microbump pitch from 40-50 micrometers to the package’s 130 micrometer bump pitch. This is typically done with a silicon TSV (through-silicon via) interposer. While this approach is effective, these substrates are very expensive, in short supply, and complex to design, resulting in lead-time and cost challenges for many advanced designs.

Sarcina’s Bump Pitch Transformer (BPT) approach uses silicon bridge technology, replacing silicon TSV interposers with more cost-effective re-distribution layers (RDL). This architecture is ideal for homogeneous and heterogeneous chiplet integration, targeting high-performance computing (HPC) devices for AI, data center, microprocessor, and networking applications.

By delivering lower costs and faster design times, Sarcina aims to democratize 2.5D package design, making it more readily available to companies to solve a wider range of problems.

Details and Applications

Sarcina’s BPT is effectively a wafer fan-out RDL technology which, thanks to its maturity, delivers lower costs and shorter lead times. This will help system designers optimize AI for new, lower-cost applications, effectively expanding the market. The company is currently engaging customers with two Bump Pitch Transformer options.

The first option (Option 1 above) creates a silicon bridge in high-density applications to connect the I/Os of adjacent dice. Tall copper pillars with a pitch of about 130 micrometers are grown underneath the RDLs. Because the majority of the I/O interconnections are between adjacent dice and have been connected by the silicon bridge, fewer I/Os need to be routed to the next level of interconnect with 130 micrometer bump pitch, which is achieved with tall copper-pillar bumping onto a standard substrate for flip-chip assembly.

The RDLs will merge power and ground micro-bumps with 40-50 micrometer bump pitch, reducing the number of power and ground bumps with tall copper pillars suitable for 130 micrometer bump pitch density. These bumps may also be assembled onto a standard organic or laminate substrate for flip-chip assembly.

The second option (Option 2 above) is a “chip last” service that handles die-to-die interconnects with less interconnection routing density. As the routing density reduces, the die-to-die interconnects no longer require a silicon bridge to pack so many traces onto a small area. This allows the removal of the silicon bridge, using only the RDL traces as the die-to-die interconnects between adjacent silicon dice. With the removal of the silicon bridge from the bump pitch transformer, the interposer cost in this option is lowered compared to the first option.

Sarcina’s BPT service offering includes BPT interposer design, O/S test pattern insertion, fabrication, BPT wafer sort, package substrate design, power/signal integrity, thermal system simulation, and substrate fabrication. A complete WIPO (wafer in, package out) engagement also covers wafer sort, package assembly, final test, qualification, and production services.

To Learn More

You can see the Bump Pitch Transformer announcements from Sarcina here and here. You can also learn more about this unique company on SemiWiki here. And you can get a broad view of Sarcina’s advanced packaging design services here. In a past life, I was involved in several advanced 2.5D package designs. I can tell you it’s nowhere near as easy as it may look. You really need a partner like Sarcina to tip the odds in your favor. I highly recommend you take a look.

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Addressing Reliability and Safety of Power Modules for Electric Vehicles

Addressing Reliability and Safety of Power Modules for Electric Vehicles
by Kalar Rajendiran on 10-23-2024 at 10:00 am

Cadence Power Module Design Process

As electric vehicles (EVs) gain widespread adoption, safety, reliability, and efficiency are becoming increasingly important. A crucial component in ensuring these aspects is the power module (PM), which manages the energy flow between the EV battery and the motor. The design of these power modules must not only meet the high-performance demands of modern EVs but also address key challenges such as thermal management, electromagnetic interference, and long-term reliability. To tackle these challenges effectively, an integrated design approach is necessary.

Cadence recently published a whitepaper that addresses this topic and presents an integrated design methodology.

Power Module Design Challenges

As mechanical power demands and fast-charging capabilities increase, power modules must handle higher energy loads, increasing the risk of failures. Poor thermal management, electromigration, warpage, and electromagnetic interference (EMI) are just a few of the challenges that can compromise power module reliability. Additionally, as electric vehicles operate at varying voltages and temperatures, designing compact and efficient power modules that can withstand these conditions is essential to ensure the vehicle’s longevity and safety.

Traditional design processes often fall short because they rely on real-world testing at later stages of development. When issues are discovered at this stage, the cost of fixing them through redesigns can be significant. The new methodology for power module design focuses on early-stage simulations and analyses to avoid these late-cycle issues.

Circuit Analysis and Schematic-Driven Package Design

A reliable power module design starts with circuit analysis, using tools like Cadence PSpice to simulate both digital and analog components. Digital simulations focus on factors like jitter, while analog simulations analyze gain, input impedance, and other performance metrics. By simulating current, voltage, power dissipation, and operating temperatures, designers can ensure reliable thermal performance and preemptively address potential failure points.

These simulations also inform other key analyses, such as warpage and life expectancy estimations through failure modes effects and diagnostic analysis (FMEDA). Ensuring that the schematic-driven package design is correct from the start, through layout versus schematic (LVS) checks, helps streamline the placement of components and connections within the power module. This early-stage precision eliminates potential errors and ensures the reliability of the final design.

Parasitic Extraction and Temperature-Aware Simulation

One of the hidden challenges in power module design is stray inductances, which can cause unwanted electromagnetic radiation and disrupt nearby electronic systems. To address this, the design methodology includes parasitic extraction of bondwires using 3D-quasistatic electromagnetic (EM) simulations. These simulations help identify and mitigate potential risks from electromagnetic interference (EMI), which could otherwise affect the vehicle’s electronic control unit (ECU) and compromise occupant safety.

Parasitic elements are highly temperature-dependent, and their effects on performance can vary significantly with operating temperature and frequency. The methodology incorporates temperature-aware parasitic extraction to account for these variations and ensure accurate calculations for power and temperature. This approach enables the design team to refine the schematic by adjusting discrete components and compensating for parasitic effects, ensuring functional reliability and reducing time-to-market delays.

Thermal Simulation and Electromigration

Effective thermal management is critical for the long-term reliability of power modules in EVs, as these modules can reach temperatures of 130°C or more. Traditional thermal analysis tools often overestimate power levels, leading to over-designed, costlier packages. By tightly coupling electrical and thermal environments in the design phase, the proposed methodology enables a more accurate thermal simulation based on actual operating conditions. This ensures that power modules are designed to handle peak power without being unnecessarily over-engineered, reducing both cost and weight.

High current densities in power modules can lead to electromigration, where metal atoms in interconnects are displaced due to high currents. This can cause functional failures over time. By analyzing current densities in the design phase, the methodology helps designers mitigate these risks and prolong the lifespan of the power module, ensuring long-term vehicle safety.

Mechanical Strain and Warpage Analysis

Mechanical stress can also lead to power module failure, especially when there are large differences in the coefficient of thermal expansion (CTE) between different materials used in the module. This can cause warpage or bending, which leads to component failure. Warpage analysis identifies potential deformation risks and allows designers to implement corrective measures, such as strategic placement of redundant components. This significantly improves the reliability and safety of power modules.

Proposed Integrated Design Methodology

Cadence’s proposed design flow for power modules in EVs focuses on co-optimizing both the die and the package to ensure efficient thermal performance at the design frequency and operating temperature. This integrated approach allows for greater safety and reliability in high-power systems, including EVs, by addressing potential risks early in the design process. By incorporating a “shift left” methodology, which emphasizes identifying and solving problems in the early stages of design, this process minimizes the risk of costly respins and unforeseen failures later in the product cycle.

The comprehensive design flow (refer to Figure below), which integrates advanced simulation, parasitic-aware analysis, and thermal management tools, offers a one-stop Cadence solution for power module development. This streamlined process not only accelerates time-to-market but also ensures that EV power modules meet stringent safety and performance requirements.

For more details including the complete analysis of a Press-Fit Full Bridge MOSFET Power Module, access the entire whitepaper here.

Summary

An integrated approach to power module design for electric vehicles not only enhances efficiency but also ensures the safety and reliability of these critical components. By addressing key concerns such as electromigration, parasitic effects, thermal management, and mechanical strain early in the design process, manufacturers can prevent late-stage failures and costly respins. The proposed “shift left” design methodology minimizes risks and reduces development costs, ensuring that power modules deliver reliable performance throughout their operating life. By implementing this methodology, manufacturers can develop power modules that contribute to safer, more efficient, and more reliable electric vehicles for the future.

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Shaping Tomorrow’s Semiconductor Technology IEDM 2024

Shaping Tomorrow’s Semiconductor Technology IEDM 2024
by Scotten Jones on 10-23-2024 at 6:00 am

IEDM 2024 SFO

Anyone who has read my articles about IEDM in the past know I consider it a premiere conference covering developments of leading-edge semiconductor process technology. The 2024 conference will take place in San Francisco from December 7th through 11th.

Some highlight of this year’s technical program are:

AI  – Lots of artificial intelligence-related semiconductor research will be presented this year. For example, since AI computing is more memory-centric than other methods, there will be an entire special Focus Session (session #3) devoted to memory technologies for AI.  Also, both of the Short Courses on Sunday, Dec. 8 will deal with AI; see the news release below for more details.  Two of the keynote talks will do the same; again, more details are below.  China’s Tsinghua University will describe a dense, fast and energy-efficient 3D chip for computing-in-memory in paper #5.3, and there are many other AI-related talks throughout the program, too.

TSMC’s new industry-leading 2nm Logic Platform – TSMC will provide details of its new manufacturing process (paper #2.1), which the researchers say has already passed initial qualification tests.

Intel  – paper #2.2 describes extremely scaled transistors, and Intel paper #24.3 shows record performance for transistors with channels that are just one atom thick.

A look back at 70 years of IEDM history – Since the conference began in 1955, IEDM has been where the world’s experts go to report groundbreaking advances in transistors and other devices that operate based on the movements or other qualities of electrons. To celebrate the conference’s 70th anniversary, there will be a special Focus Session (#28) highlighting historic advances which we now take for granted in logic, memory, interconnects, imaging and other areas.

Advanced packaging is another way forward – Packaging has become critically important to the semiconductor industry, because the benefits to be gained from advanced packaging are rivaling those which can be obtained by the traditional approach of integrating more functions onto a single chip, following Moore’s Law. You put together different types of chips, made from different technologies, in various vertical or horizontal configurations, and interconnect them in fast, dense and energy-efficient ways, and voila, you can create appealing solutions for AI and other fast-growing applications.  Of course, it’s not so simple, and another special Focus Session (#21) will delve into cutting-edge advances and future requirements in chip and package design for high-performance computing and advanced AI applications.

Power transistors for a more electrified, sustainable society – Another special Focus Session (#33) will highlight advances and future trends in power semiconductor technologies, which are crucial for sustainable electronics-based energy solutions.

Brain/electronics interfaces – Special Focus Session #14 will cover advanced neural interface technologies and their potential to revolutionize human/electronic interactions for both medical and technological applications.

To register or read more about the conference please go HERE.

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SI and PI Update from Cadence on Sigrity X

SI and PI Update from Cadence on Sigrity X
by Daniel Payne on 10-22-2024 at 10:00 am

Sigrity X

Signal Integrity (SI) and Power Integrity (PI) issues are critical to analyze, ensuring the proper operation of PCB systems and IC packages, yet the computational demands from EDA tools can cause engineers to only analyze what they deem are critical signals, instead of the entire system. Cadence has managed to overcome this SI/PI analysis limitation by using distributed simulation, where all of the cores in a machine are used, along with distributing the workload to multiple machines. Sigrity X is the platform from Cadence that uses distributed simulation for SI/PI for PCB and IC package designs.

Sigrity entails multiple EDA tools, each aimed at a specific task.

  • IBIS Modeling – AMI Builder
  • Transistor to Behavioral model conversion – T2B
  • Interconnect extraction – XcitePI
  • EM field solver – PowerSI, XtractIM
  • Serial/Parallel link analysis – SystemSI
  • Finite Difference Time-Domain Analysis – SPEEDEM
  • Power Integrity – OptimizePI, Sigrity PowerDC

Sigrity Tools

The database used in Sigrity X has migrated into a single .spd file, instead of being spread out over multiple files, simplifying your workflow.

Sigrity uses a single .spd file

Runtime improvements with Sigrity X are about 10X faster, all with the same accuracy level. For the PowerSI comparison a package plus PCB simulation improved by 12X. With XtractIM run on an InFO package showed a 15.1X speedup. On a FC-BGA package simulation the improvement was 7.18X. OptimizePI simulation was 8.56X faster using Sigrity X.

Sigrity X speedups

Run times depend on how many cores are used, so here’s a table showing the scalability comparisons. Users decide how many machines and cores to use for each run.

PCB designers using Allegro canvas can run Sigrity analysis for topological extractions, crosstalk and reflections, IR drop, impedance, coupling and return path simulations. For system-level simulations here’s an example flow using Sigrity and Clarity tools.

Sigrity and Clarity tool flow

DDR5 simulations and data-dependent measurements are done with Sigrity X by using accurate interconnect models, plus accurate modeling of transceiver equalization.

DDR5 analysis with Sigrity

Analyzing a board and package power delivery network (PDN) is accomplished using Sigrity, Clarity 3D Solver and Voltus IC Power integrity in a flow.

Power domain analysis

Case Studies

Setting up a Sigrity Simulation starts with dragging and dropping a .brd file into the window, then selecting which nets should be simulated. Ports are generated based on the selected nets, then compute resources are selected.

DDR simulation results

Continuing the DDR example a testbench is created, a circuit simulator selected, then time domain results viewed. A channel report is run and the results are compared versus expected, based on the standard, so this mask is passing at 4.4Gbps.

Eye mask plot

A power domain analysis was run on a system consisting of building blocks, subcircuits, S-parameter blocks, ideal elements, layout element, VRMs, Voltus blocks, plus an IC block. The IC block has a PWL source for the current. Target impedance is then simulated. Impedance from all eight nodes (IC2:IC9) is examined and compared to the target impedances.

Power domain analysis flow

Some of the eight impedances are peaking out above 100MHz, so the designers can reduce these impedances to meet the power ripple specification.

Eight port impedances

A final simulation is run after impedance changes, then the eight nodes are examined and the ripples are overlapping each other. Both impedance and power ripple results have been analyzed properly at the system-level.

Eight nodes simulated

Summary

SI/PI analysis is improved by the abilities in Sigrity X and the Clarity 3D Solver, using distributed simulation. Your PCB and IC package design teams will have increased confidence that each new project will meet requirements through SI/PI analysis.

Read the complete 18-page White Paper on Sigrity X.

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Advanced Audio Tightens Integration to Implementation

Advanced Audio Tightens Integration to Implementation
by Bernard Murphy on 10-22-2024 at 6:00 am

girl wearing wireless earbuds on noisy street min

You might think that in the sensing world all the action is in imaging and audio is a backwater. While imaging features continue to evolve, audio innovations may be accelerating even faster to serve multiple emerging demands: active noise cancellation, projecting a sound stage from multiple speakers, 3D audio and ambisonics, voice activated control, breakthrough to hear priority inputs, and in-cabin audio communication to keep driver attention on the road. Audio is especially attractive to product builders, providing more room for big quality and feature advances with premium pricing ($2k for premium headphones as an example). Such capabilities are already feasible but depend on advanced audio algorithms which must run on an embedded DSP. Today that option can add considerable complexity and cost to product development.

What makes advanced audio difficult?

Most audio algorithm developers work in MATLAB/ Simulink to design their algorithms. They build and profile these algorithms around predefined function blocks and new blocks they might define. When done, MATLAB/ Simulink outputs C-code which can run on a PC or a DSP though it will massively underexploit the capabilities of modern DSPs and will fail to meet performance and quality expectations for advanced audio.

A team of DSP programming experts is needed to get past this hurdle, to optimize the original algorithm to take full advantage of those unique strengths. For example, vectorized processing will pump through streaming audio much faster than scalar processing but effective vectorization demands expert insight into when and where it can be applied. Naturally this DSP software team will need to work with the MATLAB/ Simulink algorithm developer to make sure intent is carried through faithfully into DSP code implementation. Equally they must also work together to validate that the DSP audio streams match the audio streams from the original algorithm with sufficient fidelity.

MathWorks supports rich libraries to build sophisticated audio algorithms, making it the design platform of choice for serious audio product builders. Yet this automation gap between design and implementation remains a serious drawback, both in staffing requirements and in competitive time to market.

Streamlining the link from design to implementation

Cadence and MathWorks (the company behind MATLAB and Simulink) have partnered over several years to accelerate and simplify the path from algorithm development to implementation and validation, without requiring a designer to leave the familiar MathWorks environment. This they accomplish through a toolbox Cadence call the Hardware Support Package (HSP), which together with MATLAB and Simulink provides an integrated flow to drive optimized implementation prototyping, verification, and performance profiling, all from within the MathWorks framework.

Through this facility, HSP will map MATLAB/ Simulink function blocks and code replacement candidates to highly optimized DSP equivalents (this mapping could be one-to-one, one-to-many, or many-to-one). Additionally, it will map functions supported in the HSP Nature DSP library (trig, log, exponentiation, vector min/max/stddev). These mapping steps can largely eliminate need for DSP software experts, except perhaps for specialized functions developed during algorithm development. Equivalents for these, where required, can be built by a DSP expert and added to the mapping library.

Integration can also handle dynamic mode switching. If you want to support multiple audio processing chains in one platform – voice command pickup, play a songlist, or phone communication, each with their own codecs – you must manage switching between these chains as needed. The XAF Audio Framework will handle that switching. This capability can also be managed from within the MATLAB/ Simulink framework.

Once a prototype has been mapped it can be compiled and validated through a processor-in-loop (PIL) engine based on the HiFi DSP instruction set simulator. All these steps can be launched from within the MathWorks framework. An algorithm developer can then feed this output together with original algorithm output into whatever comparison they consider appropriate to assess the quality of the implementation. Wherever a problem is found, it can be debugged during PIL evaluation, again from within the MathWorks framework with additional support as needed from the familiar gdb debugger.

Finally, the HiFi toolkit also supports performance profiling (provided as a text output), which an algorithm developer can use to guide further optimization.

What about AI?

AI is playing a growing role in audio streams, in voice command recognition and active noise cancellation (ANC) for example. According to Prakash Madhvapathy (Product Marketing and Product Management Director for the Audio and Voice Product Line at Cadence), AI-based improvements in ANC are likely to be the next big driver for consumer demands in earbuds, headphones, in car cabins and elsewhere, making ANC enhancements a must-have for product developers.

HiFi DSPs provide direct support for AI acceleration compatible with audio streaming speeds. The NeuroWeave platform provides all the necessary infrastructure to consume architecture networks, ONNX or TFML, with a goal Prakash tells me to ensure “no code” translation from whatever standard format model you supply to mapping onto the target HiFi DSP. Support for integrating the model is currently outside the HSP integration.

Availability

The Hardware Support Package integration with MathWorks is available today. No-code AI support through NeuroWeave is available for HiFi 1s and HiFi 5s IPs today.

This integration looks like an important time to market accelerator for anyone working in advanced audio development. You can learn more about the HSP/MathWorks integration in this blog from Cadence and from the MathWorks page on the integration.


Unlocking SoC Debugging Challenges: Paving the Way for Efficient Prototyping

Unlocking SoC Debugging Challenges: Paving the Way for Efficient Prototyping
by Daniel Nenni on 10-21-2024 at 10:00 am

3D rendering of cyberpunk AI. Circuit board. Technology background. Central Computer Processors CPU and GPU concept. Motherboard digital chip. Tech science background.

As chip design complexity increases, integration scales expand and time-to-market pressures grow, as a result, design verification has become increasingly challenging. In multi-FPGA environments, the complexity of design debugging and verification further escalates, making it difficult for traditional debugging methods to meet the demands for high performance and efficiency. This makes efficient debugging solutions critical for successful prototype verification. Today, we’ll explore common debugging methods ranging from basic to advanced approaches.

Why is Prototyping Important

With the growing complexity of large-scale integrated circuits, chip verification faces immense time and cost pressures. Historically, designers relied on simulation or silicon tape-out for validation, a process that is both time-consuming and costly. Prototyping allows for testing real-world scenarios before tape-out, ensuring the reliability and stability of functional modules while assessing performance. This not only shortens time-to-market but also enables early demonstrations to customers enabling pre-sales activities.  Additionally, prototyping significantly reduces costs by enabling driver development ahead of silicon availability. Once silicon is ready, applications can be seamlessly integrated with drivers developed during prototyping which accelerates SoC deployment.

Prototyping offers a unique speed advantage, outperforming software simulation and hardware emulation in verification turn around times, though historically it has lacked robust debugging capabilities. While software simulation is user-friendly but  it is slower and more suitable for small-scale or module-level verification. Hardware emulation is better suited for larger designs with strong debugging capabilities while prototyping stands out for its speed. As complexity increases, users increasingly rely on debugging tools provided by FPGA vendors which can be limited in scope. Here we’ll discuss how to overcome these debugging challenges and introduce S2C’s advanced debugging solutions.

S2C’s Prodigy prototyping solution offers a comprehensive and flexible debugging platform equipped with a complete toolchain that includes real-time control software (Player Pro-RunTime), design debugging software (Player Pro-DebugTime), the Multi-Debug Module (MDM) for deep debugging, and ProtoBridge co-simulation software. These tools significantly enhance user efficiency, catering to the diverse requirements of S2C’s broad customer base with capabilities that may not be available from other vendors.

What Are the Common Debugging Techniques

With prototype verification, debugging aims to pinpoint and resolve design issues, ensuring system functionality. In complex SoC designs, engineers must ensure that issues are debuggable, minimizing time spent troubleshooting during development. When users first deploy their designs on an FPGA, they often encounter various failures which could stem from network issues within the FPGA prototype, design errors, or compilation problems like timing errors due to design partitioning or pin multiplexing. Effective debugging and monitoring tools are essential for confirming hardware functionality and verifying that all modules operate as expected. This often requires using external or embedded logic analyzers to identify the root cause of issues.

Common debugging methods include basic I/O debugging, AXI bus transaction monitoring, signal-level debugging, and protocol-based debugging. While many users rely on embedded logic analyzers from FPGA vendors during prototype bring-up, these tools may become resource-intensive and harder to manage when dealing with complex multi-FPGA designs.

S2C offers a comprehensive set of debugging solutions, ranging from simple to advanced, meeting the diverse needs of engineers during prototype verification and ensuring a smoother debugging process.

-Basic I/O Debugging:

While FPGA vendors provide various signal monitoring tools such as VIO IP cores, signal editors, and probes typically accessed through JTAG, S2C’s solution extends I/O debugging capabilities. It integrates multiple basic I/O interfaces—such as push buttons, DIP switches, GPIOs, and UARTs—directly into the prototype, offering intuitive user interactions. Additionally, S2C’s Player Pro software enhances remote diagnostic capabilities through virtual interfaces, making the debugging process more efficient.

-Bus Transaction Debugging:

For complex SoC designs, debugging AXI bus transactions is highly effective, especially when AXI has become a standard protocol. S2C’s ProtoBridge solution uses PCIe to offer up to 4GB/s of high-bandwidth AXI transaction bridging. It includes an AXI-bridged RTL interface for seamless design integration, along with PCIe drivers and APIs to support software-based stimulus development. With built-in Ethernet debugging (~10Mbps), ProtoBridge enables rapid read/write access to memory-mapped AXI slaves, meeting low-bandwidth debugging needs.

– Signal-Level Debugging:

Signal-level debugging is one of the most commonly used methods in prototype verification, involving the extraction of internal signals for issue diagnosis. S2C’s Player Pro excels in this area which allows designers to easily map internal signals to I/O. A range of expansion cards offers additional flexibility, including pin connections, 3.3V voltage conversion, and extra interfaces for push buttons, switches, and external logic analyzers, making real-time testing more efficient.

-In-System Protocol Debugging:

When FPGA prototypes interact with real-world data, protocol-based debugging becomes essential. S2C supports over 90 expansion cards and reference designs to facilitate system-level testing across various protocols. Custom solutions are also available to optimize testing and debugging for a smooth prototyping experience.

-Deep Logic Analysis:

For users requiring in-depth debugging or dealing with multi-FPGA setups, challenges often include memory capacity for signal storage and the need for cross-FPGA debugging. S2C addresses these issues with the MDM Pro which supports concurrent signal probing across up to 8 FPGAs and includes cross-trigger functionality. Equipped with 64GB of DDR4 memory, MDM Pro captures up to 16K signals in 8 groups without the need for FPGA recompilation. Pre-built into S2C’s Quad 10M and Quad 19P Logic Systems, MDM Pro offers intuitive trigger settings similar to those in FPGA vendor tools ensuring a smooth transition for engineers. It supports both IP and compile modes which provides flexibility to match various design flows.

Conclusion:

Prototyping offers significant performance advantages over software and hardware emulation. This has driven a demand for advanced debugging solutions to maximize the benefits of prototyping. As one of the earliest providers of prototyping tools, S2C enhances productivity and efficiency with a comprehensive range of debugging methods. These solutions are particularly effective in addressing the challenges of multi-FPGA environments helping engineers accelerate verification and shorten time-to-market.

For more information: https://www.s2cinc.com/

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Evolution of Prototyping in EDA

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Accelerate SoC Design: Addressing Modern Prototyping Challenges with S2C’s Comprehensive Solutions (II)