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Think Quantum Computing is Hype? Mastercard Begs to Disagree

Think Quantum Computing is Hype? Mastercard Begs to Disagree
by Bernard Murphy on 11-10-2025 at 6:00 am
Categories: PQShield, Quantum Computing, Security
2 Comments

Just got an opportunity to write a blog on PQShield, and I’m delighted for several reasons. Happy to work with a company based in Oxford and happy to work on a quantum computing-related topic, which you’ll find I will be getting into more deeply over coming months. (Need a little relief from a constant stream of AI topics.) Also important, I enjoy connecting technology to real world needs, things everyday people care about. Mastercard has something to say here.

Security is visceral when it comes to our money

I find in talking about and writing about security in tech that, while we all understand the importance of security, our understanding is primarily intellectual. Yes, security is important, but we don’t know how to monetize it. We do what we can, but we don’t need to get ahead of the game if end-user concern remains relatively low. As an end-user I share that view – until I’m hacked. As happened to my credit card a few weeks ago – I saw a charge at a Panda Express in San Francisco – a 3-hour drive from where I live. The card company removed the charge and sent me new card. Happily it’s been years since I was last hacked. But what if hacks could happen every year, or month, or week?

In their paper Mastercard talk about malicious actors using a “Harvest Now, Decrypt Later” attack paradigm. Building a giant pool of encrypted communications and keeping it in storage until strong enough decryption mechanisms become available. We’re not aware that data we care about is in the hands of bad actors because nothing bad has happened – yet. This is not a theoretical idea. The possibility already exists for systems using DES, RSA-1024 or weaker mechanisms, which is why most though maybe not all weak systems have been upgraded.

The stronger threat comes from quantum computing (QC). You might think that QCs are just toys. Small qubit counts can’t handle real jobs. Your view may be outdated. IBM already have a one-thousand usable qubit computer, Google is planning for a one-million qubit system and who knows what governments around the world can now reach, especially in hacking hotbeds.

OK you counter, but these are very specialized systems. Governments don’t want to hack my credit cards (though I’m not sure I’d trust that assertion). But it doesn’t matter. To build demand, QC centers provide free or moderate-cost access to their systems. All you have to do is download an algorithm, maybe from the dark Web, to factor large integers. Then you can break RSA-encrypted messages using Shor’s or similar algorithms.

In fairness, recent estimates suggest that RSA-2048 may not be broken before 2031. But improvements in quantum error correction are already pushing down that limit. We really can’t be certain when that barrier will be breached. Once it is, the flood gates will open thanks to all that harvested encrypted data. That breach will affect not only credit cards but all electronic payment systems and more generally finance systems. Our intellectual concern will very rapidly become a visceral concern if we are not prepared.

PQShield and quantum-resistant encryption

Mastercard mentions two major mechanisms to defend against quantum attacks: post-quantum cryptography (PQC) and quantum key distribution (QKD). QKD offers theoretically strong guarantees but is viewed currently as a future solution, not yet ready for mass deployment. The Mastercard paper reinforces this position, citing views from multiple defense agencies and the NSA. More immediate defenses are based on QKC, for which PQShield offers solutions today.

Several algorithms have been proposed which NIST is supporting with draft standards. Importantly, National Security System owners, operators and vendors will be required to replace legacy security mechanisms with CNSA 2.0 for encryption in classified and mission-critical networks. CNSA 2.0 defines suite of standards for encryption, hashing and other objectives.

The NIST transition plan projects urgency. New software, firmware and public-facing systems should be upgraded in 2025. Starting 2027 all new NSS acquisitions must be CNSA 2.0 compliant by default. By 2030 all deployed software and firmware must use CNSA 2.0 signatures and any networking equipment that cannot be upgraded with PQC must be phased out. The Mastercard paper talks about plans in other regions which seem not quite as far ahead, though I expect EU enthusiasm for tech regulation will quickly address that shortfall.

PQShield is already well established in PQC. This is a field where customer deals are unlikely to be announced, but other indicators are promising. Their PQCCryptoLib-Core is in “Implementation Under Test” testing at NIST. They are in the EU-funded Fortress project. They have partnered with Carahsoft Technologies to make quantum-safe technology available to US public sector companies. And they have published multiple research papers, so you can dig into their technology claims in detail.

Fascinating company. You can learn more HERE.

Also Read:

Podcast EP304: PQC Standards One Year On: The Semiconductor Industry’s Next Move

Formal Verification: Why It Matters for Post-Quantum Cryptography

Podcast EP290: Navigating the Shift to Quantum Safe Security with PQShield’s Graeme Hickey

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CEO Interview with Roy Barnes of TPC

CEO Interview with Roy Barnes of TPC
by Daniel Nenni on 11-08-2025 at 10:00 am
Categories: CEO Interviews

Roy Barnes Headshot

Roy Barnes is the group president of The Partner Companies (TPC), a specialty manufacturer, overseeing TPC’s photochemical etching companies: Elcon, E-Fab, Fotofab, Microphoto and PEI.

Roy is an experienced leader known for building strong teams, driving change and inspiring people to succeed. Throughout his career, he has cultivated a leadership style grounded in open communication and collaboration—ensuring teams understand one another’s strengths and work together to achieve lasting results. Roy’s focus on connection and development has consistently helped TPC grow stronger and perform at its best.

Tell us about your company?

The Partner Companies began in 2010 with a straightforward idea: bring together specialty manufacturers who excel at solving precision manufacturing problems. Over the past fifteen years, we’ve built an integrated group of eleven companies that share something fundamental — each delivers mission-critical solutions to industries where failure isn’t an option.

What ties these companies together is deep expertise in specialized processes that can complement each other to best serve our partners’ manufacturing needs. The five companies I oversee, Elcon, E-Fab, Fotofab, Microphoto and PEI, have mastered photochemical etching for ultra-precise thin metal parts, ceramic metallization and more.

The semiconductor industry has been core to our business from the beginning. Elcon Precision, which dates back to 1967, was delivering high-precision photochemical etching solutions to semiconductor manufacturers more than forty years ago. E-Fab has been doing the same since 1982. That foundation has allowed us to grow alongside the industry as it’s evolved.

Today, TPC’s 11 specialty manufacturers operate across facilities in the United States, Asia, the United Kingdom, and Mexico. Companies like Elcon, E-Fab, Fotofab, Lattice Materials, Optiforms, and PEI each bring distinct technical capabilities, whether that’s crystal growth for precision optics, high-volume production of complex metal parts, sheet metal fabrication and assembly, or plastic injection molding.

What problems are you solving?

The semiconductor sector is undergoing rapid transformation, fueled by record-breaking sales and breakthroughs in AI, 5G, and autonomous technologies that are redefining how chips power modern life. To adapt to new technological developments, we use photochemical etching — precise manufacturing process that uses light-sensitive coatings and chemical etchants to remove metal and create detailed components – to make design changes and be intimate with the design change process. Once designs are validated, we are able to rapidly scale production volumes.

This type of collaborative problem-solving is representative of how TPC helps customers overcome complex engineering challenges, bringing both process expertise and measurable results.

For example, a leading semiconductor equipment manufacturer recently shared they faced intermittent reliability failures in an aluminum nitride (AlN) heater assembly and turned to Elcon, a TPC company, for support. Elcon conducted a comprehensive failure analysis of the AlN braze stack, including the substrate, metallization, and nickel layers. Cross-sectional and adhesion testing revealed that insufficient metallization adhesion — caused by low surface roughness — was the root issue.

Elcon then conducted a design of experiments (DOE) to define the optimal AlN surface roughness range, confirming a direct correlation between roughness and metallization integrity consistent with published adhesion mechanisms. Based on these findings, Elcon provided quantitative updates to the surface finish specification, resulting in a substantial improvement in adhesion reliability and overall heater performance. While niche, these are the kind of engineering challenges — and solutions — that help enable the next gen equipment to make next gen chips.

What application areas are your strongest?

Our primary focus is partnering with semiconductor equipment manufacturers, with special emphasis on innovative and scalable domestic solutions. By working closely with these companies, we help address challenges related to equipment design and production, enhancing their competitiveness and supply chain security.

What keeps your customers up at night?

Many of our customers face intense supply chain pressures, tariff impacts, rising costs from Asia and intellectual property concerns to ensure our designs avoid being replicated or stolen. TPC’s domestic manufacturing capabilities, engineering support and dedication to secure, IP-focused partnerships help mitigate these risks, offering our customers peace of mind.

What does the competitive landscape look like and how do you differentiate?

TPC stands apart in the rapidly evolving semiconductor industry through our integrated manufacturing approach, offering more than just photochemical capabilities. As demand for faster and reliable chips grows, our ability to leverage adjacent technologies enables us to provide customers with complete designs and vertical integrations. While most of our competitors are small, family-owned businesses, TPC’s frequent investments allow us to expand our engineering and scaling capabilities. Our diverse range of materials used – from copper, stainless steel to titanium and niobium — results in new manufacturing solutions such as titanium etching.

What new features/technology are you working on?

In the heart of Silicon Valley, where we have multiple facilities, we have implemented advanced process control techniques for semiconductor processes including statistical process control (SPC) charts, to bring greater consistency and quality to photochemical etching.

This brings semiconductor-grade precision to a traditionally less-regulated manufacturing environment, improving repeatability and yields for our customers. We also continually invest in new personnel and technologies to further enhance our offerings in specialty manufacturing, photochemical etching and assembly

How do customers normally engage with your company?

We value collaborative partnerships, helping customers develop their designs and solutions with the support of our engineering team. Our customers often come in with a print and our role is to guide them through the manufacturing process. The photochemical etching process in the semiconductor manufacturing is complex and precision-driven especially as U.S. companies work to domestic supply chains. TPC’s experts are here to help customers navigate it with speed, accuracy and reliability.

For more information and to get in touch with TPC, visit https://www.thepartnercos.com/.

Also Read:

CEO Interview with Wilfred Gomes of Mueon Corporation

CEO Interview with Rodrigo Jaramillo of Circuify Semiconductors

CEO Interview with Sanjive Agarwala of EuQlid Inc.

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CEO Interview with Mr. Shoichi Teshiba of Macnica ATD

CEO Interview with Mr. Shoichi Teshiba of Macnica ATD
by Daniel Nenni on 11-08-2025 at 6:00 am
Categories: CEO Interviews

Shoichi Teshiba

With over 30 years of experience in sales and marketing of semiconductors and electronic components, Mr. Shoichi Teshiba has worked across a broad range of industries including storage, servers, networking, consumer electronics, industrial equipment, and automotive. Combining deep insight into both domestic and global markets with strong technical expertise, he has recently focused on facilitating the social implementation of emerging startup technologies. Currently, he plays a key leadership role in global technology scouting, particularly in deep tech, and oversees the management of European subsidiaries. Mr. Shoichi Teshiba has a proven track record of introducing cutting-edge technologies worldwide and driving open innovation initiatives.

Tell us about your company.

Macnica ATD Europe is the European subsidiary of Macnica Inc., one of the world’s largest technology distributors and solution providers. At our core, we are more than a distributor, we are a catalyst for innovation. Our mission is to connect pioneering semiconductor, AI, and imaging technologies with the EMEA market, providing not only cutting-edge products but also deep technical support, integration capabilities, and go-to-market strategies. We work closely with both our global technology partners and EMEA customers to co-create solutions that solve the pressing needs of today and anticipate the challenges of tomorrow.

What problems are you solving?

We help our customers navigate the complexity of emerging technologies. Whether it’s optimizing AI deployment at the edge or accelerating time-to-market for embedded systems, Macnica ATD Europe is here to bridge the gap between innovation and implementation. One of our core strengths lies in making advanced technology accessible, adaptable, and scalable. This means demystifying AI for industrial use cases, streamlining hardware-software integration, and simplifying supply chains through strong vendor partnerships and local support.

What application areas are your strongest?

Our most active and mature application domains are:

  • Edge AI and Computer Vision for Industry 4.0, smart cities, and healthcare
  • Semiconductor Solutions for automotive and industrial applications
  • AI Acceleration and Data Processing in embedded and real-time systems

We offer vertically integrated expertise that combines domain knowledge with component-level mastery – enabling us to serve OEMs, and system integrators with equal effectiveness.

What keeps your customers up at night?

In one word: complexity. Our customers are innovating rapidly, but they face significant technical, regulatory, and operational hurdles:

  • How to scale AI at the edge without compromising performance or cost
  • How to navigate supply chain uncertainty while staying ahead of the technology curve

We address these challenges by acting as a proactive partner, providing not just technology, but also consulting, design support, and local engineering expertise.

What does the competitive landscape look like and how do you differentiate?

While the technology distribution space is crowded, we stand out by offering a hybrid model of distribution and consulting. Our differentiation comes from:

  • Deep technical support and in-house engineering
  • Strong, trusted relationships with best-in-class suppliers
  • A collaborative ecosystem model that integrates customers and partners
  • Local expertise backed by the global strength of the Macnica Group

We don’t just sell components, we co-develop solutions. This high-touch, value-added approach is what makes our customers return project after project.

How do customers normally engage with your company?

Our engagement model is highly collaborative. Customers typically come to us at various stages:

  • Early stage for design consultation or technology scouting
  • Mid-stage for component sourcing and prototyping support
  • Late-stage for deployment optimization, integration, and long-term lifecycle support

They engage through our technical and sales engineers, or through co-innovation initiatives with our partners. We also host webinars, tradeshow, with live demo tradeshows, and live demos to help de-risk complex technology decisions. Whether it’s a multinational or a startup, our goal is to act as an extension of their technical and innovation teams.

 Contact Manica ATD

Also Read:

CEO Interview with Sanjive Agarwala of EuQlid Inc.

CEO Interview with Rodrigo Jaramillo of Circuify Semiconductors

CEO Interview with Wilfred Gomes of Mueon Corporation

Video EP11: Meeting the Challenges of Superconducting Quantum System Design with Mohamed Hassan

Video EP11: Meeting the Challenges of Superconducting Quantum System Design with Mohamed Hassan
by Daniel Nenni on 11-07-2025 at 10:00 am
In this episode of the Semiconductor Insiders video series,  Dan is joined by Mohamed Hassan, who leads the Quantum EDA segment at Keysight. Mohamed provides a broad overview of superconducting quantum system design. He discusses the challenges for this design style and how EDA requirements for quantum design differ from traditional chip design. 
 
Mohamed describes the Keysight offerings to address this design style, along with details of Keysight’s QuantumPro EM Solution. He describes its workflow, along with a description of a real-world application.

The views, thoughts, and opinions expressed in these videos belong solely to the speaker, and not to the speaker’s employer, organization,
committee or any other group or individual.
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TSMC Kumamoto: Pioneering Japan’s Semiconductor Revival

TSMC Kumamoto: Pioneering Japan’s Semiconductor Revival
by Daniel Nenni on 11-07-2025 at 6:00 am
Categories: AI, Automotive, Foundries, TSMC

TSMC Kumamoto Fab 2

In the lush landscapes of Kumamoto Prefecture, on Japan’s Kyushu Island, TSMC is etching a new chapter in global chip production. The TSMC Kumamoto facility, operationalized through its wholly-owned subsidiary Japan Advanced Semiconductor Manufacturing (JASM), represents the Taiwanese giant’s bold foray into Japan, the first dedicated wafer fab outside Taiwan, the U.S., and Europe.

Announced in 2021, this project embodies a strategic pivot toward diversified, resilient manufacturing. With an initial investment exceeding $8.6 billion, Kumamoto underscores TSMC’s commitment to serving key Asian clients while bolstering Japan’s domestic semiconductor ecosystem.

The journey began with groundbreaking in 2022, transforming a sprawling industrial site in Kikuyo Town into a state-of-the-art cleanroom. Construction progressed swiftly, with Taiwanese engineers relocating en masse to oversee integration. By late 2024, JASM’s first fab commenced mass production, focusing on mature yet vital process nodes: 22/28nm and 12/16nm. These nodes are ideal for automotive semiconductors, image sensors, and microcontrollers, sectors where Japanese powerhouses like Sony and Denso dominate.

The facility’s monthly capacity targets 55,000 wafers, powered entirely by renewable energy sources, aligning with Japan’s green manufacturing mandates. As of April 2025, JASM’s workforce has swelled to around 2,400, including 527 new local hires, fostering a blend of Taiwanese expertise and Japanese precision. This infusion has not only created jobs but also sparked a skills renaissance in Kyushu, a region long synonymous with electronics but starved of cutting-edge fabs. This fab was dubbed the “Knight Castle” by locals since construction was done 24 hours a day.

Kumamoto’s strategic imperative is twofold: Geopolitically, it mitigates risks from Taiwan’s exposure to cross-strait tensions, diversifying TSMC’s footprint amid U.S.-China frictions. Economically, it taps into Japan’s resurgence under the “Semiconductor Revival Plan,” backed by subsidies from the Ministry of Economy, Trade and Industry.

This funding is part of a national initiative which aims to reclaim 10% of global chip production by 2030. For TSMC, Kumamoto secures proximity to loyal customers: Sony’s image sensors for smartphones and cameras, Denso’s automotive chips for electric vehicles, and emerging AI peripherals. In an era where automotive semis face slumps, exacerbated by delayed EV adoption, the fab’s specialization offers stability. Industry watchers project profitability by late 2025, with yields already performing robustly.

Yet, expansion hasn’t been seamless. The second fab, earmarked for advanced 6/7nm processes on a 321,000-square-meter plot adjacent to the first, has encountered headwinds. Initially slated for Q1 2025 groundbreaking, construction was deferred to mid-year due to severe traffic congestion from the initial site’s operations (commutes ballooning from 15 minutes to an hour) irking residents. TSMC Chairman C.C. Wei cited these local pains during the June 2025 shareholders’ meeting, emphasizing dialogues with Japanese authorities for infrastructure upgrades. Further delays in 2025 stemmed from softer automotive demand and a pivot toward U.S. investments, pushing mass production to late 2027. TSMC builds fabs closely tied to customer demand so this a good example of intelligent semiconductor business decisions.

Despite these challenges, TSMC reaffirmed its commitment in August 2025 with board member Paul Liu quashing rumors of diminished Japanese focus. The second fab promises elevated capabilities, including 40nm variants for industrial applications, potentially doubling output and attracting more clients.

Beyond wafers, Kumamoto catalyzes regional transformation. Kyushu’s IC production value hit ¥1 trillion in 2024 for the first time in 16 years, fueled by TSMC’s ripple effects. Local suppliers, from equipment makers to materials firms, now furnish 60% of needs, nurturing a self-sustaining cluster. Governor Takashi Kimura has championed community buy-in, securing promises for green spaces and training programs amid wastewater monitoring starting January 2025.

Bottom live: Kumamoto could spawn a third fab post-2030, embedding TSMC deeper in the “semiconductor triangle” of Taiwan, Japan, and the U.S. As AI and EVs propel chip demand, this outpost fortifies supply chains, blending Eastern innovation with Western resilience. In Kumamoto, silicon flows not just as commerce, but as a bridge across borders proving that in the chip wars, collaboration outpaces isolation. For TSMC, it’s a testament to enduring partnerships, for Japan it is a revival etched in silicon, absolutely.

Also Read:

AI-Driven DRC Productivity Optimization: Revolutionizing Semiconductor Design

Exploring TSMC’s OIP Ecosystem Benefits

Breaking the Thermal Wall: TSMC Demonstrates Direct-to-Silicon Liquid Cooling on CoWoS®

TSMC’s Push for Energy-Efficient AI: Innovations in Logic and Packaging

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AI RTL Generation versus AI RTL Verification

AI RTL Generation versus AI RTL Verification
by Bernard Murphy on 11-06-2025 at 10:00 am
Categories: AI, Bronco AI, ChipAgents AI, EDA
4 Comments

RTL generation vs RTL Verification

I should admit up front that I don’t have a scientific answer to this comparison, but I do have a reasonably informed gut feel, at least for the near-term. The reason I ask the question is that automated RTL generation grabs headlines with visions of designing chips through natural language prompts, making design widely accessible. No doubt this has a lot of media appeal, an attractive place to invest AI $$. But the realities of chip design today don’t support that bet and are more aligned with investment in AI-assisted verification. Verification may not be as glamorous as design but looks like a much more compelling target for AI investment today.

Where are the real costs in design?

Years of analysis in the semiconductor industry (e.g. this Wilson report) confirm that on average 50% or more of IC/ASIC project time is spent in verification. Projects require as many verification engineers at peak as design engineers (the people building RTL) and even design engineers spend half their time in verification. Verifying RTL is a major time- and resource-consuming sink in chip design.

That verification far outweighs RTL design should not be surprising in an age where IP reuse and design reuse dominate. Few organizations have the luxury to start from a clean sheet on each design. Even startups will use commercial IP. Silicon Catalyst portfolio companies can tap into a wide range of IP, from Arm for example, at no up-front cost. There will always be some differentiating content requiring from-scratch development or extensive redesign but the hard part there is the innovation and making the idea practical in a competitive PPA envelope, not in creating the RTL.

Challenges for RTL creation

I can’t find a definitive “first” paper on using GenAI to create RTL but there are plenty of recent papers. These continue to show progress, at about the same rate as parallel efforts in software generation, intriguing but not up to hands-free usage.

More common is usage as an assistant – think of an extended auto-completion operation. A designer might describe in a comment what a following always block should do and ask the auto-completer to create that block. An emerging measure of how successful that operation is in practice, whether for RTL or software, is the rate at which the designer/programmer accepts the generated logic. Fairly consistently this seems to be around 25%.

25% is not bad for an autocompleter. How often do you accept an MS-Word or text message autocompletion? I don’t most of the time, but sometimes it’s useful. RTL auto-completion is more complex than sentence completion, so hats off to RTL generators for getting this far.

Why isn’t the acceptance rate better? There are multiple reasons. Lack of a sufficiently broad training corpus and ambiguities in the comment prompt are two obvious examples. Another revealing example is that, without additional coaching, a bot will assume the timing depth of an expression depends on the number of terms in the expression, not recognizing that arithmetic expressions are more costly than logic expressions. For some other examples see this paper.

The core problem is that generating quality RTL is a lot more complex than current systems can rise to, even for an always block. Does it support PPA targets? Does it create security or safety holes? Is the implementation intuitively reasonable and is it readily maintainable by an RTL designer?

Could more of these problems be solved in time? Quite possibly, which is why I think RTL creation moonshots are worth supporting. But we shouldn’t confuse those efforts with near-term ROI.

Opportunities in RTL verification

A big opportunity for return should be in debug, representing 47% of verification effort according to the same Wilson report. Despite years of study, in debug we still haven’t advanced far beyond debugger IDEs, which certainly help visualize behavior but do little to triage or root-cause bugs in aid of compressing debug time. (there are some point solutions, e.g. for triaging CDC violations.)

Promising signs can be seen in agentic approaches to debug, from startups like ChipAgents and Bronco AI. Triage – reducing and assigning a pile of bugs from a regression to sub-teams for further analysis – might be the biggest contribution here. As engineers we tend to obsess about how to automate root cause analysis for hard corner cases, but more effort is likely consumed in triage around the bulk of less complex bugs than in a few anomalous cases. Initial root-cause isolation (did this error come from module A or module B) can drill down to approximate fault locations, to avoid wasting engineer time on trying to debug a problem that isn’t in their code after all.

Agentic methods should be ideal for this sort of analysis for two reasons. First they can learn from expert engineers how they would approach triage and rough root-causing. Second, because they are agentic they should be able to run additional trial simulations to confirm or rule-out preliminary guesses.

This approach to debug builds on verification know-how and methods that have been in refinement for years. Success here, even partial success, could show significant ROI. Contrast that with an as-yet unquantified level of investment to improve RTL generation quality, where we also don’t know what value we can assign to partial success.

Food for thought.

Also Read:

Scaling Debug Wisdom with Bronco AI

CEO Interview with David Zhi LuoZhang of Bronco AI

ChipAgents Tackles Debug. This is Important

CEO Interview with Dr. William Wang of Alpha Design AI

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Memory Matters: The State of Embedded NVM (eNVM) 2025

Memory Matters: The State of Embedded NVM (eNVM) 2025
by Daniel Nenni on 11-06-2025 at 6:00 am
Categories: GlobalFoundries, IP, Samsung Foundry, TSMC
1 Comment

NVM Survey 25 Square Banner for SemiWiki 400x400 px

Make a difference and take this short survey. It asks about your experience with embedded non-volatile memory technologies. The survey is anonymous, and the results will be shared in aggregate to help the industry better understand trends: 2025 Embedded Non-Volatile Memory Survey.

We are now in the AI era where data is the lifeblood of innovation, and embedded NVM stands as a cornerstone technology, retaining information without using power and enabling everything from MCUs and IoT SoCs to automotive controllers and secure elements.

As of November 2025, embedded NVM is moving fast. Edge data is surging, AI features are landing on MCUs and SoCs, and power budgets are tighter than ever. Memory is central to the devices we build. This survey looks at where eNVM stands today in terms of markets, technology, and adoption, and where it’s heading next.

Market Overview and Growth

Embedded emerging NVM, including MRAM, RRAM/ReRAM, and PCM, is entering a broader adoption phase across MCUs, connectivity, and edge-AI devices, with momentum building in automotive and industrial markets. Research firm Yole Group indicate the embedded emerging segment should exceed $3B by 2030, reflecting wider availability in mainstream process nodes and stronger pull where eFlash is no longer a good fit at ≤28 nm.

Technological Advancements

Embedded flash remains foundational, but scaling limits at advanced nodes have pushed MRAM, ReRAM, and embedded PCM to the foreground. Foundries and IDMs are extending embedded options beyond 28/22 nm planar CMOS toward 10–12 nm-class platforms, including FinFET. Yole highlights aggressive foundry roadmaps: TSMC has established high-volume MRAM/ReRAM and is preparing 12nm FinFET ReRAM/MRAM for 2025 and beyond. Samsung, GlobalFoundries, UMC, and SMIC are accelerating embedded MRAM/ReRAM/PCM across general-purpose MCUs and high-performance automotive designs. STMicroelectronics stands out as the IDM fully committed to embedded PCM, ramping xMemory solutions for industrial and automotive MCUs, with 18nm FD-SOI extending reach after 2025.

In parallel, BCD and HV-CMOS flows are incorporating embedded NVM as practical replacements for EEPROM/OTP in analog, power management, and mixed-signal designs. On the IP side, suppliers are qualifying embedded NVM technologies for these platforms, giving designers more options where cost, endurance, and retention outweigh legacy choices. Beyond code and data storage, in-/near-memory compute concepts using eNVM are gaining interest for low-power edge AI inference.

Drivers, Challenges, and Use Cases

Automotive remains the center of gravity for embedded emerging NVM, and 2025 brings a noticeable uptick in secure ICs and industrial MCUs as more products reach production. In practice, ReRAM, MRAM, and PCM each have a role: ReRAM is gaining traction in several high-volume categories; MRAM and PCM are attractive where speed and endurance dominate. The mix varies by node, application, and vendor roadmap.

The challenges are familiar: integrating eNVM at advanced logic nodes, trading off endurance and retention, qualifying to automotive-grade reliability, and achieving cost-effective density as embedded code and AI parameters grow. The trend line is positive, with PDK/IP availability growing and capacity ramping, so these issues are being addressed rather than deferred.

Outlook

By 2030, embedded NVM will underpin more on-chip AI features and practical in-/near-memory compute blocks, with broader use in neuromorphic-inspired accelerators at the edge. Yole’s projections indicate that the embedded emerging segment is now the primary engine of growth, led by ReRAM in high-volume MCUs and analog ICs, while MRAM and embedded PCM consolidate in performance-critical niches. As edge data grows, eNVM’s role expands from “just storage” to part of the computing fabric, redefining efficiency and making embedded memory more central than ever to device intelligence.

Bottom line: In 2025, embedded NVM isn’t just memory, it’s the enabler of intelligent, persistent systems on chip. With accelerating adoption across MCUs and edge SoCs, and clear roadmaps from leading foundries and IDMs, the trajectory is set: embedded memory matters more than ever. Let us know your opinion by taking the short survey.

Take the 2025 Embedded Non-Volatile Memory Survey Here.

Also Read:

Chiplets: Powering the Next Generation of AI Systems

Podcast EP312: Approaches to Advance the Use of Non-Volatile Embedded Memory with Dave Eggleston

Podcast EP311: An Overview of how Keysom Optimizes Embedded Applications with Dr. Luca TESTA

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5 Lessons the Semiconductor Industry Can Learn from Gaming

5 Lessons the Semiconductor Industry Can Learn from Gaming
by Admin on 11-05-2025 at 10:00 am
Categories: EDA, Perforce, RISC-V

Perforce 1

By Kamal Khan
The semiconductor world has always been the beating heart of tech innovation, powering everything from our smartphones to the latest AI breakthroughs. However, as chip complexity increases and market demands accelerate, adherence to traditional development cycles may be stagnating design teams and slowing the pace of innovation.

In contrast, the gaming industry has perfected a model of rapid, iterative development and profound user-centricity. Game developers ship products, gather massive amounts of feedback, and iterate at a pace that is often foreign to the more rigid semiconductor world.

For semiconductor design teams, engineers, and executives, the methodologies that drive the fast-paced gaming world offer valuable new perspectives. Here are five key lessons they can learn from gaming:

1. Embrace Iterative Innovation and Agility

The Challenge: Rigid, Waterfall-Style Development Cycles

Semiconductor firms become entrenched in rigid development cycles that feel almost ceremonial. Roadmaps are often planned years in advance, and the design process follows a rigid, waterfall-like progression from specification to tapeout. While this approach supports the careful level of control needed to prevent costly errors, it can also stifle innovation and make it difficult to pivot in response to new market demands or technical challenges.

Lesson: Develop Agility Through Iteration and Feedback.

Game development is a dynamic and often chaotic process. Studios frequently release beta versions of their games only to pivot entire projects after a single weekend of testing. This agile approach allows them to refine the user experience, fix bugs, and ensure the final product resonates with its audience.

Applying It to Semiconductors:

While the physical constraints of chip manufacturing are undeniable, the pre-production and verification stages offer significant room for agility. Semiconductor teams can adopt a more iterative mindset by:

  • Implementing Agile Verification: Instead of waiting for the entire design to be complete, teams can use incremental verification techniques to test and validate smaller blocks of IP as they are developed. This allows for earlier feedback and reduces the risk of discovering major flaws late in the cycle.
  • Leveraging Early Prototypes: Using Field-Programmable Gate Arrays (FPGAs) and emulation platforms allows for earlier software development and system-level testing. This creates a feedback loop that can inform hardware design long before tapeout, much like a game’s beta test.
  • Adopting Spiral Development Models: Rather than a linear progression, a spiral model involves creating successive iterations of a design, with each loop building upon the last and incorporating feedback and new requirements.

By divorcing themselves from long-duration design cycles, semiconductor firms can become more experimental, responsive, and ultimately more innovative.

2. Understand and Prioritize the End-User Experience

The Challenge: A Disconnect from the End-User

Semiconductor companies are engineering-driven and often disconnected from the humans who ultimately use their products. They tend to focus on hitting performance benchmarks, increasing transistor density, and achieving specific power targets. While these metrics are critical, they can lead to a disconnect from the software developers and end consumers who ultimately use the technology.

Lesson: Get to Know Your End-Users.

Game developers are fanatical about the player experience. They invest countless hours in playtesting and user research to ensure that a game not only performs well but also “feels right.” Gameplay mechanics, user interface design, and overall enjoyment are key to success, and developers will often scrap months of work if players don’t find the experience compelling.

Applying It to Semiconductors:
Chip designers can think beyond raw benchmarks and consider how hardware design choices impact the end application.

  • Prioritize Real-World Workloads: Instead of focusing solely on synthetic benchmarks, design and optimize chips for specific, real-world applications like AI inference, high-fidelity gaming, or complex data processing. NVIDIA’s success is a testament to this approach; their GPUs are designed to excel in both gaming and AI, two markets with very specific, high-performance demands.
  • Engage with Software Developers: By actively engaging with the software developers who build applications on your hardware, chipmakers can gain invaluable insights into which features are most important and how to optimize chips for these programmers.

By shifting the focus from theoretical improvements to tangible user benefits, semiconductor firms can create products that offer a superior real-world experience and command greater market loyalty.

3. Implement Real-Time Optimization

The Challenge: Static, Pre-Defined Performance

A chip’s performance parameters are traditionally set during the design phase. While some level of power management exists, the hardware itself cannot adapt its core functionality in real-time in response to changing workloads. This can lead to inefficiencies where a chip may consume more power than necessary or fail to deliver peak performance when it is most needed.

Lesson: Adopt Real-Time, Game Engine-Like Adaptation

Game engines like Unity and Unreal don’t simply set parameters once, they constantly adjust rendering quality, physics calculations, and asset loading to maintain a smooth and consistent frame rate. The result is a perfect balance of visual quality and performance that keeps their users engaged.

Applying It to Semiconductors:
The chips of the future should behave more like game engines by intelligently and dynamically adapting to their workloads.

  • AI-Driven Design and Power Management: The semiconductor industry is exploring AI in electronic design automation (EDA) to optimize chip layouts. The next step is to integrate this intelligence directly into silicon via on-chip AI that predicts future workloads and pre-emptively adjusts clock speeds, voltage, and even processing unit configuration.
  • Adaptive Architectures: Design chips with more flexible and reconfigurable components. A processor that could dynamically reallocate resources between its CPU, GPU, and neural processing units based on the specific demands of an application would always be optimized for the task at hand.

By building chips that can learn and adapt in real-time, the semiconductor industry can elevate performance and efficiency beyond what is possible in static designs.

4. Break Down Ecosystem Walls

The Challenge: Fragmented Architectures and Ecosystems

Fragmented or varied architectures (like x86 and ARM) and proprietary ecosystems force software developers to spend significant time and resources optimizing their code for each specific platform. This lack of interoperability stifles innovation and creates a frustrating experience for developers.

The Lesson: Solve for Cross-Platform Consistency

The gaming industry has largely solved the challenge of cross-platform development. A game developed using an engine like Unity can be deployed across $3,000 PC or a five-year-old smartphone with a relatively unified feel and performance. This is achieved by focusing on tools and APIs that work seamlessly across different hardware.

Applying It to Semiconductors:
There is a significant opportunity for chipmakers to embrace this ecosystem-first mindset.

  • Standardize Software Interfaces: By working together to create more standardized APIs and hardware abstraction layers (HALs), the industry can reduce the burden on software developers. The goal should be to allow developers to write code once and have it run efficiently across a wide range of hardware.
  • Embrace Open Standards: Supporting open standards like RISC-V is a powerful way to break down ecosystem walls. An open and collaborative approach to instruction set architecture (ISA) design encourages broader adoption and innovation.

The days of writing completely different code for different chips should be behind us. Hardware should be designed for seamless interoperability.

5. Build Communities, Not Just Products

The Challenge: Siloed Design Spaces and a B2B Mindset

Many semiconductor firms operate with a traditional B2B mindset, viewing their customers as other businesses rather than a community of developers and end users. This approach leads to siloed design processes and missed opportunities for valuable feedback and co-innovation.

The Lesson: Harness the Power of Community

The most successful game companies treat their communities are their greatest asset. They actively engage with players, streamers, and modders (users who create modifications for games) to obtain invaluable feedback. This symbiotic relationship elevates their products to meet consumer needs, fosters loyalty, and serves as a powerful marketing engine.

Applying It to Semiconductors:
Semiconductor firms can unlock immense value by cultivating genuine communities.

  • Open-Source Collaboration: Actively participating in and contributing to open-source hardware and software projects is a powerful way to engage with the developer community. This fosters goodwill, accelerates innovation, and provides direct insight into the needs of your users.
  • Gamified Learning and Engagement: The industry can draw inspiration from gaming to educate the next generation of engineers. For example, researchers at UC Davis developed “Photolithography,” a game that teaches players how to build virtual semiconductors.

By transforming from closed-off component suppliers into active ecosystem participants, semiconductor companies can build stronger relationships and create products that are more aligned with the needs of their market.

Designing an Adaptive and Collaborative Semiconductor Future

AI and gaming are powerful forces propelling advancements in semiconductor technology. The companies that lead will do so by incorporating agile methodologies, real-time simulations, AI-driven automation, scalability, and user-centric design. However, this shift requires the right tools.

Perforce IPLM provides a unified environment for managing the complexities of semiconductor design, from IP lifecycle management to verification and documentation. By breaking down silos and enabling secure, global collaboration across teams, Perforce IPLM empowers semiconductor companies to adopt the agile principles of the gaming world and accelerate their path to innovation. Learn more today.

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Kamal Khan is Vice President North American Gaming and Hi Tech. He has over 20 years of domestic and international experience, specializing in PLM, Data Management, IP lifecycle management, IoT Security, Semiconductors, Enterprise software, EDA, CAD, 3D Printing, Cloud solutions. 

This article was originally published on Perforce.com. For more information on how Perforce IPLM streamlines semiconductor development , visit https://www.perforce.com/products/helix-iplm
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Podcast EP316: An Introduction to Hardware Security Modules (HSMs) and Marvell’s Unique LiquidSecurity Offering with Bill Hagerstrand
by Daniel Nenni on 11-05-2025 at 8:00 am

Daniel is joined by Bill Hagerstrand, director of Security Business at Marvell Technology where he manages the market-leading Marvell LiquidSecurity® HSM business. Bill has more than 20 years of experience in the semiconductor, AI/machine learning, and security markets.

Bill explains what an HSM is, how it is configured and what functions it performs across multiple applications. He explains the key customer needs in this growing market both today and tomorrow. Bill also describes the unique capabilities offered by Marvell’s LiquidSecurity products and how they provide expanded capabilities in the marketplace.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

Posted on

A Compelling Differentiator in OEM Product Design

A Compelling Differentiator in OEM Product Design
by Bernard Murphy on 11-05-2025 at 6:00 am
Categories: AI, EDA, Siemens EDA

PartQuest

Jennifer, an OEM hardware designer, is planning a product around a microcontroller she thinks will meet her needs and wants to supply power from a 3V coin cell battery which she must connect though a boost controller. Jennifer searches a rough description of the part she needs, generating a long list of component manufacturers who are all anxious to attract her attention. She clicks through the websites, scans the headlines and tries to drill down through white papers and technical datasheets. She ends her day with a headache and still no clear idea of who would be the best fit since tradeoffs in how she builds her design depend on component details that are difficult to extract from multiple dense PDFs.

Suppose instead she started her parts search along a path designed to guide her painlessly to a decision. She can do all the discovery she wants without having to leave her terminal, without needing to read through lengthy datasheets, or committing to a purchase. She can experiment with interactive reference designs, exploring parameter changes that will more closely match her needs. At every step Jennifer becomes more confident that she has found the right component to fit her objectives. This component manufacturer is on track for a design win before sales ever picks up a phone, and she will be drawn naturally to look for her next component from the same supplier.

Redesigning initial component discovery for the OEM engineer

Nobody wants to wade through datasheets and technical specs in the early stages of discovery. This is the age of AI and chatbots. We should be able to ask natural language questions about configurations and operating parameters and expect to get helpful answers — more detailed answers than are available through a generic GPT-like search.

This more effective search might narrow the field perhaps to a couple of options. Our engineer now wants to experiment with the component she thinks might be the best fit, but without having to get into detailed eCAD yet. The manufacturer offers an interactive reference design in which she can experiment with parameters, maybe battery voltage and internal resistance, and directly view impact on behavior, say for load current draw.

The manufacturer also offers exploration tools to view schematics, PCB layout, and BOM for the reference design so she can develop a sense of how this may translate to her product objectives. At the same time, she can check availability, supply chain issues, and regional compliance issues, minimizing time wasted on manufacturing mismatches and forestalling any late-stage manufacturing surprises.

A Siemens white paper has an interesting way of describing this interaction. Unlike traditional marketing-centric web pages and PDFs, this is engineering outreach, not marketing outreach.

Now that she is committed to this path, Jennifer can transition her trial experiments into full eCAD development around her design, through a natively supported tool suite accessible through this interactive design enablement flow or through a preferred in-house flow supported by direct eCAD model downloads based on the parts she’s selected — while continuing to keep an eye on potential manufacturing hiccups as geopolitical realities evolve.

Collaboration, enhancing manufacturer stickiness

Jennifer may have questions which can’t be answered through AI searches or interactive references. Collaborative discussion with an expert application engineer can guide her through these concerns. With permission, the apps experts can review detailed and more open-ended questions in the context of a design example and suggest possibilities through markup, comments or examples — without the need to schedule meetings.

This interaction has obvious benefits both for the designer and for the component manufacturer. The designer has a simple glide path to component selection using the language she speaks: natural language filters, trials against an interactive reference design and schematic and PCB layout to confirm the fit to her objective. The manufacturer gets a prospect already invested in how their components fit her solution without the overhead of meetings. Everyone wins.

Does this vision sound appealing? Read this Siemens white paper for a more detailed understanding of how they have enabled this solution together with Microchip as a component manufacturer.

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