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Pioneering Engineer Dr. Tsu-Jae King Liu to Receive Semiconductor Industry’s Top Honor

Pioneering Engineer Dr. Tsu-Jae King Liu to Receive Semiconductor Industry’s Top Honor
by Daniel Nenni on 11-04-2025 at 10:00 am

Dr. Tsu Jae King Liu SemiWiki

In a landmark recognition of trailblazing innovation and leadership, Dr. Tsu-Jae King Liu, the newly elected President of the National Academy of Engineering has been named the 2025 recipient of the Global Semiconductor Alliance’s highest accolade: the Dr. Morris Chang Exemplary Leadership Award. Announced on October 23, 2025, this prestigious honor underscores Liu’s profound influence on semiconductor technology, from groundbreaking inventions that power modern computing to her steadfast advocacy for engineering education and global collaboration. The award, to be presented at GSA’s Annual Awards Celebration on December 4, 2025, in San Jose, California, celebrates individuals whose visionary contributions have reshaped the $662 billion industry.

The Dr. Morris Chang Exemplary Leadership Award, established in 1999 and named after TSMC founder Dr. Morris Chang, honors exceptional figures who drive innovation, growth, and long-term opportunities in semiconductors. It recognizes creativity that yields measurable impacts, such as fostering company growth or advancing the supply chain, and is open to nominees from academia, industry, government, or venture capital. Administered by GSA’s Awards Committee and approved by its Board, the award is selective—sometimes withheld if no candidate meets its rigorous standards. Liu joins an elite cadre of past honorees, including Chang himself, whose leadership at TSMC revolutionized chip manufacturing.

Born in Taiwan and raised in the United States, Liu’s journey exemplifies the fusion of academic rigor and practical ingenuity. She earned her B.S., M.S., and Ph.D. in electrical engineering from Stanford University in 1984, 1986, and 1994, respectively. Her early career at Xerox Palo Alto Research Center (1992–1996) focused on thin-film transistor technology, enabling the high-definition flat-panel displays that dominate consumer electronics today. In 1996, she joined the University of California, Berkeley’s Department of Electrical Engineering and Computer Sciences, where she spent over 25 years as a professor, amassing more than 550 publications and 97 U.S. patents.

Liu’s crowning achievement is her co-invention of the FinFET in collaboration with Berkeley colleagues Chenming Hu and Jeffrey Bokor. Introduced in the early 2000s, this nanoscale design overcame the limitations of traditional planar transistors, allowing chips to shrink dramatically while boosting performance and efficiency. FinFETs underpin advanced processors in smartphones, servers, and AI systems, enabling Moore’s Law to persist amid physical constraints. Her work earned accolades like the DARPA Significant Technical Achievement Award, the IEEE Kiyo Tomiyasu Award for pioneering contributions to electronics engineering, and the Intel Outstanding Researcher in Nanotechnology Award. In 2017, she was elected to the NAE; in 2018, to the National Academy of Inventors. As an IEEE Fellow, Liu also received the IEEE Founders Medal in 2024 for her lifetime of innovation.

Beyond research, Liu’s leadership has amplified her impact. At Berkeley, she chaired the EECS department (2014–2016), served as Vice Provost for Academic and Space Planning (2016–2018), and led the College of Engineering as Dean (2018–2025). In these roles, she championed interdisciplinary initiatives, diversified STEM participation, and forged industry ties to address talent shortages. Her mentorship earned her the EECS EE Division Outstanding Teaching Award in 2003 and UC Berkeley’s Distinguished Teaching Award. Elected NAE President in 2025, Liu now advises on national engineering priorities, including the CHIPS Act’s workforce needs. She has served on boards for Intel and MaxLinear and as a NIST Industrial Advisory Committee member, bridging academia and industry.

“Tsu-Jae King Liu’s leadership and groundbreaking contributions have helped shape the future of semiconductor technology and the talent who power it,” said Jodi Shelton, GSA CEO. “Her influence spans industry and academia, and her example continues to inspire generations of innovators. We are proud to honor her as the first woman in academia to receive the Dr. Morris Chang Exemplary Leadership Award.”

Liu’s Taiwanese heritage adds poignant resonance. “I am deeply honored to have been selected as the 2025 Dr. Morris Chang Exemplary Leadership Award recipient, especially since my ancestral roots are in Taiwan where Dr. Chang’s leadership has had transformative impact,” she stated. “I have been very fortunate to work with – and learn from – many exemplary leaders, and to be part of a vibrant, global community that advances technology for the benefit of people and society.”

This award arrives at a pivotal moment for semiconductors, amid geopolitical tensions and surging demand for AI and clean energy tech. Liu’s holistic approach—merging invention with equitable education—positions her to guide the NAE in tackling these challenges. As GSA’s event draws over 1,500 leaders, her recognition not only celebrates past triumphs but ignites future ones, ensuring the industry’s innovations serve humanity broadly. In an era demanding resilient supply chains and diverse talent, Dr. Liu’s legacy illuminates the path forward, proving that exemplary leadership transcends borders and disciplines.

Also Read:

IEDM 2025 and the 100th Anniversary of the FET

AI-Driven DRC Productivity Optimization: Revolutionizing Semiconductor Design

Pioneering Edge AI: TekStart’s Cognitum Processor Ushers in a New Era of Efficient Intelligence


PDF Solutions Charts a Course for the Future at Its User Conference and Analyst Day

PDF Solutions Charts a Course for the Future at Its User Conference and Analyst Day
by Mike Gianfagna on 11-04-2025 at 8:19 am

PDF Solutions Charts a Course for the Future at Its User Conference and Analyst Day

Every major supplier has its user event. This is usually where the latest innovations from the company are revealed and progress over the past year is promoted. While there may be user presentations and exhibits, the primary focus is typically the vendor communicating its messages to the user base. The upcoming PDF Solutions Users Conference & Analyst Day is different. The tagline for the event is Shaping Tomorrow’s Semiconductor Ecosystem— Together.

The last part is key. PDF has assembled a diverse group of senior executives from across the semiconductor ecosystem at this event. The presentations will be compelling, with a primary focus on how the entire group is collaborating with PDF to catalyze a new direction for the semiconductor industry. This focus on collaboration to change the future is unique to PDF and quite potent in its goals. Let’s look at how PDF Solutions charts a course for the future at its User Conference and Analyst Day. That theme was already present in PDF CEO John Kibarian’s keynote at the recent SEMICON West event which I covered a few weeks ago. You can find my perspective on the keynote here and the content of his keynote here.

Event Overview

The graphic at the top of this post provides the dates and location for the event. A registration link is coming, but let’s first look at what’s in store when you attend.

On the event webpage, PDF points out that the semiconductor industry is experiencing accelerated innovation. Further to this point demand has never been higher, complexity never greater, and the opportunities never more exciting. A critical observation is that realizing this expanded potential will require partnerships, shared secure scalable solutions, and a collective commitment to pushing boundaries.

With this backdrop, PDF has assembled a world-class group of industry executives for the featured presentations. Below are the folks currently listed. This is an impressive assembly of visionary leaders.

Featured Event Speakers

After cocktails and dinner on the first day of the event, attendees will be treated to a fireside chat with Tom Caulfield, Jean-Marc Chery and John Kibarian. In my experience, these informal discussions yield significant and actionable information.

PDF promises to demo breakthrough technologies in AI-driven manufacturing, equipment connectivity, and yield optimization at the event. Real case studies will also be presented that showcase measurable impact from technology development to high-volume production. These case studies will span fabless to foundries and assembly and test.

There will also be demo kiosks at the event that cover:

  • Enterprise Integration / Operational Product Costing
  • Exensio Studio AI Solution
  • Next Generation Equipment Control and Connectivity
  • Guided Analytics Solution
  • Remote Equipment Connectivity & Control for PDF eProbe Using secureWISE Solution

A Closer Look at the Event

Dr. Christophe Begue

You can peruse the detailed agenda on the event website. Links are coming. I had the opportunity to chat with Dr. Christophe Begue, VP of corporate strategic marketing at PDF. He provided some additional details about the event.

Christophe explained that he sees PDF Solutions as the convener for the semiconductor industry, bringing companies from the ecosystem together with a shared vision to improve the process. He pointed out that the extensive data engine that PDF has developed becomes a critical tool to allow this work to occur.

He listed three main themes for the 2025 PDF Solutions Users Conference that capture this sentiment:

  1. Cross industry collaboration, execution at scale
  2. Industrial applications of AI, first and foremost, is about data
  3. Connectivity, security and trust are best delivered from a neutral industry platform

He also pointed out that not all the participants at the conference are PDF customers. The footprint that PDF Solutions is creating goes beyond just a customer/supplier relationship.

Christophe provided some details about the presentations that will be part of the two-day event. Beyond the previously mentioned industry keynotes, there will discussions of how to

accelerate digital transformation in semiconductor manufacturing. PDF’s eProbe solution will also be discussed, with details on the technology, adoption, business model, and a real PDF end-to-end solution. There will also be a deep dive on PDF’s technical strategy.

PDF’s equipment and fab integration solutions will be presented, with details of fab data infrastructure and manufacturing analytics solutions. How PDF’s Exensio enables advanced test will also be presented with examples.

This is a bit more detail of a full and robust two-day agenda. No matter what part of the ecosystem you are working in, you’ll find important and actionable information at this event.

More Details and How to Register

I highly recommend you attend this event. This is the future of the semiconductor industry. You can see an overview of the event here. Some more details of the event can be found here.  And you can purchase a ticket for the entire event here

The conference will be held at the Santa Clara Marriott. You can find details about the location and reservations here. Do it today! And that’s how PDF Solutions charts a course for the future at its User Conference and Analyst Day.

 


TCAD Update from Synopsys

TCAD Update from Synopsys
by Daniel Payne on 11-03-2025 at 10:00 am

TCAD importance min

We live in an exploding AI world, and this has put pressure on foundries to deliver new products faster than ever before. Any help to accelerate the semiconductor R&D goes a long way to make the life of Fab engineers easier. EDA tools in the TCAD (Technology Computer Aided Design) category are critical for TCAD engineers to accelerating R&D by simulating semiconductor process and devices before anything is manufactured in the Fab. TCAD engineers work with process, integration, and device engineers to provide critical insight into semiconductor manufacturing to reduce R&D cost, optimize the technology node and product faster, and make foundry more profitable.

Synopsys is the industry-leader for TCAD tools, and its Sentaurus suite of TCAD products are considered as the gold standard. One of the main challenges of TCAD engineers is to calibrate the tools to manufacturing data and improve accuracy for their workflows. I recently attended a webinar on Sentaurus Calibration Workbench (SCW), which is one of the recent TCAD tools from Synopsys, that uses ML to help TCAD engineers automate the calibration.

The first time that I heard about Sentaurus it reminded me of the galaxy named Centaurus.

This webinar had three Synopsys people presenting:

  • Saurabh Suryavanshi, Product Manager
  • Youngkwon Cho, Senior Staff Engineer
  • Dipanjan Basu, Principal Engineer

Saurabh explained that TCAD tools provide physics-based directionality and helps engineers perform “what-if” analysis during early stages of R&D. Furthermore, by calibrating the TCAD tools to experimental data the users can improve the accuracy of the models and use the TCAD simulations to supplement wafer-based learning during Technology development and Process Ramp. Calibration of TCAD tools, essentially further elevates the value provided by TCAD tool from “what-if” analysis to improving the efficiency of Fab by reducing R&D cost and time to market.

In the past, TCAD engineers primarily relied on manual methods for calibration, but that approach took too much time and provided sub-optimal results, because it is a complex task and provided little exploration of the parameter space. A newer approach for calibration proposed by Synopsys uses  automation by having re-usable workflows with expert modules, adopting the Python language and a simple GUI to improve ease of use, and shortening the calibration time with gradient-based and Machine Learning (ML) algorithms.

Here is what an end-to-end calibration workflow looks like –

The Sentaurus Calibration Workbench helps a TCAD engineer navigate the end-to-end calibration workflow by helping with set up and execution of the calibration workflow, from data preparation to workflow setup to execution to evaluating the results.

Youngkwon showed how you can prepare a new project from a Sentaurus Workbench (SWB) parent deck in developing a calibration workflow, then use that in SCW. For the calibration workflow setup phase, you can use both the tool GUI and a Python API. SCW provides both gradients based as well as machine learning model for calibration.

Synopsys has adopted and enhanced open-source models for the ML-based workflows. SCW provides support to both expert users as well as new users by supported low-level as well as high level ML models.  In addition, Synopsys provides expert written application notes that provide an end-to-end calibration workflow for critical calibration applications such as CMOS and SIMS. The high-level ML model as well as application notes provide a quick start-up option for users. For expert users, SCW also allows users to bring in their own custom model written either in PyTorch or TensorFlow.

For ML-based workflow, you define the DOE and optimize the number of simulations. Furthermore, the user can run sensitivity analysis to identify most critical parameters. Youngkwon highlighted these two features as most critical for reducing the time to calibration.

The final phase of using SCW is the result evaluation where ML visualization provides interactive graphs for advanced analytics, plus you may create custom tasks with your own ML models. With learning curve analysis, you examine how model scores change with training set size. The DOE map function examines the error distributions, finding areas of low predictive power. On the parallel coordinates plot it shows optimal conditions or finds outliers through the connections between input and output.

Dipanjan shared key use-cases on CMOS calibration, 1D SIMS calibrations, hierarchical model calibration, and mobility calibration in GaN devices. All these applications are available for existing users through SolvNet. The CMOS calibration, which usually involves dozens of parameters, showed the true power of workflow automation provided by SCW. The entire calibration was divided into 5 workflows, where parameters were calibrated one step. The SIMS calibration is a great example of using SCW to not-only handle multiple parameters but also multiple targets and multiple implant species. The final validation step re-runs the TCAD simulation with the calibrated parameters to evaluate the model, showing that the model fits closely with experimental data post-calibration as shown by the figure below.

Dipanjan also shared Hierarchical modeling using the Garand Monte Carlo (GMC) in the Sentaurus Device (S-Device) tool was presented for 3D structures. This was a unique case, where calibration is not done against the experimental data but between two modeling frameworks.  Such calibration allows users to attain accuracy of GMC simulation, while maintaining the speed of continuum modeling in S-Device.

Towards the end, Saurabh shared three customer success stories. In the first story, he showed an order of magnitude improvement in calibration at a memory customer. This was possible by following the right practices throughout the end-to-end calibration workflow and utilizing SCW as prescribed in the workflow. He also shared a success story at an advanced logic customer, where they had a 3X improvement in simulation time by moving from gradient-based calibration to ML-based calibration. Lastly, he shared the success at a mature node customer where the calibration was impossible by manual methods. They used SCW to define an iterative flow and used ML to achieve calibration with mere low hundreds of DOE simulations. All these success stories showed significant quality of result while helping users to reduce the time-to-calibration.

Summary

Device and process development are daunting tasks for foundries to undertake, so any automation is welcomed to speed up TCAD simulations. Synopsys has responded to this challenge by bringing ML technology into the TCAD calibration flow in their Sentaurus Calibration Workbench (SCW) tool, bringing about 10X faster time to results even with more than 50 parameters. This tool is widely application across the industry including memory, logic, as well as specialty device manufacturer.

View the archived webinar online.

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Synopsys and NVIDIA Forge AI Powered Future for Chip Design and Multiphysics Simulation

Synopsys and NVIDIA Forge AI Powered Future for Chip Design and Multiphysics Simulation
by Daniel Nenni on 11-03-2025 at 6:00 am

Synopsys Nvidia Agentic AI 2025

In a landmark announcement at NVIDIA’s GTC Washington, D.C. conference Synopsys unveiled deepened collaborations with NVIDIA to revolutionize semiconductor design and engineering through agentic AI, GPU-accelerated computing, and AI-driven physics simulations. This partnership, building on over three decades of joint innovation, integrates Synopsys’ expansive portfolio (now bolstered by its recent acquisition of Ansys) with NVIDIA’s cutting-edge AI and GPU technologies.

The goal: empower engineers to tackle unprecedented challenges in chip design, manufacturing, and system-level simulations with unprecedented speed, accuracy, and intuition.

At the heart of the announcement is agentic AI for next-generation semiconductor development. Synopsys is fusing its AgentEngineer™ technology with NVIDIA’s NeMo Agent Toolkit, incorporating Nemotron open models and datasets. This synergy supercharges autonomous design flows, transforming AI from a mere tool into a collaborative partner that optimizes workflows, enhances productivity, and accelerates time-to-market. For instance, Synopsys’ chip design agents, currently in development, streamline formal verification processes. These agents deepen signoff efficiency, uncover critical bugs overlooked by human reviewers, and boost overall design quality. NVIDIA is piloting this AgentEngineer tech for AI-enabled formal verification, underscoring its practical impact on advanced node processes like 2nm and beyond. By automating repetitive tasks and providing intelligent insights, agentic AI addresses the escalating complexity of AI chips, where design cycles have ballooned amid exploding transistor counts and power constraints.

Complementing this is accelerated computing, leveraging NVIDIA’s GPU prowess to turbocharge Synopsys’ software suite, the industry’s broadest, spanning nearly 20 GPU-optimized products. Synopsys is expanding integrations for compute-intensive workloads, including EDA, test, and manufacturing tools. A standout example is Ansys Fluent® computational fluid dynamics (CFD) software, which achieves a staggering 500x speedup via GPU acceleration and AI initialization for fluid simulations, vital for thermal management in high-performance AI data centers. Similarly, Synopsys QuantumATK® for atomistic simulations delivers up to 15x performance gains using NVIDIA libraries and GPUs, rendered seamlessly in NVIDIA Omniverse for immersive visualization. These enhancements extend to computational lithography, where Synopsys’ OPC software on NVIDIA’s cuLitho platform slashes runtime compared to CPU-based methods, enabling TSMC and others to push physics limits for sub-2nm nodes. The result? Faster iterations, reduced energy consumption, and scalable simulations for everything from quantum devices to hyperscale systems.

The third pillar, AI physics, merges NVIDIA’s AI physics engines with Synopsys’ simulation tools to model real-world complexities with extraordinary fidelity. Engineers can now simulate atomic-scale semiconductor behaviors or macro-scale phenomena like aircraft aerodynamics in Omniverse, blending physics-based accuracy with AI’s predictive power. “With NVIDIA AI physics technologies and agentic AI integrated within Synopsys tools, engineers are empowered to simulate the complexities of the real world with extraordinary fidelity and speed,” stated Synopsys executives. This is particularly transformative for automotive and aerospace, where Synopsys’ digital twin solutions—integrated with Omniverse—validate software-defined vehicles pre-manufacturing, slashing costs and enhancing safety.

These collaborations arrive at a pivotal moment. The semiconductor industry faces mounting pressures: AI demand surges transistor densities, geopolitical tensions strain supply chains, and sustainability mandates demand efficient designs. Synopsys’ post-Ansys portfolio spans silicon-to-systems, from EDA to multiphysics, positioning it to unlock insights across scales. NVIDIA’s Blackwell GPUs and CUDA-X libraries further amplify this, with Synopsys adopting them for TCAD and lithography to yield “unprecedented performance gains,” per Sanjay Bali, Synopsys’ SVP of strategy.

The implications ripple outward. For chipmakers like TSMC and Intel, agentic AI means fewer design respins and quicker innovation ramps. In automotive, Omniverse-enabled twins could halve validation times for Level 4 autonomy. Broader industries, from energy to healthcare, benefit as AI physics democratizes high-fidelity modeling. Yet challenges remain: ensuring AI agents’ trustworthiness in safety-critical apps and scaling GPU infrastructure amid chip shortages.

Bottom line: This NVIDIA-Synopsys alliance heralds an era where engineering is intuitive and boundary-pushing. By weaving agentic AI’s autonomy, accelerated computing’s velocity, and AI physics’ precision, it promises to fuel the next industrial revolution—one where silicon dreams become reality faster than ever.

Also Read:

Chiplets: Powering the Next Generation of AI Systems

The Rise, Fall, and Rebirth of In-Circuit Emulation: Real-World Case Studies (Part 2 of 2)

Statically Verifying RTL Connectivity with Synopsys


IEDM 2025 and the 100th Anniversary of the FET

IEDM 2025 and the 100th Anniversary of the FET
by Daniel Nenni on 11-02-2025 at 10:00 am

IEDM 2025 SemiWiki

The International Electron Devices Meeting (IEDM) is the world’s preeminent forum for unveiling breakthroughs in semiconductor and electronic device technology, manufacturing, design, physics, modeling, and circuit integration. Sponsored by the IEEE Electron Devices Society, it has been a cornerstone event since 1955, attracting thousands of researchers, engineers, and industry leaders annually to discuss innovations that drive the electronics industry forward. As we approach its 71st edition, IEDM 2025 promises to be particularly momentous, commemorating the 100th anniversary of the field-effect transistor (FET), a foundational invention patented in 1925 that revolutionized modern computing and electronics.

Scheduled for December 6-10, 2025, at the Hilton San Francisco Union Square in San Francisco, California, the conference adopts the theme “100 YEARS of FETs: SHAPING the FUTURE of DEVICE INNOVATIONS.” This milestone edition will blend retrospective insights with forward-looking advancements, emphasizing how FETs and their evolutions continue to enable emerging technologies like AI, quantum computing, and sustainable electronics. Attendees can expect a hybrid format, with in-person sessions complemented by on-demand access to recorded presentations post-event, ensuring global participation.

The program is rich and diverse, featuring over 220 presentations, including invited and contributed papers. Highlights include three plenary talks by renowned experts, offering high-level perspectives on industry trends. Six tutorials on Saturday, December 6, will provide foundational knowledge for newcomers and specialists alike, while two short courses on Sunday, December 7, delve deeper into cutting-edge topics. Evening panel discussions will foster debate on pressing challenges, and exhibits from December 8-10 showcase the latest tools and products from sponsors.

A standout feature is the five special focus sessions, curated to address timely themes:

  • Emerging Neural Interface Technologies for Human Interface, exploring bio-electronic bridges between biology and electronics.
  • AI Memory: Technology and Architecture, focusing on efficient solutions for AI workloads through innovations in memory and logic.
  • Leading Semiconductor Products and Advanced Packaging, highlighting integration strategies for next-gen chips.
  • Emerging Power Electronic Devices and Integration for a Sustainable Society, addressing energy-efficient power systems for mobility and grids.
  • IEDM’s Finest Innovations: A Retrospective Leading to the Future, reflecting on historical breakthroughs to inspire tomorrow’s devices.

These sessions underscore IEDM’s role in tackling global challenges, from AI efficiency and beyond-silicon materials to neuromorphic computing and eco-friendly power devices.

The call for papers, issued in May 2025, invites original work across nine technical areas, including Advanced Logic Technology, Emerging Device and Compute Technology, Memory Technology, and more. Emphasis is on novel results, with strict anti-plagiarism policies and requirements for in-person presentations. Student papers are encouraged, with awards and travel support available.

Bottom line: IEDM 2025’s significance lies in its timing amid rapid advancements in semiconductors, driven by demands for AI, 5G/6G, and electrification. By gathering academia, industry, and government, it accelerates technology transfer, fostering collaborations that could define the next century of device innovation. Whether you’re a researcher presenting groundbreaking work or an executive scouting trends, this conference is essential for staying at the forefront of electron devices. With its blend of history and futurism, IEDM 2025 not only celebrates the FET’s legacy but also charts paths to sustainable, intelligent electronics that will transform society.

I hope to see you there!

Registration Details

Also Read:

Breaking the Thermal Wall: TSMC Demonstrates Direct-to-Silicon Liquid Cooling on CoWoS®

How the Father of FinFETs Helped Save Moore’s Law

Revolutionizing AI Infrastructure: Alchip and Ayar Labs’ Co-Packaged Optics Breakthrough at TSMC OIP 2025


CEO Interview with Sanjive Agarwala of EuQlid Inc.

CEO Interview with Sanjive Agarwala of EuQlid Inc.
by Daniel Nenni on 11-01-2025 at 10:00 am

EuQlid Co founders picture

Sanjive Agarwala is co-founder and CEO of EuQlid, a quantum technology company, developing novel 3D imaging tools to support the design and manufacturing of semiconductors and batteries.

Prior to EuQlid, Sanjive served as Corporate Vice President and General Manager of the IP Group at Cadence Design Systems. His business included silicon proven analog, advanced memory interfaces, high-speed SerDes IPs that are all based on industry-standard protocols and Tensilica Processor IP system solutions, with a focus on expanding the Cadence IP portfolio and enabling customers to get their system-on-chip (SoC) products to market faster and with higher quality.

Prior to Cadence, Sanjive was at Texas Instruments, where he led the development of the company’s digital signal processing, artificial intelligence, and digital/analog platform technology, as well as high-end SoCs targeting automotive, industrial, and wireless base-station applications.

Tell us about your company?

EuQlid, a quantum technology company, is developing novel 3D imaging tools to support the design and manufacturing of semiconductors and batteries. Our technology addresses a critical gap in the semiconductor and energy storage industries, visualizing sub-surface currents with precision and speed, where today’s inspection and test tools cannot reach.

What problems are you solving?

The insatiable compute demand of AI is driving semiconductor logic, memory and advanced packaging technologies to adopt complex 3D architectures. New metrology and inspection tools are needed to control and optimize increasingly complex manufacturing workflows. Global demand for advanced metrology and inspection tools exceeds $10 billion annually and is growing rapidly with the adoption of 3D architectures.

Metrology plays a crucial role in semiconductor manufacturing by providing detailed information on the physical properties of silicon and packages. Process engineers make control adjustments to meet specific product parameters, ensuring the production of reliable semiconductor devices of high quality while minimizing waste. Effective metrology is therefore essential for maintaining the economic viability and sustainability of the overall manufacturing process.

EuQlid’s proprietary quantum 3D imaging platform, Qu-MRITM, enables non-destructive mapping of buried current flow with precision and speed that are unmatched in the industry.

What application areas are your strongest?

The next era of semiconductor scaling will be driven by 3D heterogeneous integration (3DHI) and novel 3D logic and memory architectures. EuQlid’s 3D imaging platform meets or surpasses precision and speed requirements to enable measurement of sub-surface currents and thereby determine the integrity of buried and invisible device structures. The semiconductor industry today is valued at over $600B annually and heading to $1T+ by 2030. Inspection and metrology tools have always been an integral part of manufacturing, and demand continues to grow with the increasing complexity of manufacturing workflows.

Similarly, with the “electrification of everything” revolution, energy storage devices are undergoing significant innovation and growth, and will continue to do so for decades to come. Improving battery lifetime, safety and performance requires understanding exactly how and where degradation initiates and propagates. EuQlid’s magnetic imaging platform enables visualization of the spatial and temporal current heterogeneities key to battery health monitoring and charge estimation.

What keeps your customers up at night?

Semiconductor industry leaders like TSMC, Intel and Samsung spend tens of billions of dollars annually in advancing core semiconductor technology and building manufacturing facilities. World economies are dependent on their ability to manufacture and ship flawless semiconductor products. The complexity of these devices and manufacturing flows puts immense pressure on them to stay ahead of the game with best-in-class design and manufacturing tools. They rely on companies like EuQlid to innovate and provide the metrology tools needed to deliver their products.

What does the competitive landscape look like and how do you differentiate?

Metrology is adapting to meet the varied demands and integration techniques required by different 3DHI workflows. Technologies such as X-ray fluorescence (XRF), atomic force microscopy (AFM), ellipsometry, and white-light interferometry provide engineers with unprecedented precision and capabilities, but they also have their limitations. EuQlid is addressing the whitespace in buried interconnect opens, shorts and non-wet defect inspection for in-line metrology applications.

What new features/technology are you working on?

EuQlid is developing the full-stack Qu-MRI platform combining quantum magnetometry with advanced signal processing and machine learning to deliver buried electrical current maps with high-throughput and nano-amp sensitivity without physical contact or destructive cross-sectioning.

The technology platform is being used to analyze customer samples representing their tough problems which require innovative solutions going forward.

How do customers normally engage with your company?

Customers engage with us by reaching out directly through our academic and industry networks. They can also reach us online through our website (euqlid.io) or LinkedIn.

Also Read:

CEO Interview with Wilfred Gomes of Mueon Corporation

CEO Interview with Alex Demkov of La Luce Cristallina

CEO Interview with Dr. Bernie Malouin Founder of JetCool and VP of Flex Liquid Cooling


CEO Interview with Rodrigo Jaramillo of Circuify Semiconductors

CEO Interview with Rodrigo Jaramillo of Circuify Semiconductors
by Daniel Nenni on 11-01-2025 at 8:00 am

Rodrigo Jaramillo CEO, Circuify Semiconductors Nov 2025

With over 18 years of experience in the semiconductor industry, Rodrigo Jaramillo is the Co-Founder and CEO of Circuify Semiconductors, an engineering design solutions startup based in Guadalajara, Mexico. Circuify provides ASIC, SoC, and Chiplet design services for the North American semiconductor industry, with experience covering the full design flow from architecture to tape-out in advanced silicon nodes down to sub-5 nm and “More than Moore” technologies such as Chiplets, 2.5/3D integration, and advanced packaging.

Prior to founding Circuify, he was a Senior ASIC Design Engineer at AMD, where he worked on power consumption analysis for commercial microprocessors. Before that, he was an ASIC R&D Engineer with Intel Labs, developing experimental chips in pioneering silicon technologies with a focus on ultra-low power design and PVT variation challenges. He began his career at Intel as a Physical Design Engineer, where he led a design group for memory implementations in the server processor family.

Tell us about your company.

We are proudly the first entrepreneurial semiconductor solutions provider from Mexico, delivering chip and IP design services for the global high-tech industry.

Founded in 2017 in Guadalajara, Mexico, Circuify Semiconductors was established by a team of highly skilled industry experts with more than 100 combined years of hands-on experience in IP and IC design.

Over 50% of our executive and engineering teams hold Master’s or PhD degrees in Electronic Engineering, complemented by extensive real-world experience designing ICs and IPs for applications including High-Performance Computing, Artificial Intelligence (AI), Internet of Things (IoT), and Embedded Systems. Our expertise spans advanced silicon nodes, including FinFET technologies down to 5nm and below.

What problems are you solving?

Our mission extends well beyond delivering world-class chip and IP design projects. We are focused on building Mexico’s and Latin America’s semiconductor ecosystem as well as cultivating the next generation of engineering talent.

  1. Ecosystem Development: We are helping shape Guadalajara into the “Silicon Valley of Latin America.” The Mexican government has recognized our leadership in this effort and is collaborating with us to expand local infrastructure, education, and innovation capacity—with Circuify Semiconductors at the forefront of this critical mission.
  2. More than Moore technologies: Working with innovative and disruptive silicon startups on solutions in chiplets (RTL-to-GDSII), 2.5D and 3D integration including logic, cores and HBM phys, high-speed data transmission (die-to-dies), to meet the growing demands for performance, power efficiency and advanced physical sign-off requirements of advanced silicon process technologies.
  3. Leading-Edge Analog IP Development: In collaboration with select foundries, we are developing complex analog IPs for targeted customers, helping them differentiate their end solutions. This in-house IP strategy is a key differentiator for Circuify Semiconductors.
  4. Research & Development: We are engaged in multiple SoC and Analog-Mixed-Signal (AMS) R&D projects with partner universities and have published our work in IEEE and global industry conferences.
  5. Education & Integration: Through academic collaborations, we integrate real-world ASIC/SoC/Chiplet design into university programs, preparing students to meet the growing talent demand in Mexico’s semiconductor ecosystem, particularly in the Guadalajara’s hub.
What application areas are your strongest?

Our strongest capabilities lie in Chiplet, Design Functional Verification and Analog-Mixed-Signal (AMS) design, leveraging the latest industry-standard EDA tools and methodologies.

We are also a leader in Physical Design (RTL-to-GDSII), specializing in complex floor planning, timing closure, and full physical verification sign-off for sub-5nm projects.

We collaborate closely with foundries specializing in AMS technologies and are developing proprietary in-house IPs to bring further differentiation and value to our customers’ products.

What keeps your customers up at night?

For most of our clients, the biggest challenge is meeting aggressive development and verification schedules without compromising on quality or performance. Additionally, the exponentially increasing cost of design and tape-out at advanced nodes is a major concern. We mitigate this through an efficient and cost-effective operational model.

That’s where our flexible engagement model, deep technical expertise, and reliable delivery help them stay on track—and sleep better at night.

What does the competitive landscape look like, and how do you differentiate?

The global semiconductor services industry is highly competitive, but Circuify Semiconductors stands apart through a combination of technical depth, communication efficiency, and regional advantage.

We offer:

  • A unique IP development strategy that enables customers to differentiate their end products.
  • Fluent English communication and same-time-zone collaboration, ensuring seamless interaction with North American clients.
  • A world-class engineering team with experience at Intel, AMD, NXP, and other leading semiconductor companies.
  • A deep commitment to partnership — we don’t just deliver designs; we co-create solutions and invest in our clients’ success.
  • A mission-driven approach that empowers local talent and strengthens the semiconductor value chain in Mexico and Latin America.
What new features or technologies are you working on?

At Circuify Semiconductors, we are advancing complex Analog-Mixed-Signal (AMS) and next-generation digital design solutions. Current R&D areas include:

  • Chiplet architectures for heterogeneous integration
  • Custom AMS IP development for high-performance and low-power applications
  • Design automation and verification frameworks to accelerate time-to-market

More importantly, we see ourselves not just as a design services provider, but as a strategic innovation partner—helping our clients innovate faster.

How do customers normally engage with your company?

We work with three main categories of clients:

  1. Full Collaboration Partners: Companies that engage us early at the architecture level, enabling true co-design and system-level optimization from concept through tape-out.
  2. Block-Level Partners: Clients who rely on our expertise for specific IP blocks or subsystems within larger designs.
  3. Project Acceleration Clients: Companies that require specialized analog or mixed-signal engineers to help meet critical deadlines or overcome verification bottlenecks.

While we value all types of collaborations, our preference is Category 1, where early engagement allows us to contribute to system modeling, performance analysis, and design strategy—maximizing overall impact and project efficiency.

Also Read:

Podcast EP315: The Journey to Multi-Die and Chiplet Design with Robert Kruger of Synopsys

Podcast EP313: How proteanTecs Optimizes Production Test

Chiplets: Powering the Next Generation of AI Systems


Podcast EP315: The Journey to Multi-Die and Chiplet Design with Robert Kruger of Synopsys

Podcast EP315: The Journey to Multi-Die and Chiplet Design with Robert Kruger of Synopsys
by Daniel Nenni on 10-31-2025 at 10:00 am

Daniel is joined by Robert Kruger, product management director at Synopsys, where he oversees IP solutions for multi-die designs, including 2D, 3D, and 3.5D topologies. Throughout his career, Robert has held key roles in product marketing, business development, and roadmap planning at leading companies such as Intel, Broadcom, Nokia, and Altera. He brings extensive expertise in semiconductor technologies, including ASICs and FPGA products, as well as deep knowledge of specialized requirements across various sectors, including wireless infrastructure, military, automotive, industrial, and data center markets.

Dan explores emerging multi-die/chiplet design with Robert, who covers a wide range of topics. Robert discusses the market drivers for chiplets, both from a captive and open market perspective. He explains how markets will mature based on both business and technical needs. Roberts describes what the journey to a chiplet-based multi-die design approach looks like.

He discusses the value of IP subsystems and how they are built. Robert also covers the design and verification challenges associated with this new design approach and concludes with a summary of the capabilities Synopsys brings to the market to enable multi-die and chiplet-based solutions.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.


Intel to Compete with Broadcom and Marvell in the Lucrative ASIC Business

Intel to Compete with Broadcom and Marvell in the Lucrative ASIC Business
by Daniel Nenni on 10-31-2025 at 6:00 am

Lip Bu Tan Intel

The second chapter of our book “Fabless: The Transformation of Semiconductor Industry” describes the ASIC business and how important it is. That was more than 10 years ago and the ASIC business is still at the forefront of the Semiconductor industry and is a key enabler of the AI revolution we are experiencing today.

First let’s talk about the ASIC business then let’s talk about what Lip-Bu Tan said in his prepared statement on the most recent investor call about the new Intel Central Engineering Group and the ASIC and design services business.

Application-Specific Integrated Circuits are custom-designed semiconductors engineered for specific applications, delivering unmatched performance, power efficiency, and cost-effectiveness compared to general-purpose chips like CPUs or GPUs. ASICs are pivotal in high-volume markets such as artificial intelligence, high-performance computing, telecommunications, automotive, and consumer electronics. Unlike programmable devices, ASICs are optimized for specific tasks, enabling innovations like AI accelerators, 5G/6G infrastructure, and edge computing. The ASIC ecosystem thrives on collaboration between fabless design houses, foundries, and end-users, driving technological advancements.

As of 2025, the global ASIC market is valued at more than $20 billion and is expected to double in the next five years. Key growth drivers include surging demand for AI, edge computing, and advanced connectivity (5G/6G). Systems companies are now doing their own ASICs often times using an ASIC company to jump start internal chip design efforts. Apple’s first iPhone SoC used an ASIC service as did Google’s first TPU.

There are two basic types of ASIC companies, semiconductor companies like Broadcom and Marvell who also do ASICs and ASIC specific services companies like Alchip and AION Silicon who just do ASICs thus not competing with customers. Here are brief descriptions of the ASIC companies I know personally. Alchip and AOIN Silicon are current SemiWiki partners.

Broadcom Inc.

Broadcom is a semiconductor giant with a robust ASIC portfolio. It designs custom silicon for networking, storage, broadband, and AI, serving hyperscale data centers with tailored chipsets, such as accelerators for clients like Google. Broadcom’s ASIC business blends merchant silicon with bespoke designs, contributing significantly to its revenue. In Q2 2025, Broadcom reported record revenues, with custom ASIC segments achieving gross margins exceeding 50%. Its strength lies in AI leadership and diversified offerings.

Marvell Technology Inc.

Marvell specializes in data infrastructure semiconductors, with a growing focus on custom ASICs for AI, 5G, and cloud computing. Transitioning from storage controllers, Marvell now prioritizes high-speed, low-power SoCs and interconnects. Its Q2 FY2026 revenue surged 58% driven by ASIC demand from AI and networking sectors.  Partnering with leading foundries, Marvell is well-positioned for AI-driven growth, emphasizing scalable, high-performance silicon solutions.

Alchip Technologies

Taiwan-based Alchip, established in 2003 in Taipei, is a fabless ASIC leader specializing in HPC and AI. Renowned for rapid prototyping and first-silicon success, Alchip collaborates with tier-one cloud providers and TSMC, leveraging advanced nodes for machine learning accelerators and automotive chips. As a TSMC Value Chain Alliance member, Alchip offers end-to-end services, from SoC design to manufacturing, ensuring high-performance, low-latency solutions. Its 2025 focus on sustainable silicon design strengthens its competitive edge in AI and networking markets.

AION Silicon

AION Silicon, a lesser-known but emerging player, focuses on innovative ASIC solutions for AI and IoT applications. Based in the U.S., AION emphasizes customizable, high-efficiency chips for edge computing and smart devices. While smaller than Broadcom or Marvell, AION’s agile approach and partnerships with foundries position it for growth in niche markets. Its 2025 roadmap highlights low-power AI accelerators, targeting cost-sensitive applications.

Arm, Qualcomm, MediaTek and other chip companies have also joined the custom silicon business but that is another story. Now let’s talk about what Lip-Bu announced:

“By connecting our architectures through Nvidia NVLink, we combine Intel CPU and x86 leadership with Nvidia unmatched AI and accelerated computing strengths, unlocking innovative solutions that will deliver better customer experience and provide a beachhead for Intel in the leading AI platform of tomorrow. We need to continue to build on this momentum and capitalize on our position by improving our engineering and design execution. This includes hiring, promoting top architecture talents, as well as reimagining our core roadmap to ensure it is the best-in-class features. To accelerate this effort, we recently created the Central Engineering Group, which will unify our horizontal engineering functions to drive leverage across foundational IP development, test chip design, EDA tools, and design platforms. This new structure will eliminate duplications, improve time to decision-making, and enhance coherence across all product development.”

“In addition, and just as important, the group will spearhead the build-out of a new ASIC and design service business to deliver purpose-built silicon for a broad range of external customers. This will not only extend the reach of our core x86 IP, but also leverage our design strengths to deliver an array of solutions from general purpose to fixed-function computing.”

Bottom line: Brilliant move by Lip-Bu Tan! The ASIC business is critical but it is also VERY competitive. Rather than trying to compete with TSMC’s Value Chain Alliance or acquiring a large ASIC group (which is what Broadcom and Marvell did), Intel doing custom ASICs centered around Intel/Nvidia IP using Intel Foundry manufacturing and packaging is the right thing to do, absolutely.

Fill those fabs!

Also Read:

Yes Intel Should Go Private

AI Revives Chipmaking as Tech’s Core Engine

Advancing Semiconductor Design: Intel’s Foveros 2.5D Packaging Technology


Quadric: Revolutionizing Edge AI

Quadric: Revolutionizing Edge AI
by Daniel Nenni on 10-30-2025 at 10:00 am

Revolutionizing Edge AI SemiWiki Blog Image

In the rapidly evolving landscape of AI, Quadric stands out as a pioneering force in edge computing. Founded in 2018 and headquartered in Burlingame, California, Quadric is a technology company focused on developing high-performance, energy-efficient processors for AI workloads at the edge devices like smartphones, IoT sensors, autonomous vehicles, and industrial robots. Its flagship product, the Chimera processor, integrates the flexibility of general-purpose computing with the efficiency of specialized AI hardware, addressing the growing demand for on-device AI processing. This blog explores Quadric’s mission, technology, and impact on the edge AI ecosystem, highlighting its role in shaping the future of intelligent devices.

Quadric’s core innovation lies in its Chimera GPNPU, a hybrid processor that bridges the gap between traditional CPUs/GPUs and dedicated AI accelerators like TPUs. Unlike conventional neural processing units optimized solely for deep learning inference, the Chimera GPNPU combines a programmable architecture with specialized AI capabilities. This allows it to handle diverse workloads, including machine learning inference, signal processing, and classical computing tasks, all within a single licensable processor IP core. By unifying these functions, Quadric eliminates the need for multiple specialized processors, reducing complexity, power consumption, and cost—critical factors for edge devices where space and energy are constrained. For example, in autonomous vehicles, the Chimera can process real-time sensor data (e.g., LiDAR, radar) while running control algorithms, enabling faster and more efficient decision-making.

The Chimera’s architecture is a hybrid between a conventional C++ programmed DSP (the world’s largest and most capable, with up to 32,768 bits of parallelism) and hardware accelerator for convolutions and matrix math. It features a single instruction dispatch feeding into a massively matrix-parallel execution pipeline with up to 1024 of processing elements, optimized for matrix and vector operations common in neural networks. Unlike traditional GPUs that rely solely on sequential instruction pipelines, Quadric’s processor can switch into and out of two modes of execution, traditional linear code flow, or a dedicated matrix/convolution that executes operations in a dataflow-driven manner, minimizing latency and maximizing throughput. This hybrid of DSP behavior plus Accelerator behavior is what earned the architecture the Chimera brand name – a processor with the DNA of two very different architectures merged into one processor pipeline. This approach delivers up to 10x better performance-per-watt compared to competing solutions, according to Quadric’s benchmarks. Additionally, its software stack, including the Quadric SDK and Chimera graph compiler, allows developers to program in familiar frameworks like TensorFlow or PyTorch, ensuring compatibility with existing ML models while optimizing them for the Chimera’s unique architecture.  Critically, the processor runs both C++ user code as well as user python code making the Chimera core far more flexible that competing hardwired accelerators.

Quadric’s impact extends across industries. In healthcare, its processors enable wearable devices to perform real-time diagnostics, such as detecting irregular heart rhythms, without relying on cloud connectivity, thus enhancing privacy and responsiveness. In industrial IoT, Quadric-powered sensors can analyze vibration or temperature data on-site, reducing latency and bandwidth costs. The automotive sector benefits from its ability to handle complex perception tasks in self-driving cars, where low power and high reliability are paramount. By processing AI workloads locally, Quadric’s technology also addresses privacy concerns, as sensitive data no longer needs to be transmitted to centralized servers—a growing priority in a data-conscious world.

Bottom line: Quadric is poised to shape the future of edge AI as devices become smarter and more autonomous. Its emphasis on general-purpose AI processing aligns with the trend toward heterogeneous computing, where no single processor type dominates. By enabling efficient, on-device intelligence, Quadric not only enhances performance but also democratizes AI deployment across resource-constrained environments. As edge AI demand grows to an estimated $70 billion market by 2030, Quadric’s innovative approach positions it as a key player in making intelligent systems ubiquitous, from smart homes to autonomous factories.

 Visit Quadric Inc. for more information.

Ready to bring intelligence to the edge? Connect with a Quadric SME to explore your project.

Also Read:

Legacy IP Providers Struggle to Solve the NPU Dilemna

Recent AI Advances Underline Need to Futureproof Automotive AI

2025 Outlook with Veerbhan Kheterpal of Quadric