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Machine Learning with Prior Knowledge

Machine Learning with Prior Knowledge
by Bernard Murphy on 08-09-2018 at 7:00 am

I commented recently on limitations in deep learning (DL), one of which is the inability to incorporate prior knowledge, like basic laws of mathematics or physics. Typically, understanding in DL must be inferred from the training set, which in a general sense cannot practically cover prior knowledge. Indeed one of the selling points of DL is that it doesn’t need to be programmed with algorithms; intelligence is inferred entirely from these training sets through a form of optimization. This works well when the training set is large enough to cover the most important aspects of an objective but not so well when other variations are introduced, such as rotations or movement. That’s a rather big limitation.

The brute-force way to solve this problem is to expand the training to cover more variations. For rotations, instead of N training samples, perhaps you need 108*N to cover 3 axes of rotation and 36 orientations in each axis (0, 10, 20, … degrees). That’s a massive increase in the number of training samples you have to gather and label. For movement, how do you train ML to determine what will happen to all the other balls on a snooker table when you strike the cue ball? Using training to rediscover what Newton codified over 300 years ago seems like a huge waste of ingenuity.

The best way to handle these variants is to use prior knowledge in math and physics, combined with ML. In computer graphics we infer the impact of rotations on a view using algorithms based on math formulae. In the snooker example, we use Newton’s laws of motion, again encoded in algorithms. Those laws/algorithms capture in a few simple equations what would otherwise require perversely large training sets in the pursuit of algorithm-free recognition. So much for banishing algorithms.

One paper from Stanford uses an understanding of projectile mechanics to identify and track the path of a pillow thrown across a room. As far as I can tell, they model recognition in short segments of the path first, then use constraints to penalize complete paths which don’t follow the expected second-order equation of motion. In effect they are using a classical formula as a constraint in the structure of a neural net. This work shows some promise for learning in such contexts with only weak supervision.

Another interesting paper from the Institute of Science and Technology in Austria takes a different approach to build (through ML) models for safe operating conditions for robots (such as ranges of moving arms or legs) based on learning simple formulae from operations in a known-safe range. These formulae then allow extrapolations beyond the trained range. They describe this as “a machine learning method to accurately extrapolate to unseen situations”, in effect building its own prior knowledge in the form of simple linear equations through experiments in a more bounded space.

A third example from the Sorbonne University provides an illustration of forecasting sea-surface temperatures (SSTs). Surface temperature data is already generated through satellite imagery, providing vast amounts of current and historical information. Forecasting how this will develop requires evolving this data forward in time based on partial differential equations (PDEs) and is the basis for the standard approach to forecasting using numerical solution methods. This research team instead uses a CDNN with discretized version of the PDE equations to guide weighting in time-propagation in the net. Their work shows promising results in comparison with numerical methods and some other NN approaches.

So, two methods which reduce/discretize prior knowledge (physics) to mechanisms which fit into existing deep learning architectures through weighting and one which derives simple equations to form its own “prior” base of knowledge. Intriguing directions, though for me the Sorbonne approach seems the most extensible since almost all problems in physics can be reduced to PDEs (though I guess the geometry of present-day neural nets will limit application to 2 dimensions, plus time).


Enhancing Early Static FSM

Enhancing Early Static FSM
by Alex Tan on 08-08-2018 at 12:00 pm

Finite state machines (FSMs) are widely adopted as part of reactive systems to capture their dynamic behaviors using a limited number of modes or states that usually change according to the applied circumstances. Some terminologies are frequently used to describe the FSM characteristics: state, transition, condition and sequences. A state defines the behavior and may produce action or output; a transition describes change involving of state(s); a condition allows transition to occur; and a sequence is comprised of a set of two or more transitions.

FSM can be categorized in term of its output transition. A deterministic FSM, if it has only one transition to next state; while a non-deterministic FSM has more than one possible next state for each pair of current state and input vectors. For practical applications, FSMs can be grouped based on how their outputs are defined. Moore FSM is the state machine whose output are a function of the current state only, while a Mealy FSM has its output and next state dependent on both the current state and input(s).

Many of the FSM practical applications such as in communication systems, crypto-processing, visual processing and as part of the embedded controllers are implemented using various schemes, from a static to be more reconfigurable styles –depending on if it is internally initiated (self-reconfigurable) or driven by external reconfiguration events.

Aldec and Verification of FSM
As an industry leader in Electronic Design Verification, Aldec’s solutions include a verification strategy in ALINT-PRO™ that is comprised of three key elements: static structural verification, design constraints setup, and dynamic functional verification.

The first two steps are executed in ALINT-PRO, while dynamic checks are implemented via integration with Aldec’s simulators Riviera-PRO™ and Active-HDL™ (ModelSim® is supported) based on the automatically generated testbench.

Previously, designers had to deal with debugging the FSM late in the implementation stage such as by using Riviera-PRO advanced verification platform as illustrated in the following diagram:

“Most issues designers face when implementing FSM-based control blocks tend to be caught during RTL-signoff, using coverage-enabled simulation and/or formal property checking methods,” observes Sergei Zaychenko, Aldec Software Product Manager.

In response to the increasing verification challenges for complex designs, Aldec has expanded the rule-checking capabilities of its popular ALINT-PRO™ tool. it has enhanced the tool to include twice as many FSM checks and new graphical representations to aid with state explorations.

“Aldec ALINT-PRO can discover many complex FSM issues long before test stimuli are available. With the latest version of ALINT-PRO™ users can do FSM-level verifications that will save them a significant amount of verification time further on down the line,” added Sergei.

An early FSM static validation can be achieved with ALINT-PRO by taking a two-step approach: first by performing an FSM exploration using FSM graphical environment, and then by applying a complete list of FSM targeted rule checks. ALINT-PRO extracts FSM from a design code and presented in FSM viewer.

To facilitate a better exploration of the extracted FSMs and reveal FSM-based design issues, ALINT-PRO (v2018.07) has an enhanced GUI incorporating checks based on the 25 newly added FSM design rules covering advanced aspects and typical errors. The FSM window acts as the FSM debugging tool that generates state transition graph with color-coded notation signifying transitions among object states. It differentiates a deterministic, non-deterministic, beginning and ending state. Designer could trace a sequence and switch data representation mode from graph to tabular format.

FSM Static Checks and Coding Issues
An event-driven system programming tends to use heavily nested conditional constructs (if-else, switch-case) in order to implement various responses due to a triggering event or a combination of past events in the system. FSM adoption is intended to reduce potential clutters caused by the complex number execution paths, the multitude of variables and the many transitioning between different modes of execution.

ALINT-PRO identifies FSM related bugs including unreachable, deadlockand redundantstates which are the common types of shortcomings faced by designers while capturing the FSM RTL codes. An unreachablestate is not reachable from any initial state of the FSM but has output to transition; while a deadlockstate is reachable but once entered indefinitely unable to change its state; and a redundantstate has neither input or output transition from/to.

The FSM type compliance check can be targeted to a pre-defined set of requirements such as to satisfy two combinational and one sequential processes. Additional FSM implementation specific checks such as those related to reset control, FSM state enumeration, state encoding type allocation (binary, gray, onehot, etc.) and other FSM attributes declaration (e.g., fsm_encoding=…) are complementing the over 40 new rules designated for improving the VHDL and Verilog/SystemVerilog RTL coding quality.

To generate a highly reliable design, best-FSM-design-practice type of checks can also be applied. This includes good naming conventions (describing more than one FSM in a single design unit, unique names for states of different FSMs, etc.); FSM should recover in Reset state in case of FSM state variable corruption and use case default with unconditional transition to FSM reset state. Reset state transition handling is crucial such as in autonomous sequential modules of a complex digital system.

Workspace, Project and Heterogeneous Design
In ALINT-PRO environment, the RTL codes, constraints and properties are captured into workspace and projects. An enhanced setup automation for complex Xilinx Vivado and ISE projects is made in 2018.07 release. The extension enables a “push button” flow for early static verification of IP-intensive Xilinx FPGA-targeted designs. A workspace is automatically organized to deliver hierarchical and incremental DRC and CDC analysis, allowing the designer to concentrate on checking custom RTL blocks, while preserving accuracy at the boundaries of IP blocks. Unless an IP block is re-configured in the original design environment, it is only being analyzed once, and the extracted block-level timing constraints are automatically promoted to enable higher level verification of the main design.

To find out more about ALINT-PRO, please check HERE


Tesla Leap of Faith (or the Adoration of Elon Musk)

Tesla Leap of Faith (or the Adoration of Elon Musk)
by Roger C. Lanctot on 08-08-2018 at 7:00 am

The Reverend Elon Musk, CEO of Tesla Motors, held forth to his flock on yesterday’s earnings call. Musk described at length his efforts to lead the company out of production hell. The lengthy session highlighted the challenges facing the company, which posted its greatest quarterly loss ever, and was emblematic of the typical high-flying technology entrepreneur making a big bet against long odds.

Unique to Tesla, though, is the commitment it seeks from both investors and the drivers of its cars. In fact, Musk went so far as to insist that the media and analysts must commit more fully to the company’s vision for achieving mass electrified, sharable vehicle autonomy – or risk being described directly as idiots or worse.

He has no patience for scary headlines which tend to follow the relatively infrequent fatal crashes of Tesla vehicles. He confirmed on the call that the amount of recorded automated driving that occurs in autopilot-equipped Tesla vehicles tends to decline after such reports only to recover later. In Musk’s eyes, these discouraging downturns in autopilot usage only further delay the arrival of full autonomous operation – i.e. the promised land.

Musk also takes issue with the inclination of the press to blame-shame Tesla for pre-emptively releasing data implicating drivers in their own autopilot misadventures, fatal or otherwise. Musk did not mention the growing number of crashes (after all, there are more Tesla’s on the road), fatal and otherwise, that appear to be the result of autopilot shortcomings.

This is where the leap of faith is most difficult to take. Musk and Tesla were on solid ground two years ago (can it be that long?) following the fatal Florida crash. Tesla took multiple steps in response to that event including:

  • Parted with camera system supplier Mobileye
  • Laid blame for the crash upon a misuse of autopilot (on a non-limited access highway)
  • Updated autopilot software and geo-fenced its usability
  • Conducted a study of vehicle data – sharing the results with the National Highway Traffic Safety Administration – demonstrating that vehicle crashes were substantially reduced in Tesla’s equipped with autopilot

Ultimately, the scope of Tesla’s geo-fencing expanded such that it was nearly unlimited thereby completing the transition away from Mobileye. Still the system remains ill-suited to secondary roads and side streets with intersections.

Intermittent crashes continue including a fatal crash in California, once again blamed on driver inattention, along with non-fatal crashes with parked vehicles on highways. One crash stands out from the rest, though, having occurred shortly before the fatal Florida crash.

The crash occurred in China and Tesla was reportedly unable to retrieve the vehicle’s data logs due to the severity of the crash. As a result, the fatal China crash between a Tesla and a truck parked in the high speed lane of a highway, remains unresolved along with pending legal action from the family of the driver.

Given the fact that the China crash occurred before Tesla modified its automated driving system software, it is difficult to conclude whether any findings from that crash will be relevant to understanding how autopilot, as currently configured, functions today. More importantly, in spite of the availability of video from the vehicle, Tesla asserts that it is not possible to conclude that autopilot was operating at the time of the crash.

Infrequent though they may be, Tesla crashes continue to occur. Operating a Tesla in autopilot mode – and, in fact, investing in Tesla – requires a leap of faith. You have to believe in Tesla and Musk’s vision of autonomous operation.

Tesla has not been the only autonomous vehicle operator to experience a fatality. Uber suffered the same fate, though the fatality was a pedestrian not a passenger or driver. In the Uber crash in Tempe, Az., a number of factors were blamed including driver inattention and a malfunctioning or inactive automatic braking system. Some astute observers also noted that a thermal sensor might have aided detection of the pedestrian on the dark road.

Tesla famously makes use of ultrasonic, radar and camera sensors supported by Nvidia processors to analyze and fuse the incoming information and enable automated driving. Also famously, Musk disparages the use of Lidar sensors, which some believe might have prevented both the Florida and China fatal crashes.

An Israeli startup, BrightWay Vision, asserts that its image gating technology, for enhancing camera-based sensor inputs, might have also prevented the China crash. The gating technology might have been able to overcome what is thought to have been radar interference caused by the picket fence-like highway barrier on the left side of the vehicle.

The bottom line: To buy a Tesla or its stock or to operate a Tesla in autopilot mode is to take a leap of faith. It is a leap of faith in the gigafactory strategy, the fast charging network, SpaceX, increases in battery power density, reductions in cost, increases in production and the pursuit of profitability. It is a leap of faith in a CEO who sleeps on the factory floor and occasionally indulges in Tweet storms.

Mainly, it is a leap of faith that the best and most ethical decisions are being made regarding vehicle autonomy. If Musk were CEO of any other car company he would long ago have been crucified by investors, regulators and customers for the handful of fatalities that have occurred in Tesla vehicles. Musk spent a fair amount of time on Wednesday’s call apologizing for his rants and insults from the previous earnings call. What Musk really needs to do is thank his customers – especially those who have adopted autopilot – for their leap of faith.


Timing Closure Techniques for SOCs with Embedded FPGA Fabric

Timing Closure Techniques for SOCs with Embedded FPGA Fabric
by Tom Simon on 08-07-2018 at 12:00 pm

Once the benefits of using an embedded FPGA fabric are understood, the next question is about how timing closure is handled between the ASIC and the eFPGA blocks. First let’s look briefly at the advantages. By moving the eFPGA on to the SOC die, tons of I/O logic and the need for any package and board interconnect will vanish. Package and board routing create messy signal integrity and timing issues that require SerDes and bus protocols to tame. The added benefits also include reduced power – less logic to drive – and much lower latency. Instead of using a pair of SerDes, now the ASIC and eFPGA talk over direct wired signal nets.

While talking to Volkan Oktem, Achronix’s Senior Director of Product Applications, about the topic of timing closure with eFPGA I learned that there are two approaches for connecting the eFPGA to signals on the ASIC side. The easiest way is to use what they call “simple timing mode”, where there is a register on each net to help timing handoff at the eFPGA boundary. Of course, if you want to have the eFPGA output a signal off-chip, the SOC can include any necessary interfaces. But, the eFPGA can be thought of as just more logic – that just happens to be programmable.

In simple timing mode, the eFPGA and ASIC regions can be timed independently of each other. Constraints can be used in the eFPGA synthesis to ensure external timing meets spec. Then the ASIC just sees the eFPGA as a well-behaved block on the chip, like any other. For simulation, there is a gate level netlist with timing back annotation for the eFPGA so that top level timing can be verified.

If designers want to get rid of the extra clock cycle delay required by the intermediary registers, they can use the “advanced timing mode” which allows a direct connection from the ASIC logic to the input or outputs in the eFPGA. The catch is that the timing on these paths is now shared between the ASIC and the eFPGA. Achronix supplies a methodology that facilitates timing closure when using the advanced timing mode. First the user performs STA on the entire design, including the ASIC logic and the eFPGA logic. Next Achronix supplied scripts are used to extract the ASIC and eFPGA portions of all the nets that cross the boundary between the two parts of the design. Then these delays are passed as constraints to the ACE eFPGA tools so the eFPGA can be synthesized to meet timing. If there is more than one application for the eFPGA this process can be repeated for each.

After an iteration of the above process, designers can see if timing it met. If not, additional optimization or clock period adjustments can be made to close timing. While there is more effort required to use the advanced timing mode, it may well be worth it. Adding an eFPGA block to the floorplan otherwise is not much different than adding any other IP block. There are a few caveats, such as through routing is not allowed. So, placement of the eFPGA should take in to consideration the top level ASIC routing needs. There are no special supply or clock requirements.

An interesting side-note that came up in my conversation with Volkan was that for debug and test it is possible to program part of the eFPGA with special testers and debugging aids. This can help improve testability and visibility for the eFPGA and also the surrounding ASIC logic.

Volkan also pointed out that for some customers the goal is just to make a portion of an SOC programmable, adding for instance the flexibility being able to make post silicon logic changes. This affords the ability to refine and adapt functionality much later in the development process. However, he explained that sometimes their customer’s goal is to create special a purpose FPGA device, one that is tailor made for a specific application. This can have a number of advantages over off the shelf FPGA parts.

With a straightforward integration process, either with interface registers or through direct connection, the addition of programmability to an SOC design can be tremendously beneficial compared to off chip FPGAs or going without programmability altogether. Volkan has been working on developing new tools and documentation to make this process easy and efficient. There are resources on the Achronix website that go into much more detail and further explain clocking options and the timing closure process.


Timing Channel Attacks are Your Problem Too

Timing Channel Attacks are Your Problem Too
by Bernard Murphy on 08-07-2018 at 7:00 am

You’ve heard about Meltdown and Spectre and you know they’re really bad security bugs (in different ways). If you’ve dug deeper, you know that these problems are related to the speculative execution common in modern processors, and if you dug deeper still you may have learned that underlying both problems are exploits called timing side-channel attacks which depend on differences in timing between different operations, for example in retrieving data from a cache on a hit or miss. From there on for many of us, certainly for me, the details get a lot harder to follow.

But you probably thought (as I did) “this is a problem for the CPU guys, not my concern”. Bad news – you need to worry about this too. Timing channel exploits are not just for CPUs and caches. Timing exploits are possible through NoCs, in accelerators, between accelerators and their caches, pretty much anywhere an attacker might probe for hints to privileged information. We can’t just punt this to someone else; we need a deeper level of understanding.

So I talked to Jason Oberg, CEO of Tortuga, who has a PhD in timing channels; he managed to drag me through the basics. I say “drag” with feeling because just understanding the basics was hard; trying to reason about whether you have timing channel problems in a large design may earn you an extended stay in a sanitarium. They’re hard because this class of problem inherently spans multiple instructions and requires you to look at both software and hardware together. To see why, Jason shared a couple of the “easier” examples. These assume a victim process and an attacker process can run on the same system (under a VM OS for example).

First, think about a public-key cryptography system – could be in hardware or software. This depends on calculating a number to a power (the key) then taking the modulus of the result to some base. The most efficient standard way to do this uses a square-and-multiply algorithm, progressing over bits in the key. Square and multiply operations take different times and use of these operations differs for 0 and 1 bits in the key, therefore total time taken for the operation (if you have access to a sufficiently accurate clock) reveals the number of ‘1’ bits in the key. So start a timer, run the encryption, stop the timer and read the result. Since the key won’t change, repeat with multiple carefully-selected plain-text inputs, analyze the timing variations for these inputs and you can reconstruct the key one bit at a time.

The crypto-experts figured this out and one came up with a better algorithm called Montgomery’s ladder, which is immune to this kind of attack because it balances operation times for 0 and 1 bits. But then the experts found another way to force timing variations, through data retrieval times from the cache. Hang on to your hats – this is going to get complicated. One approach starts with something called a Prime and Probe attack. Before running the encryption test, the attacker primes the cache by filling with its own cache lines. Then the attacker times an encryption test, as before. Subsequently the attacker swaps back in and checks if any of the cache lines it preloaded have been evicted by the encryption. If they have, each such operation would have taken longer to execute in the encryption.

Now back to Montgomery’s ladder. This also steps through the key bitwise and performs different operations in each case depending on whether the bit is 0 or 1. But because of the Prime and Probe setup, now timing is sensitive to memory indexing from the ladder operation in the victim process and that indexing is still based on progressive bits in the key. From there you just continue to run analyses over multiple plain-text samples, analyzing the timing variations for these operations, from which you can ultimately extract the key.

Reminder – these are just examples; nothing about them is particularly restricted to CPUs, caches or encryption. Timing channel vulnerabilities can happen all over the place, as I mentioned earlier. And you can’t figure out where you might have such a problem without looking at hardware and software together. Formal and other standard security tools really can’t help. Even thinking about where you might have such problems can be difficult. You probably should talk to Tortuga who have a strong background in this domain and have built tools particularly around finding timing channel problems.


Cadence Update on AMS Design and Verification at #55DAC

Cadence Update on AMS Design and Verification at #55DAC
by Daniel Payne on 08-06-2018 at 12:00 pm

As a blogger in the EDA industry I get more invitations to meet with folks at DAC than I have time slots, so I have to be a bit selective in who I meet. When the folks at Cadence asked me to sit down and chat with Mladen Nizic I was intrigued because Mladen is so well-known in the AMS language area and he’s one of the authors of, The Mixed-Signal Methodology Guide: Advanced Methodology for AMS IP and SoC Design, Verification, and Implementation. You can buy this book at Amazon for just $115.00 and you’re sure to get a great ROI for the time spent reading it.


Prior to Cadence you find that Mladen worked at both Silvaco and Anacad, so he has a rich history in TCAD and circuit simulation tools.

Q: What are the trends with AMS simulation these days?

For AMS simulators we see that the performance always keep improving, from SPICE-level all the way up to digital. In my recent focus in AMS methodology, we are trying to leverage simulation to do better verification. Verification planning and managing your simulations for analog are now more important, because we need to be smart with simulation.

Model-based verification is becoming mainstream in Mixed-signal. Now with Real Number Modeling in Verilog and System Verilog designers are picking these languages. AMS modeling is a challenge, and it can be approached either top-down or bottom-up.

More engineers are becoming modeling specialists, as they know circuit design, CAD tools and verification approaches. They are asking themselves, what needs to be modeled?

Q: What are the challenges of modeling of AMS blocks?

To accurately model the characteristics of an analog block does require some circuit design understanding, so in most cases it takes a team to create a model, then compare the model against specs or other circuit results.

Q: Have AI or ML techniques been used much for AMS modeling?

ML may provide some help to automate the process of moving a transistor-level netlist up to a behavioral model.

Cadence has templates to help build models more quickly, and the designer needs to know how much detail and accuracy is really needed. It’s the classic benefits versus investment, so don’t over-model and don’t spend too much effort in creating models.

Q: Who on the team should be creating AMS models?

Well, forcing analog designers to do modeling may not work.

Analog designers are changing to adopt modeling in order to meet shorter time to market demands, and there is now more willingness to look at new methodologies.

Q: How should I go about learning AMS modeling?

There are Design Services for learning modeling, plus an IP team can deliver most AMS blocks requested. Training is also available, take a look at the standard courses from Cadence Education Services.

Q: What is happening on the language standards front?

We have both Verilog-AMS and SystemVerilog (getting Extensions to RNM) . Cadence is involved in standards committees and SystemVerilog AMS will become a standard in about 2020 and that process is under IEEE control.

Q: Is cloud-based EDA going to work this time?

In the cloud we see companies mixing and matching their simulation runs, both private and public clouds. Tasks that take the most time fit the cloud model quite well: library characterization, MC, validation or regression. All of the key apps are ready on the cloud today.

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Synopsys Offers First Single-Vendor Comprehensive Photonic IC Design Flow

Synopsys Offers First Single-Vendor Comprehensive Photonic IC Design Flow
by Daniel Nenni on 08-06-2018 at 7:00 am

Synopsys has a long history of being a thought leader and it’s not surprising to see the company jumping into the forefront of new technologies. For decades, I’ve been steeped in electronic IC design and it caught me by surprise to find that Synopsys had been quietly working on filling out their portfolio in the optical design solutions space. This first caught my attention with Synopsys’ 2014 acquisition of Brandenburg GmbH, who were known for their LucidShape product. LucidShape is used for design and simulation of automotive lighting systems. My assumption at the time was this was a move to help bolster Synopsys’ position in automotive markets.

What I didn’t realize was that Synopsys had already made two other acquisitions in the optical-space: Optical Research Associates (ORA) in 2010 and the RSoft Design Group (RSoft) in 2012. It turns out that Synopsys was already well on its way to building arguably the largest and most experienced optical design automation and services organization in the world. The ORA acquisition brought Synopsys decades of optical design experience (the company was originally founded in 1963), while the RSoft business, which released its first software package for the integrated optics industry in 1990, brought Synopsys into the realm of photonics and Photonic Integrated Circuits (PICs) with a full catalog of powerful optical system-level and device-level simulation tools.


Most recently, Synopsys acquired PhoeniX Software, a leading PIC and MEMS implementation tool provider. RSoft and PhoeniX also brought Synopsys decades of experience in photonic CAD and design, having their origins in the very early 1990’s.

In case you are wondering to what purpose Synopsys is doing this, I should note that the companies that now make up the Optical Solutions Group of Synopsys are already bringing in significant revenues. Strategically, this is just the beginning and it’s coming at just the right time. The IoT, 5G, big data, artificial intelligence, autonomous self-driving vehicles, and quantum computing are all on the cusp of exploding onto the market and they all have one thing in common: an insatiable need to be able to move and process huge amounts of data, further accelerating the need for optical data communication networks and data center infrastructure.

Therein lies an inflection point for Synopsys. Photonics (especially integrated photonics combined with integrated electronics) holds the promise of moving orders-of-magnitude more data at orders-of-magnitude faster speeds with — catch this — orders-of-magnitude less power! In less than a decade, Synopsys has brought in hundreds of person-years of optical experience and is marrying that experience with some of the best EDA tools in the industry.

With the PhoeniX acquisition, Synopsys has filled in an important technology gap and is now the first supplier to be able to offer a full front-to-back PIC design flow with all tools coming from one company. They can now address everything from system-level optical systems through fully integrated photonics on a chip, all from one company. No one else in the industry can offer this today. The obvious benefit to users is that you can expect the design flow to work well together and, if it doesn’t, there is no finger pointing back and forth between vendors. You have one company to hold accountable. On a more positive note, Synopsys is able to work all of the pieces to make for a better flow, which is important at the early stages of a technology when things are rapidly changing.

As a quick overview, consider the following PIC design flow from Synopsys:


Not only does Synopsys have the most complete photonics and optical solutions offering, but they also boast the most comprehensive PDK support for photonic foundries and package suppliers. Synopsys supports over 30 PDKs available on a variety of photonic platforms such as Indium Phosphide, Silicon, Silicon Nitride, Silicon Germanium, Polymers, etc. The tool flow also allows designers to add their own custom building blocks to any technology to take advantage of the best of both worlds (custom and pre-characterized PDK building blocks).

Consider also that photonic systems usually require some type of electronic control. Who better than Synopsys, with their strengths in EDA, IP, and software solutions, to combine these domains with photonics? New markets can take a while to sort themselves out. Photonics and how it combines with electronics will be no different, but with fast-growing markets like those already mentioned, and the technology Synopsys is bringing to bear, you can start to see a real powerhouse emerging for next-generation designs.
See also:

Synopsys Optical Solutions Group Home Page
Synopsys Driving the PIC Revolution Datasheet

A big thank you to my friend Mitch Heins of Synopsys for his contributions to this article.


Career Change Advice and how EDA Hiring has Changed

Career Change Advice and how EDA Hiring has Changed
by Mark Gilbert on 08-05-2018 at 7:00 am

I think most of us can attest that changing jobs is one of the most stressful decisions we make, as our careers progress. Making a job change is rarely an easy decision, though admittedly, so wonderful when it accomplishes your career and life goals. Having the right, well thought out expectations is the best way to ensure success, and not waste your or anyone else’s time. Here is the best way to approach a career change…

First, think of where you are now… is this position, the role you want, for the next several years? Is the team you work with, a team you enjoy working with? Do they make you feel good, comfortable about coming to work every day? Does the company have a product that interests you and are they doing well? Does their product work, scale and have longevity in the market? Do they treat their employees well? Are you looking for something different? What might that difference look like? It is these questions and more that should always be considered before making the decision to start looking or interviewing.

Once you have decided to start exploring, or perhaps follow up on a position that you just learned of, either through a friend or recruiter, make sure that you are prepared for all of the next steps. While your technical abilities will certainly make or break the outcome, there are other key preparations that can help you maximize your success through the process. One key ingredient to add to the formula, is the use of a highly specialized INDUSTRY recruiter. This one key ingredient can increase your chances of a great and lasting outcome. To start, a good recruiter will help you examine your reasons for wanting to make a career move. The right recruiter can prepare you, giving you insights into the process, as well as the dos and don’ts, and timing of what to say when, which should all help to ensure that you present yourself, in the best light.

A successful experienced recruiter will walk you through the interviewing process, using their own proven formula to prepare you each step of the way, further ensuring your chances of a successful outcome. Proper interviewing techniques is key to a good outcome, regardless of how good you are technically. More importantly, that recruiter, if they are good and have relationships with the hiring company, should do all the post-interview follow ups, on both sides, so that the process keeps moving forward.

Bottom line: getting hired in today’s job market is no easy task. Companies are more particular in who they hire, than ever before. The good news is, there are far fewer candidates looking so the pool is smaller, making your chances a little better. Companies want people that can make an immediate contribution. When applying, save yourself time by applying to things within your wheelhouse, and perhaps go out a few spokes. In the tech world we all play in, it is all about innovation and new approaches to problem solving. Know your strengths and play to them. Make sure your resume has all the key ingredients to excite and interest the person reading it. If your resume does not catch their eye, regardless of how good you are, you have no chance of getting the call.

In my next blog, I will cover some more good reasons for considering a career change as well as good tips for structuring a strong resume.


An update on the Design Productivity Gap

An update on the Design Productivity Gap
by Tom Dillinger on 08-03-2018 at 12:00 pm

Over a decade ago, a group of semiconductor industry experts published a landmark paper as part of the periodic updates to the International Technology Roadmap for Semiconductors, or ITRS for short (link). The ITRS identified a critical design productivity gap. The circuit capacity afforded by the Moore’s Law pace of technology advancement was growing faster than the capabilities of EDA tools and flows to support the associated design complexity. The figure below captures the ITRS projections at that time.

Note that the ITRS experts recognized the increasing influence of design IP (and its reuse) to help mitigate the gap. Nevertheless, this ITRS report served as a ‘call to action’ for the EDA industry to address methods to improve design productivity.

Fast-forwarding a decade, how has the landscape changed? Moore’s Law has continued to enable tremendous growth in circuit density, a testament to the expertise and ingenuity of fabrication engineers and equipment manufacturers. Note that this process technology evolution has been achieved without a reduction in reticle size, truly an amazing achievement.

Many EDA tools have been re-architected (and design models optimized) in support of multi-threaded (and in some cases, distributed) computation for very large datasets.

EDA platforms have been introduced, integrating analysis algorithms into implementation flows to improve optimization decisions, and thus overall design closure schedules. In support of these timing, noise, and power optimizations, the design model (and cell library model) complexity has grown – this adds to the stress on dataset size.

I was curious to know, “How has the industry progressed in closing the productivity gap? What are the areas where the gap remains?”

At the recent DAC55 in San Francisco, Cadence assembled a panel of industry and EDA experts to address the topic:

“Monster Chips – Scaling Digital Design Into the Next Decade”

The panel participants were:

 

  • Chuck Alpert, Senior S/W Group Director for Genus Synthesis, Cadence
  • Anthony Hill, Fellow and Director for Processor Technology, Texas Instruments
  • Antony Sebastine, Principal Engineer with the Systems Group, ARM
  • Anand Sethuraman, Senior Director, ASIC Products, Broadcom
  • Patrick Sproule, Director of Hardware, P&R Methodology, Nvidia Corp.

Here are some of the insights the panel shared – both acknowledging the strides made in addressing the design productivity gap and highlighting remaining challenges.

Advances
“The growing use of (multiple instances of) hard IP has required significant focus on macro placement. Automated macro placement in design blocks has improved significantly – routing congestion is reduced.”

“DRC throughput – especially approaching tapeout – is always time-critical. The (distributed) physical design verification tools have kept runtimes in check.”

“The ECO-based flows to close on timing issues have improved substantially.”

“The signal buffering and advanced layer selection algorithms in GigaOpt provide better physical implementations—of course, pre-route to post-route correlation is always a challenge.”

Challenges

“Design implementation capacity must be improved. The Quality of Results (QoR) for blocks greater than 2 million instances tends to degrade substantially.”


“Agreed. We are constrained to block sizes of 1M-3M instances to achieve suitable turnaround time and QoR. The design partitioning overhead in floorplanning and constraint management is cumbersome. We need to be able to support block sizes of 20M-30M instances to keep pace with the technology.”


“We are utilizing physical design servers with 40 processors and 768GB to 1TB memory, but the (multi-threaded) jobs are still limited in throughput.”

“A flow of increasing importance is the calculation of dynamic P/G grid IR voltage drop, and the impact on timing margins. The tools need to have the capacity to support activity-based analysis on very large networks.”

Expanding upon the last comment, the significance of dynamic voltage drop (DvD) on design closure was a common theme throughout the DAC conference, both in technical presentations and the EDA vendor exhibit floor. Current SoC designs commonly incorporate several features that increase the sensitivity of timing analysis calculations with DvD-based characteristics:

 

  • dynamic operation voltage domain optimization (DVFS)
  • non-linear cell and interconnect delay dependence upon (reduced) P/G voltages
  • (aggressive) library cell track allocation to the P/G rails

At advanced process nodes with aggressive voltage domain and power optimizations, static IR drop P/G analysis (with fixed cell characterization margins) will be increasingly problematic.

Summary

Chuck A. from Cadence offered a unique perspective to the comments from the other panel members. “Cadence wants to partner with design teams working on difficult blocks. We evaluate our implementation platform QoR on our internal testcases, but would benefit from a closer collaboration, to better understand the issues presented by specific designs.”

The takeaways from the discussion that I noted are:

Several EDA tool areas have made significant improvements in designer productivity and support larger dataset sizes – e.g., analysis-driven optimization algorithms, multi-threaded and distributed algorithms.

Nevertheless, designers are continuing to face the productivity gap identified a decade ago – support for block sizes of 20M-30M instances is required to keep pace with Moore’s Law. Specifically, physical design implementation flows require (academic and industry) research focus to be able to accommodate larger block sizes. Collaborative partnerships between (leading-edge) design teams and flow developers are required.

Patrick S. from TI reminded the audience that there will be an increasing demand to integrate reliability-based analysis algorithms into implementation platforms – e.g., EM, aging mechanisms. The goal would be to exit implementation and be ready for reliability sign-offmuch as EDA platforms strive for timing/noise signoff quality.

Alas, the EDA productivity gap is still present – a factor of 10X improvement in throughput is needed.

At DAC, I bumped into a professor colleague who lamented that EDA academic research funding was drying up, as there is a general perception that “all big EDA problems have been adequately addressed… the money is going to proposals associated with machine learning and AI.”In actuality, the challenges of efficient design data modeling, development of (tightly-correlated) optimization algorithms, and opportunities for improved (distributed) processing are more important than ever.

I guess you could consider this to be a 2018 version of the ITRS call to action.

-chipguy


Speak N Spell

Speak N Spell
by Daniel Nenni on 08-03-2018 at 7:00 am

This is the ninth in the series of “20 Questions with Wally Rhines”

Success has many authors and the Speak & Spell product from Texas Instruments generated lots of write-ups to demonstrate this. For most of the semiconductor industry, results of innovation were not apparent to the masses but, for the consumer electronics that emerged in the 1970s, the innovations were visible, exciting and fun. My job in the Consumer Products Group (CPG) was Engineering Manager with responsibility for the design and development of all the chips and plastic cases used in TI’s fledgling consumer business. In early 1977, almost all of CPG was moved from Dallas to Lubbock. From then on, we performed the logic design for our chips in Lubbock while the physical layout was done in Houston under the direction of K. Bala, an energetic, driving manager who was perfect for the task of juggling dozens of complex designs while competing for resources with TI’s traditional semiconductor business.


From left to right, Gene Frantz, Richard Wiggins, Paul Breedlove and Larry Brantingham

Paul Breedlove was in charge of product development for the “Consumer Calculator Division” which was managed by Jim Clardy (later CEO of Harris Semiconductor and then co-founder and CEO of Crystal Semiconductor (which ultimately became Cirrus Logic). Jim and Paul had a miserable job. Japanese manufacturers like Casio, Sharp, Toshiba and many more could design and manufacture great “four function” (add, subtract, multiply and divide) calculators for less than TI could. By late 1977, TI was reselling Toshiba four function calculators with a TI label because they were more profitable than our own. Paul kept searching for a differentiating alternative and he found it by attending one of the monthly “Research Reviews” that were held in the Central Research Laboratories (CRL) and open to TI employees from other parts of the company. At this particular review, Richard Wiggins presented the technology he was developing for speech synthesis. He was approaching a capability of producing understandable speech at a data rate of only 1000 bits per second. Paul was fascinated. Why not develop a product that took advantage of speech to differentiate, or augment, traditional consumer electronic products? Paul was helped along by the analogy of one of the few really profitable, successful consumer calculators called “The Little Professor” which was an arithmetic learning aid for children. Every year we expected revenue for the Little Professor to decline but it seemed to have a life of its own. We were beginning to realize that parents will pay any price to give their children an advantage in the education system.

As an experiment in innovation, TI had recently established a funding mechanism called the “Idea Program” where any employee could propose an idea for a product or technology and, if approved, receive $25,000 of funding to demonstrate feasibility. Paul submitted an Idea Program proposal (probably because the Consumer Calculator Department was really squeezed for funding) and Ralph Dosher, the CPG Controller, approved it. That’s when I became involved. Paul needed someone to figure out how to design chips that could be used in the product. Larry Brantingham worked in the Logic Design Branch of the Engineering Department I ran and he became the obvious choice.

Speech synthesis chips were under development at National Semiconductor and other companies but success was very limited because the current state of the art N-Channel MOS, or NMOS, technology was just too slow to achieve the needed performance for this computationally intense application. What is so remarkable about Speak ‘N Spell is that Larry didn’t use the higher performance NMOS technology but instead used the much slower P-Channel MOS, or PMOS. Why, you might ask? Very simple. Larry didn’t know how to design with NMOS. In addition, CPG was in a continuous battle with the Semiconductor Group over pricing of chips and Morris Chang, Semiconductor Group VP, became tired of all the arguments and settled the dispute by offering CPG a flat $25 price per two-inch wafer of PMOS, which was a five photomask process at that time. If Larry had learned how to design with NMOS, the program would have failed because the cost of NMOS wafers would have been too high. While the artificially subsidized price for PMOS made the cost feasible, the performance seemed much to slow.

Larry went to work with Richard Wiggins designing a pipelined multiplier in PMOS. Responsibility for the product was moved from Consumer Calculators to Specialty Products which was run by Kirk Pond (later CEO of Fairchild Semiconductor) because, although Consumer Calculators were struggling, the Specialty Products Divisions was struggling even more to find new product possibilities. Gene Frantz was enamored with the product and quickly became product manager, tasked with all the issues of choosing product features, name, marketing, etc. as well as managing the overall product development (Figure One)

Even more ridiculous than designing a pipelined multiplier for the synthesis chip was the task of designing read-only memory (ROM) chips big enough to store the pre-recorded speech vocabulary. When I presented the proposed chip design program to the TI Corporate Development Committee, Dean Toombs, head of R&D for the Semiconductor Group argued that the engineers in CPG had gone crazy. Semiconductor Group was struggling to produce the NMOS 2716 ROM at very low yields. If they couldn’t produce a 16K ROM, how could CPG design a 128K bit one? What Dean overlooked, however, was the fact that the TMS 2716 needed an access time of 450 nanoseconds while our speech chips could be dramatically slower. PMOS was also an older, more mature technology and was easier to produce than the highly advanced NMOS. So we received approval to go ahead and received corporate funding to develop a four-chip system with a synthesizer, controller and two 128K bit ROMs (Figure Two).

As the actual die size increased beyond the original estimates, the estimated cost of the chips increased. At one point, Kirk Pond threatened to kill the whole program because it was well known that $40 was a critical point for consumer products where both spouses had to approve the purchase. By the time Speak ‘N Spell was introduced, the suggested retail price was $60 and it sold so well that we quickly raised it to $65. Like the Little Professor, parents just couldn’t resist the purchase of an educational aid that would help their children spell, even though the synthesized speech sounded more like a robot than a human. Shortly after the introduction, we were invited to show the product on the Today Show, the most popular TV news program of the day. Charley Clough, our highly articulate and lovable head of Semiconductor Group sales walked Jane Pauley through the steps of using Speak ‘N Spell while Gene Frantz was behind stage with backup units since the reliability of our early production units wasn’t very good.

Speak & Spell took the world by storm and became a great story of corporate innovation. Not long after the introduction, I moved to Houston and took over the Microprocessor Division where we developed the TMS 320 single chip digital signal processor, or DSP. Although I was the only one who worked on both programs, there was at least a remote connection to the theme of digital signal processing in TI’s speech synthesis success. And DSP became the cornerstone of TI’s next wave of growth.

The 20 Questions with Wally Rhines Series