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Jeephack Repercussions

Jeephack Repercussions
by Roger C. Lanctot on 02-04-2019 at 7:00 am

Automotive cybersecurity is an intractable nightmare with significant though inchoate implications for consumers and existential exposure for auto makers. This reality became painfully clear earlier this month when the U.S. Supreme Court declined to hear FiatChrysler Automotive’s appeal in a class action lawsuit over allegations of vulnerabilities in its Jeeps and other trucks.

The case will go to trial in March.

At the core of the lawsuit, arising from the infamous 2015 so-called “Jeephack” orchestrated by Chris Valasek and Charlie Miller (now General Motors employees), is the issue of FCA’s liability and responsibility for the hack or future hacks. The litigation raises the question of whether truck buyers can sue over hypothetical future injuries without being actual victims of cybersecurity.

Approximately 200,000 FCA vehicle owners are parties to the class action and the penalty they are asking the court to apply is $2,000 per vehicle. Obviously that means FCA’s exposure in the litigation is potentially $400M. In reality, given that 1.4M vehicles are implicated in the alleged FCA vulnerability the actual exposure is $2.8B.

The consumers have said that, had the defects been disclosed, they never would have purchased the vehicles in the first place or would have paid less for them. They also said the defects reduce their vehicles’ resale value. A U.S. District judge certified the class action for claims of fraudulent concealment, unjust enrichment and violation of various state and federal consumer protection laws..

The significance of the lawsuit is that it quantifies the potential value of cybersecurity to the consumer at $2,000/car. It also suggests that large numbers of consumers are starting to care enough and understand enough about cybersecurity to take legal action where and when it is found to be wanting.

The action is the latest step in the process of the automotive industry coming to grips with the implications of cybersecurity. Every month brings word of yet another vehicle hack. Usually these “reveals” are accompanied by a description of the remedy being offered by the car maker – often in the form of a software update delivered either wirelessly to the car or during a dealer visit.

The cost of a dealer visit for a software update can be between $200 and $300. The lawsuit increases by tenfold the understanding of that financial exposure and elevates cybersecurity to a board-level concern for most auto makers. Members of the Auto-ISAC, which is coordinating the industry’s reaction to the cybersecurity dilemma, acknowledge a steady flow of reported hacking attempts of cars.

But, as an industry, we appear to be whistling past the graveyard.

The simultaneous announcements from car makers of hacks and fixes reflects the reality that most automotive hacks, of late, have been conducted by ethical or white hat hackers. Hackers working as individuals or as employees of organizations such as IOactive, Lab Mouse of Tencent’s Keen Labs have used automotive hacks to build their reputations and relationships with auto makers.

A wide range of cybersecurity suppliers have also used hacks of auto makers or their suppliers as “door openers.” Multiple automotive cybersecurity companies have hacked cars and components as part of educating auto makers to the scope of the cybersecurity problem.

The choreographed nature of these hack-fix announcements further reflects the limited preparedness of the industry. The pending lawsuit calls into question the adequacy of the existing process of consumer notification regarding vehicle vulnerabilities.

The reality is that cars may never be certifiably secure. In fact, it is known that car company’s enterprise operations have been hacked into via their connected cars and vice versa. Knowing that is enough to cause some lost sleep among senior auto executives while motivating others to elevate cybersecurity to a board-level responsibility.

The automotive industry has one of the most complex supply chains and is further compromised by its dependency on networks of franchise dealers. Add car sharing networks and autonomous vehicles into the mix and you have a gargantuan challenge.

If FCA can be sued on the grounds of potential vulnerability, successfully or not, the time has arrived to prioritize cybersecurity counter-measures. The challenge for auto makers is that consumers assume their vehicles are secure. The reality is that nearly any car can be hacked given enough time and determination on the part of the hacker.
The saving grace is that to-date most hacks have required significant time and effort including disassembly of vehicle systems and reverse engineering of firmware. It is also somehow reassuring that the potential opportunity derived from the hacking appears to boil down to vehicle or identity theft. Thus far terrorism remains nothing more than a boogeyman.

The onset of near-universal vehicle connectivity along with collision avoidance, self-parking and other automated driving features, demand better cybersecurity preparedness in the industry. As to whether a lack of preparedness exposes auto makers to billions of dollars in liability, the courts will decide. One thing is clear, the Supreme Court of the United States chose not to dismiss the lawsuit – so the entire industry will be paying attention this March.

Roger C. Lanctot is Director, Automotive Connected Mobility in the Global Automotive Practice at Strategy Analytics. Roger will be participating in the Future Networked Car Workshop, Feb. 7, at the Geneva Motor Show –https://www.itu.int/en/fnc/2019.

More details about Strategy Analytics can be found here: https://www.strategyanalytics.com/access-services/automotive#.


MENTOR at DVCON 2019

MENTOR at DVCON 2019
by Daniel Nenni on 02-04-2019 at 7:00 am

The semiconductor conference season has started out strong and the premier verification gathering is coming up at the end of this month. SemiWiki bloggers, myself included, will be at the conference covering verification so you don’t have to. Verification is consuming more and more of the design cycle so I expect this event to be well worth our time, absolutely. Mentor, of course is the premier verification company so first let’s see what they are up to:

Mentor, a Siemens Business will have experts presenting conference papers and posters, as well as hosting a luncheon, panel, workshop, and tutorial at DVCon 2019 February 25-28 in San Jose, CA. You’ll also find experts on the exhibit floor in booth #1005. Special guest Fram Akiki, VP Electronics Industry at Siemens PLM, will deliver Tuesday’s keynote “Thriving in the Age of Digitalization”.

KEYNOTE
Thriving in the Age of Digitalization
Tuesday, February 26, 1:30pm-2:30pm
Presented by Fram Akiki, Siemens PLM
Semiconductor technology continues its relentless advance with shrinking geometries and increased capacity stressing design and verification of today’s most demanding System on Chip solutions. While these challenges alone are significant, future challenges are rapidly expanding as market demand for Internet of Things, Automotive electronics and autonomous systems, 5G communication, Artificial Intelligence and Machine Learning technologies – and more – show explosive growth. These advances add significant complications and drive exponential growth in design and verification challenges of these solutions. This exponential development not only expands the market; it sparks new competitive pressures as new companies look to challenge the more established businesses that have long defined the industry. These factors explain why it’s important to have an integrated digitalization strategy to succeed in today’s semiconductor market.

SPONSORED LUNCHEON
A Tale of Two Technologies: ASIC & FPGA Functional Verification Trends
Tuesday, February 26, 12:00pm-1:15pm
The IC/ASIC market in the early- to mid-2000 timeframe underwent verification process growing pains to address increased design complexity. Similarly, due to increased complexity we find that today’s FPGA market is being forced to address its processes. What solutions are working? What separates successful projects from less successful ones? And how do you measure success anyway? At this luncheon we will address these and other questions. Please join Mentor, A Siemens Business as we explore the latest industry trends and what successful projects are doing to address growing complexity.

PANEL
Deep Learning –– Reshaping the Industry or Holding to the Status Quo?
Wednesday, February 27, 1:30pm-2:30pm
Participating Companies: Advanced Micro Devices, Babblelabs, Arm, Achronix Semiconductor, NVIDIA
Moderator Jean-Marie Brunet from Mentor, a Siemens Business, will take panelists through various scenarios to determine how AI and deep learning will reshape the semiconductor industry. They will look carefully at the chip design verification landscape to access whether it’s equipped to handle this new and potentially exciting area. Audience members will be encouraged to bring questions and opinions to ensure a lively and thought-provoking panel session.

WORKSHOP
It’s Been 24 Hours – Should I Kill My Formal Run?
Monday, February 25, 3:30-5:00pm
In this workshop we will show the steps you can take to make an informed decision to forge ahead, or cut your losses and regroup. Specifically, we will describe:

  • How you can set yourself up for success before you kick off the run by writing assertions, constraints, and cover properties in a “formal friendly” coding style
  • What types of logic in your DUT will likely lead to trouble (in particular, deep state space creators like counters and RAMs), and how to effectively handle them via non-destructive black boxing or remodeling
  • Matching the run-time multicore configuration and formal engine specifications to the available compute resources
  • Once the job(s) start, how to monitor the formal engines’ “health” in real time
  • Confirm the relevance of the logic “pulled in” by your constraints
  • Show how a secure mobile app can be employed to monitor formal runs when you are away from your workstation
  • Examine whether a run’s behavior is consistent with the expected alignment between the DUT’s structure and the formal engines’ algorithmic strengths
  • Leverage all of the above to make the final “continue or start over” decision

TUTORIAL
Nex Gen System Design and Verification for Transportation
Thursday, February 28, 8:30am-11:30am
In this tutorial, Mentor experts will demonstrate how to use these next-generation IC development practices to build and validate smarter, safer ICs. Specifically, it will look at:

  • How to use High-Level Synthesis (HLS) to accelerate the design of smarter IC’s
  • How to use emulation to provide a digital twin validation platform beyond just the IC
  • How to use develop functionally safe IC’s

CONFERENCE PAPERS
Tuesday, February 26, 3:00pm-4:30pm
5.1 UVM IEEE Shiny Object
5.3 Fun with UVM Sequences – Coding and Debugging

Wednesday, February 27, 10:00am-12:00pm
9.2 A Systematic Take on Addressing Dynamic CDC Verification Challenges
9.3 Using Modal Analysis to Increase Clock Domain Crossing (CDC) Analysis Efficiency and Accuracy
10.1 Unleashing Portable Stimulus Productivity with a PSS Reuse Strategy
10.2 Results Checking Strategies with the Accellera Portable Test & Stimulus Standard

Wednesday, February 27, 3:00pm-4:30pm
11.1 Supply Network Connectivity: An Imperative Part in Low Power Gate-level Verification
12.2 Formal Bug Hunting with “River Fishing” Techniques

EXHIBIT HALL – MENTOR BOOTH #1005
Mentor, a Siemens Business, has pioneered technology to close the design and verification gap to improve productivity and quality of results. Technologies include Catapult® High-Level Synthesis for C-level verification and PowerPro® for power analysis. Questa® for simulation, low-power, VIP, CDC, Formal and support for UVM and Portable Stimulus. Veloce® for hardware emulation and system of systems verification, unified with the Visualizer™ debug environment.

Join the Mentor booth theater sessions to watch technology experts discuss a broad range of topics including Portable Stimulus, emulation for AI designs, verification signoff with HLS, functional safety, accelerating SoC power analysis, and much more!

Theater sessions include:

  • Portable Stimulus from IP to SoC – Achieve More Verification with Questa inFact
  • Accelerate SoC Power, Veloce Strato – PowerPro
  • Exploring Veloce DFT and Fault Apps
  • Mentor Safe IC: ISO 26262 & IEC 61508 Functional Safety
  • Adding Determinism to Power in Early RTL Using Metrics
  • Scaling Acceleration Productivity beyond Hardware
  • Verification Signoff of HLS C++/SystemC Designs
  • An Emulation Strategy for AI and ML Designs
  • Advanced UVM Debugging

POSTER SESSIONS
Tuesday, February 26, 10:30am-12:00pm
Mentor experts will be representing the following poster sessions:

  • SystemC FMU for Verification of Advanced Driver Assistance Systems
  • Transaction Recording Anywhere Anytime
  • Multiplier-Adder-Converter Linear Piecewise Approximation for Low Power Graphics Applications
  • Verification of Accelerators in System Context
  • Introducing your Team to an IDE
  • Moving Beyond Assertions: An Innovative Approach to Low-power Checking using UPF Tcl Apps

DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored byAccellera Systems Initiative, an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies. In response to global interest, in addition to DVCon U.S., Accellera also sponsors events in China, Europe and India. For more information about Accellera, please visitwww.accellera.org. For more information about DVCon U.S., please visitwww.dvcon.org. Follow DVCon on Facebookhttps://www.facebook.com/DvCon or @dvcon_us on Twitter or to comment, please use #dvcon_us.


CES 2019 Stormy Weather for IBM

CES 2019 Stormy Weather for IBM
by Roger C. Lanctot on 02-03-2019 at 12:00 pm

Ginni Rometty, chairman, president and CEO of IBM was kind enough to take on the task of an hour-long keynote at CES 2019 in Las Vegas last week. She used the opportunity to highlight three areas of computational innovation at IBM – deep data, broad AI and quantum systems – with the help of three partners: Delta Airlines, Wal-Mart and Exxon Mobile.

CES 2019: CTA State of the Industry Address and IBM Keynote

Rometty proclaimed IBM’s advances in weather forecasting and the importance of building trust, transparency and security around data analytics. She also talked about the positive societal impacts of these technological advances and how artificial intelligence, while changing everything about how humans work in the future, will be a force for good.

Unfortunately, there were two big gaps in Rometty’s comments. Firstly, Rometty had nothing to say about the automotive industry – an industry where IBM is deeply embedded and invested and therefore implicated in the nearly 40,000 annual fatalities that occur on the nation’s highways. And, secondly, she had nothing to say about the Weather Channel’s alleged sharing of location data via its smartphone application which has 45M active monthly users.

Rometty correctly pointed out that IBM is not thought of as a consumer technology company, yet IBM underpins many if not most consumer interactions with technology on a daily basis. A week before her keynote at CES, the city of Los Angeles attorney filed a lawsuit claiming that the Weather Company, which is owned by IBM, “unfairly manipulated users into turning on location tracking by implying that the information would be used only to localize weather reports,” according to a report in the New York Times.

“Yet the company, which is owned by IBM, also used the data for unrelated commercial purposes, like targeted marketing and analysis for hedge funds, according to the lawsuit,” reported the Times. The lawsuit alleges a violation of California’s Unfair Competition Law.

(Two years before, IBM announced a partnership with General Motors to create a contextual marketing platform in GM vehicles to be called OnStar Go. The cooperation was announced at CES 2017, but by CES 2018 IBM had handed the opportunity over to a company called Xevo which now manages the application as the “GM Marketplace.”)

The report in the New York Times sounds like a sad tale of corporate malfeasance unlikely to end well for all involved. For its part, IBM has asserted its innocence.

For me, though, the bigger issue is the underlying question of weather and automotive safety. In Nate Silver’s “The Signal and the Noise: Why So Many Predictions Fail – but Some Don’t,” the author notes that weather is a rare area where prediction and forecasting has shown steady improvement in accuracy.

There is a lot of promise in weather forecasting and it may be for that reason that IBM acquired The Weather Channel in 2016. In fact, weather has become a contentious issue around enabling automated vehicle operation, with some analysts – including professors at Michigan State – suggesting that autonomous vehicles will never be able to overcome the challenges posed by weather.

Interestingly enough, a growing cadre of private weather researchers including Global Weather Corporation, Foreca, Weather Cloud, Weather Telematics and others are applying their analytic platforms to better understand and predict road surface conditions. These efforts are integrating data sources including roadside and on-vehicle sensors along with atmospheric indicators to enable automated vehicles to advise drivers when it may be necessary for a human operator to intervene.

IBM’s keynote focused on how IBM was integrating new weather data forecasting sources including inputs from airplanes to enhance the accuracy and granularity of global weather forecasts. The focus for IBM is its Global High-Resolution Atmospheric Forecasting System, or GRAF, which is using IBM supercomputers to aggregate data from millions of sources, including the smartphones of Weather Channel app users (on an opt-in basis). GRAF will be rolled out later this year, IBM says.

Clearly, the app is playing a role in the larger weather-related message for IBM. In an age of European Global Data Protection Regulation and California’s new privacy legislation, one would expect IBM to make sure it gets privacy and disclosure right.

Rometty told USAToday: “Your ATM doesn’t work without us, you can’t get an airline ticket without us, you cannot fill your car with gas without us, you (won’t have a) supply at Wal-mart without us. We really are underneath almost all of it.”

IBM wants and deserves credit for changing our lives every day – maybe even saving our lives and making our lives better. It is important, therefore, that IBM take on the most challenging and important tasks facing society and avoid the trivialities of potential legal violations via smartphone apps.

Better weather forecasts are a powerful value proposition – but accountability matters too. At a trade event dominated by personal transportation transformation, IBM was oddly silent on its contribution to resolving automotive safety issues and automated driving, in particular. How can the company solve these big challenges if it can get tripped up by an app-related end user disclosure?

Roger C. Lanctot is Director, Automotive Connected Mobility in the Global Automotive Practice at Strategy Analytics. Roger will be participating in the Future Networked Car Workshop, Feb. 7, at the Geneva Motor Show –https://www.itu.int/en/fnc/2019.

More details about Strategy Analytics can be found here: https://www.strategyanalytics.com/access-services/automotive#.


Open-Silicon SiFive and Customizable Configurable IP Subsystems

Open-Silicon SiFive and Customizable Configurable IP Subsystems
by Daniel Nenni on 02-01-2019 at 12:00 pm

After 8 SemiWiki years, 4,386 published blogs, and more than 25 million blog views, I can tell you that IP is the most read semiconductor topic, absolutely, and that trend continues. Another correlating trend (from IP Nest) is the semiconductor IP revenue increase in relation to the semiconductor market (minus memory) which more than doubled from 2006 to 2016 and is set to double again by 2026.

If you really want to know how important IP is ask an ASIC expert like Open-Silicon who specializes in chip differentiation by using customizable and configurable IP Subsystems. Here is a quick look at proprietary and third party IP that is an integral part of customizable system and physical design solutions offered by Open-Silicon:

By using an HBM2 IP Subsystem (controller + PHY + I/O), with silicon validation completed in TSMC’s FinFET and CoWoS technologies, customers can minimize the integration risk. Open-Silicon can also do a complete ASIC for you if time-to-market is a challenge.

Hybrid Memory Cube (HMC) is an innovative memory architecture in terms of performance, bandwidth, power efficiency, and reliability: 15x the performance of a DDR3 module, 70% less energy per bit than DDR3 DRAMs, and 90% less space than today’s RDIMMs.

Open-Silicon, a founding member of the Interlaken Alliance formed in 2007, launched the 8th generation of Interlaken IP core supporting up to 1.2 Tbps bandwidth. This high-speed chip-to-chip interface IP features an architecture that is fully flexible, configurable and scalable. Open-Silicon provides a complete Networking IP Subsystem which includes MAC IP + FlexE IP + PCS IP + MCMR FEC IP + Interlaken IP for ease of integration and as a one-stop solution to customers designing ASICs in TSMC FinFET technologies.

Investigating, evaluating, and integrating IP is rapidly becoming the biggest challenge of the SoC/ASIC industry. The success of a chip depends on the careful selection of reliable IP. Open-Silicon has a dedicated IP team that works with a wide variety of IP providers and is continually qualifying and ranking IP and updating a portfolio of recommended IP. The goal being to help you make informed IP decisions that differentiate your product, assure IP quality and reusability, and deliver first-time working silicon.

As you may have read Open-Silicon is now a SiFive company. It was a very disruptive move which greatly accelerated SiFive’s mission of becoming a fabless custom SoC powerhouse by leveraging Open-Silicon’s large customer base and ASIC implementation expertise.

The SiFive Tech Symposiums start this month in North America where you can spend time learning about the latest RISC-V offerings differentiated by customizable and configurable IP subsystems.

The RISC-V ISA has spawned a worldwide revolution in the semiconductor ecosystem by democratizing access to custom silicon with robust design platforms and custom accelerators. SiFive is fueling the momentum with myriad hardware and software tools for new and innovative RISC-V based solutions for IoT, AI, networking and storage applications. Attendance is free and includes lunch and plenty of time to meet and network with the speakers.

Mohit Gupta, SiFive Vice president of SoC IP, will be talking about all the offerings described above and more at the SiFive Tech Symposium at the Computer History Museum in Mountain View.

About Open-Silicon
Open-Silicon is a system-optimized ASIC solution provider that innovates at every stage of design to deliver fully tested IP, silicon and platforms. To learn more, please visit www.open-silicon.com

About SiFive
SiFive is the leading provider of market-ready processor core IP based on the RISC-V instruction set architecture. www.sifive.com

Also Read:

Ethernet Enhancements Enable Efficiencies

RISC-V End to End Solutions for HPC and Networking

A 2021 Summary of OpenFive


How to be Smart About DFT for AI Chips

How to be Smart About DFT for AI Chips
by Tom Simon on 01-31-2019 at 12:00 pm

We have entered the age of AI specific processors, where specialized silicon is being produced to tackle the compute needs of AI. Whether they use GPUs, embedded programmable logic or specialized CPUs, many AI chips are based on parallel processing. This makes sense because of the parallel nature of AI computing. As a result, in silicon for these applications we are seeing large numbers of replicated processing elements and distributed memories. These large AI designs fortunately lend themselves to advanced DFT solutions that can take advantage of their architectural characteristics.

Mentor has produced a white paper, titled “AI Chip DFT Techniques for Aggressive Time to Market”, that talks about how the properties of many large AI chips can be leveraged to save DFT, ATPG and test time. The first step they recommend is to take advantage of AI chip regularity. They propose doing test insertion and pattern generation/verification at the core level. Hierarchical DFT, like that found in Mentor’s Tessent, can use hierarchically nested cores that are already signed off for DFT to run DFT on the entire design from the top level. Higher level blocks can include blocks or cores that have already had DFT sign-off. These in turn can be signed off and used repeatedly within a chip.

Tessent’s IJTAG allows plug and play for core replication and integration. It also offers automation for chip-level DFT configuration and management. The flexibility this allows for some interesting optimizations. One such case is where there are a large number of very small cores. Mentor suggests using hierarchical grouping of cores for test to reduce overhead and save time. This is a happy middle ground between too granular and completely flat ATPG.

Another optimization that their approach allows is channel broadcasting. This allows the same test data to be used for identical groups of cores. It reduces test time and the number of pins required. Tessent is smart enough to help optimize the configuration for channel broadcasting.

In addition to repeating logic elements, AI chips have a large number of smaller distributed memory elements. If each memory core had its own BIST controller this would require a large area overhead. With Tessent it is possible for one BIST controller to be shared among multiple memory cores. To go along with this they offer a shared-bus interface to optimize the connections to the BIST controller.

Another topic the white paper covers is their move to RTL for test insertion. When this is used, it is possible to run test verification before the synthesis. RTL verification runs much faster than gate level verification. Also, the debug process is easier. Moving test debug and verification to the RTL level means that synthesis is not required each time a test fix is made. Mentor has also implemented a number of testability checks at RTL that can save down-steam iterations during ATPG.

While AI is making the lives of end users easier, it is certainly creating a demand for increasingly powerful silicon for processing. Despite this growing complexity of silicon, there is a bright spot in the test arena. Mentor clearly has been investing in their DFT product line. The good news is that many of the characteristics of these AI chips create opportunities for improving the efficiency of the design process and the resulting design, particularly in the area of test. If you want to delve into the specifics of how Mentor proposes designers take advantage of DFT optimizations for AI chips, the white paper is available on their website.


Secretary Chao Unchained @ CES 2020

Secretary Chao Unchained @ CES 2020
by Roger C. Lanctot on 01-31-2019 at 10:00 am

U.S. Department of Transportation Secretary Elaine Chao has agreed to mount the stage at the upcoming Consumer Electronics Show in Las Vegas to share her vision of the positive economic impact of technology unleashed from regulatory oversight. It’s a powerful message but it’s going to be a tough sell.

Chao is likely taking the keynote slot vacated by General Motors CEO Mary Barra in the wake of the catastrophic United Auto Workers strike which left dealer lots bare in time for Christmas and delayed plans for the company’s first electric pickup truck – at least according to official GM statements.

The front burner issue for Chao at CES 2020 will be enhanced vehicle safety from inter-vehicle (V2V) connections. To her credit Secretary Chao has carved out a technology agnostic stance on the issue which has conveniently left the door open for the Federal Communications Commission to pass a Notice of Proposed Rule Making (NPRM) last week re-allocating the 5.9GHz spectrum intended for V2V applications.

“The Commission proposes to designate the lower 45 megahertz of the band for unlicensed uses like Wi-Fi,” writes the FCC in its NPRM. “This 45 megahertz sub-band can be combined with existing unlicensed spectrum to provide cutting-edge high-throughput broadband applications on channels up to 160 megahertz wide.

“The Commission is proposing to dedicate the remaining 30 megahertz of the band for use by transportation and vehicle safety-related communication services. Specifically, in the NPRM, the Commission proposes to revise its rules to provide Cellular Vehicle to Everything (C-V2X), an emerging standard for transportation applications, with exclusive access to the upper 20 megahertz of the band.

“Under the Commission’s current rules, no spectrum is allocated for C-V2X. The NPRM seeks comment on whether to retain the remaining 10 megahertz for use by DSRC systems or to dedicate it for C-V2X use.”

If adopted, the FCC plan likely puts a fork in the plans of the National Highway Traffic Safety Administration’s efforts to mandate dedicated short range communication (DSRC) technology for the same application. This 20-year-old effort appears to have arrived at the end of the road – which one might imagine is welcome news at the Trump administration’s USDOT where regulations are being eliminated, not promulgated.

Just last week Chao released a statement that she had signed a “rule on rules” ensuring the department’s regulations aren’t “too complicated, out of date, or contradictory.” The new Transportation Department action formalized a Trump administration requirement that for each regulatory step a department takes, it must undertake two deregulatory moves.

News reports quoted USDOT claims that it had exceeded its own standard, establishing a ratio of 23 deregulatory steps for each regulatory initiative – estimating unspecified resulting industry savings of $3.7B. (The agency provided no details regarding the source of these savings or industries impacted.)

Maintaining that 23-1 ratio of deregulation to regulation may pose a challenge as the USDOT faces a growing clamor for more regulatory guidance in the development of self-driving cars and the advancement of active safety systems. Secretary Chao and the Trump administration may have painted themselves into a corner with the new mandate or simply written themselves out of the normal NHTSA script intended to reduce highway fatalities by guiding the future of automotive design.

Of course, the claim of a $3.7B contribution to industry savings from reduced regulatory oversight must be considered in the context of what is shaping up as a far more enduring industry impact from Trump administration policies as Boeing ponders the termination of 737 MAX production in January. With two fatal crashes occurring under the guidance of an acting USDOT secretary (preceding Secretary Chao), the Trump administration will have to come to terms with the $3.7B earnings hit Boeing took months ago to which $5B in victim compensation and liability has since been added to Boeings books.

Some have taken to describing the USDOTs deregulation binge as “win-ovation.” Nobody at Boeing in Chicago or Renton, Washington, would use such a word – especially as Boeing ponders what may be the demise of its most popular plane.

Maybe Secretary Chao can ask fellow CES keynoter Delta Airlines CEO Ed Bastian what he thinks about deregulation.


Qualcomm Attests Benefits of Mentor’s RealTime DRC for P&R

Qualcomm Attests Benefits of Mentor’s RealTime DRC for P&R
by Tom Simon on 01-31-2019 at 7:00 am

When floor planning (FP) and place & route (P&R) tools took over from custom layout tools for standard cell based designs, life became a lot better for designers of large digital chips. The beauty of the new flows was that all the internals of the standard cells and many IP blocks were hidden from view, lightening the load on the tools and designers. So-called footprints, in the form of Library Exchange Format (LEF) files, filled in for the internals of these cells and blocks.

A properly constructed LEF cell view is frequently adequate to give the P&R tool the ability to produce design rule correct final GDS level layout. But not always. Final DRC is always needed. As design sizes increased and the loop from final whole chip DRC to fixes and verification became unwieldy and not practical for highly sensitive chip design schedules.

This is the issue that Qualcomm encountered in their flow while designing extremely large state of the art SOCs. I recently had the chance to read a white paper that talks about the issues that Qualcomm encountered and how they solved them with Mentor’s Calibre RealTime Digital in-design DRC. Let’s look at the primary issues that they encountered.

LEF files contain an abstract of the underlying layout called a footprint. However, as the cells and blocks are placed in a design there are a large number of interactions that can take place between these cells that could lead to DRC violations. Waiting until late in the design cycle to verify all the base layer design rule correctness can leave serious issues baked into the design until they are much more difficult to fix.

The other source of issues are interactions between routing in the P&R tool and the geometry inside of the placed cells. A cause of this issue can be errors in the LEF cell views. In this case the errors might not be caught until the entire design is exported and merged with the contents of the placed cells. For large designs like those in development at Qualcomm, the chip level operation to merge all the geometry in the design can take a long time.

The white paper describes the process that Qualcomm adopted using Mentor’s Calibre RealTime Design solution. Instead of doing a merge of the entire design and running batch DRC, Calibre RealTime Digital makes direct calls to the Calibre engine running foundry qualified sign-off Calibre rule decks. It is able to run analysis on the area in proximity to where designers are working. It enables incremental DRC while in the P&R tool, including all the layout layers and nested cells and blocks that are normally not available from the P&R tool. As a result, designers get nearly instantaneous feedback on violations and feedback on potential fixes.

When geometry in inside placed cells is part of violation, selected shapes contained in the cells or blocks is shown to help designers fully understand the error, so a fix can quickly be made. This is really the best of both worlds, designers can still work efficiently in the P&R tool environment, yet they are able to detect and understand problems that arise due to the fully merged geometry and all layers.

It was years ago that Calibre completely disrupted the DRC market with the introduction of its easy to use and highly effective hierarchical capabilities. Customers immediately understood the competitive advantage that they would gain by using Calibre. The Calibre RealTime Digital interface looks to be another game changing capability to come from this formidable development team. Based on the white paper it seems that Qualcomm agrees with this sentiment.


The 50th Year of Intel, What Happened in 2018

The 50th Year of Intel, What Happened in 2018
by Daniel Payne on 01-30-2019 at 12:00 pm

2018 was the 50th year for Intel in the semiconductor business, and their Q4 2018 conference call just happened last week, so I’ll get you all caught up on what they talked about. Bob Swan is the CFO and interim CEO, as the company continues to search for a new CEO after Brian K. was ousted for misconduct. Here’s a quick financial summary for the Q4 2018 quarter:

  • EPS of $1.28, beat estimates by $0.06
  • Revenue of $18.66B, a 9.4% increase, but missed estimates by $360M

For the entire year revenue passed $70B, a growth of 13% thanks to data center, IoT, programmable, memory and modem businesses. I spend all day in the cloud by browsing, banking, reading, writing and networking, so no surprise that the Data Center Group did $23B in revenue, up 21% for the year.

I kind of expected the PC business to be flat or slightly down, but surprisingly that business grew 9% for the year. There was no big Q4 revenue uptick, so the product areas blamed are:

  • Modem
  • China slow-down
  • Slower cloud growth
  • NAND pricing

Hopes are high for three areas: AI, Autonomous Driving, 5G. All of these topics are popular on SemiWiki, so let’s see if Intel can compete on a global scale with so many competitors in each field.

Related blog:Intel Swaggers at CES

3D chip packaging (aka Foveros) has arrived, and their first product is coming later in 2019, Lakefield – a 10nm CPU, four Atom cores, Gen 11 graphics. I’m still curious about how they managed to remove all of that heat effectively.

The 9th generation of Intel Core desktop products was launched in 2018, so that benefits the scientific, gaming and content creating segments. The 10nm Ice Lake client CPUs were previewed, but not quite ready for sale in 2018.

Vision processing is a typical AI task using CNN (Convolutional Neural Networks), so Intel has a 3rd generation vision processing unit along with a toolkit called OpenVINO. Another tease for AI is something Intel calls a Neural Network Processor for Inference (NNPI), due in the 2H2019, with a product family name of Nervana.

Intel’s automotive acquisition Mobileye added some 28 new design wins and 78 vehicle model launches last year, so that segment for collision detection and avoidance is in growth mode for ADAS levels one to three.

Shareholders of INTC stock enjoyed receiving $5.5B in dividends, and the company bought back 217 million shares as the stock traded between $42 – $57.

One statistic that really jumped out at me was that revenue per employee has improved 25% in the past three years.

Just the Data Center Group at Intel produced $6B of revenue in Q4, more than most companies in the world.

Back in 2006 Intel and Micron created IM Flash Technologies, LLC, but in 2018 Micron announced their plans to fully own the technology known within Intel as 3D Xpoint, or product name of Optane. Intel can still purchase their chips from Micron, so let’s see if this segment continues to grow in 2019.

Forecasts for 2019 at Intel are:

  • Revenue of $71.5B,
  • EPS of $4.60

Q1 2019 forecast of $16B in revenue and EPS at $0.87, so no growth expected.

The transition at Intel from PC-centric to data-centric is slowly taking shape.

Data Center revenues for the first nine months of 2018 were up 45%, but the fourth quarter slowed way down. For 2019 they hope that the second half shows pickup in this area.

2018 we saw Intel exit Wind River and the wearables market. The 10nm node slowly continues to ramp up production volumes in 2019, although some 4 years later than expected.


Why High-End ML Hardware Goes Custom

Why High-End ML Hardware Goes Custom
by Bernard Murphy on 01-30-2019 at 7:00 am

In a hand-waving way it’s easy to answer why any hardware goes custom (ASIC): faster, lower power, more opportunity for differentiation, sometimes cost though price isn’t always a primary factor. But I wanted to do a bit better than hand-waving, especially because these ML hardware architectures can become pretty exotic, so I talked to Kurt Shuler, VP Marketing at Arteris IP, and I found a useful MIT tutorial paper on arXiv. Between these two sources, I think I have a better idea now.

Start with the ground reality. Arteris IP has a bunch of named customers doing ML-centric design, including for example Mobileye, Baidu, HiSilicon and NXP. Since they supply network on chip (NoC) solutions to those customers, they have to get some insight into the AI architectures that are being built today, particularly where those architectures are pushing the envelope. What they see and how they respond in their products is revealing.

I talked a bit about this in an earlier blog (On-Chip Networks at the Bleeding Edge of ML). There is still very active development, in CPUs and GPUs, around temporal architectures, primarily to drive performance – single instruction, multi-data (SIMD) fed into parallel banks of ALUs. More intriguing, there is rapidly-growing development around spatial architectures where specially-designed processing elements are arranged in a grid or some other topology. Data flows through the grid between processors, though flow is not necessarily restricted to neighbor to neighbor communication. The Google TPU is in this class; Kurt tells me he is seeing many more of this class of design appearing in his customer base.


Why prefer such strange structures? Surely the SIMD approach is simpler and more general-purpose? Neural net training provides a good example to support the spatial approach. In training, weights have to be updated iteratively through a hill-climbing optimization, aiming at maximizing a match to a target label (there are more complex examples, but this is good enough for here). Part of this generally requires a back-propagation step where certain values are passed backwards through the network to determined how much each weight influences the degree of mismatch (read here to get a more precise description).

Which means intermediate network values need to be stored to support that back-propagation. For performance and power you’ll want to cache data close to compute. Since processing is quite massively distributed, you need multiple levels of storage, with register file storage (perhaps 1kB) attached to each processing element, then layers of larger shared caches, and ultimately DRAM. The DRAM storage is often high-bandwidth memory, perhaps stacked on or next to the compute die.

Here it gets really interesting. The hardware goal is to optimize the architecture for performance and power for neural nets, not for general purpose compute. Strategies are based on operation ordering, eg minimizing update of weights or partial sums or minimizing size of local memory by providing methods to multicast data within the array. The outcome, at least here, is that the connectivity in an optimized array is probably not going to be homogenous, unlike a traditional systolic array. Which I’m guessing is why every reference I have seen assumes that the connectivity is NoC-based. Hence Arteris IP’s active involvement with so many design organizations working on ML accelerators.

More interesting still are architectures to support recurrent NNs (RNNs). Here the network needs to support feedback. An obvious way to do this is to connect the right -side of the mesh to the left-side forming (topologically) a 3D cylinder. You can then connect the top-side to the bottom-side, making (again topologically) a torus. Since Kurt tells me he hears about these topologies from a lot of customers, I’m guessing a lot of folks are building RNN accelerators. (If you’re concerned about how such structures are built in semiconductor processes, don’t be. These are topological equivalents, but the actual structure is still flat. Geometrically, feedback is still routed in the usual way.)

I see two significant takeaways from this:

  • Architecture is driven from top-level software goals and is more finely tuned to the NN objective than you will find in any traditional application processor or accelerator; under these circumstances, there is no one “best” architecture. Each team is going to optimize to their goals.
  • What defines these architecture topologies, almost more than anything else, is the interconnect. This has to be high-throughput, low-power, routing friendly and very highly configurable, down to routing-node by routing-node. There needs to be support for multicast, embedding local cache where needed and high-performance connectivity to high-bandwidth memory. And of course in implementation, designers need efficient tools to plan this network for optimal floorplan, congestion and timing across some very large designs.

I hope Kurt’s insights and my own voyage of discovery added a little more to your understanding of what’s happening in this highly-dynamic space. You can learn more about what Arteris IP is doing to support AI in these leading-edge ML design teams HERE. They certainly seem to be in a pretty unique position in this area.


Switch Design Signoff with IC Validator

Switch Design Signoff with IC Validator
by Alex Tan on 01-29-2019 at 12:00 pm

The surge of network traffic at the data centers has driven to an increase in network bandwidth, doubling every 12-15 months according to a study conducted on Google’s data centers. The primary drivers to this uptick include the proliferation of cloud computing, more distributed storage architecture, emerging applications in AI, 5G and video streamings.

Innovium is a provider of high performance and highly scalable switching silicon solutions for data centers. Its TERALYNXTM Ethernet Switch family supports switch capacity ranging from 3.2 Tbps through 12.8 Tbps with large buffers. Key to its network switch design requirements are the power efficiency in terms of performance per watt, a very low latency and inherently high port count connectivity. Innovium has rolled-out several generation of silicon starting with 28nm at 3.2Tbps and the most recent one in 16nm at 12.8Tbps. One of the main challenges to its silicon design is the need to reduce the physical verification time.

IC Validator™ is a comprehensive physical verification solution from Synopsys. It delivers both performance scalability and a broad runset support for advanced process nodes including 7nm FinFET. IC Validator’s Design Rule Checking (DRC) and Layout Versus Schematic (LVS) physical verification engine has near-linear scalability performance across hundreds of CPU cores and substantially reduces the time to results as shown in Figure 2.

Earlier this month, Synopsys announced Innovium adoption of IC Validator as its TERALYNX physical signoff tool. Innovium was able to take advantage of IC Validator’s performance scaling across 250 plus CPU cores to complete full-chip DRC/LVS signoff in TSMC 16 FinFET process within a day.

“Physical verification is on the critical path to our tapeout. Early physical verification closure is essential to ensure that design schedules are met,” said Keith Ring, vice president of Technology at Innovium. “IC Validator performance enabled us to complete full-chip DRC and LVS signoff within a day for our flagship network switch design.”

“Designers are challenged to close physical verification within schedule because of the increasing manufacturing complexity at advanced technology nodes,” said Christen Decoin, senior director of business development, Design Group at Synopsys. “Through high performance, scalability, and readily available optimized runsets from all major foundries, IC Validator is providing designers with the fastest path to production silicon.”

I had the opportunity to talk about this announcement with Manoz Palaparthi, Synopsys Technical Marketing Manager. The following is his excerpted responses to my inquiries:

What types of challenges that Innovium overcame by migrating to IC Validator physical signoff?
Performance was a key concern for Innovium. The design is large with several billions of transistors to verify. As such, the traditional full-chip DRC signoff happens late in the design flow and its long runtimes can lead to tapeout delays. With IC Validator, Innovium could complete full chip DRC and LVS runs under one day. Innovium used IC Validator across more than 250 CPU cores to take advantage of IC Validator’s distributed processing and scalability.

Which parts of IC Validator verification features being utilized by Innovium?
Innovium deployed IC Validator for all of their physical verification needs, including DRC, LVS, Antenna checks and metal-Fill.

Could you comment on how IC Validator smart memory-aware load scheduling and balancing technology work?
Yes. The memory aware scheduling and smart load sharing technologies are built into the IC Validator scheduler.

Memory aware scheduling enables jobs to be scheduled based on their individual memory requirements. IC Validator scheduler estimates memory needs in advance. If a job requires large memory, for example 512GB or 1TB, it is scheduled on a large machine. Lighter jobs are scheduled on smaller machines. And as the jobs progress, the tool dynamically adjusts and reschedules as needed. With smart load sharing technology, IC Validator continuously monitors jobs and dynamically optimizes them: are the jobs progressing well? Have some machines died? Is load balancing and rescheduling required from some jobs?

Once the jobs start running, scheduler ensures that jobs run as efficiently as possible. This technology, combined with massive distributed processing scalability, accelerates time to results for customers like Innovium.

IC Validator has evolved to a comprehensive physical signoff tool, could you comment on how you keep adding values to the tool?
The focus for IC Validator product is on delivering highest productivity to the physical verification engineer. In that direction, we recently introduced lot of technology to help our customers to get to their tapeouts faster: Massively parallel distributed processing with scalability to 1000s of CPUs, Explorer to quickly identify and fix gross design weaknesses during chip integration and fusion technology for automated DRC repair, timing aware metal fill and more.

For potential users who would like to migrate to IC Validator, could you share what the expected pre-adoption collaboration time?
Potential customers can migrate to IC Validator very quickly. IC Validator runsets are readily available for all mainstream process nodes from foundry partners such as TSMC, GF, Samsung and more.

After the runsets are ready, it is just a matter of few hours to setup the tool and start running PV jobs with IC Validator. Over the next few days/weeks, customers typically do runs with some designs to evaluate tool for performance and features. Several of our recent customers are able to deploy IC Validator in production within a month.

To find out more details on IC Validator, please check HERE