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20 Questions with Wally Rhines

20 Questions with Wally Rhines
by Daniel Nenni on 06-08-2018 at 12:00 pm
Categories: Wally Rhines

When I first started blogging in 2009 my sound byte was, “I blog for food” and the first lunch invitation I received was from Mentor Graphics CEO Wally Rhines, we have been friends ever since. Wally has an incredible mind with a memory to match, coupled with his charm and depth of experience I would easily say that Dr. Walden Rhines is the most interesting man in the semiconductor ecosystem, absolutely.

In this series of blogs I hope to capture Wally’s experience in enough detail to publish it as an autobiography. Hopefully the SemiWiki community will get involved and help with questions, comments, and critiques, for the greater good of the semiconductor ecosystem…

A Winding Path to the Semiconductor Industry

Gainesville, Florida in the 1950s was a small town of 25,000 people that doubled in size during the school year. There was almost no place to work except at the University so most of my peers had at least one PhD parent on the faculty. Competition was fierce as situations (like the daughter of the head of the Math Department competing with the son of the head of the Physics Department for top scores in high school courses) raised the level of intensity.

My father was a professor and a traditional engineer, as was his father so when it came to discussion of career choices, the conversation was short. “I think I might like to be a lawyer”, I might say. “Engineering is great preparation for law school”, my father would reply. Or, if I suggested the medical profession, there would be a similar answer. Variants of this discussion were followed by more than a dozen visits to the leading engineering schools in the U.S. until he concluded that the University of Michigan had the best undergraduate engineering program. And so, that’s where I went.

While my father was pleased with my decision to affiliate with the Chemical/Metallurgical Engineering program, he was less enthusiastic about the love I acquired for computers. Michigan was the first university to acquire an IBM 360 mainframe and had a close relationship with IBM. Bob Arden’s Math 273 course attracted a lot of people I came to know later, like Sam Fuller (later head of R&D at Digital Equipment and CTO at Analog Devices), David Liddle (Founder of Metaphor….) and Fred Gibbons (founder of the company that developed pfsWrite, the first widely accepted word processor for the TRS 80 and Apple computers). Math 273 required us to complete four computer projects including a program to execute the Newton/Raphson convergence approach to find functional values of zero for an equation; little did I know that this basic algorithm would be fundamental to all the SPICE simulations I ran in the years ahead.

Sam Fuller and I joined the same fraternity and embarked upon various contests to see whether our brains or our livers had greater endurance. At one point, we decided that sleep was just an escape mechanism so we decided to eliminate it, with less than beneficial consequences.

As graduation approached, the intensity of the Vietnam War increased. In February of our senior year, President Johnson announced an end to automatic deferments for graduate students unless they were married, which Sam was. Marriage struck me as much too extreme an alternative (since I didn’t know anyone I wanted to marry) but I managed to find a program that let me go on to grad school if I spent the summer at Fort Benning “pushing Georgia” with push-ups as my Drill Sargent yelled at me. Choice of a graduate school was a switch from my undergraduate experience. Getting into good graduate schools wasn’t that difficult so I only applied to Stanford and U.C. Berkeley. Previous fatherly advice of, “If you’re good enough to go to graduate school, you’re good enough to get someone else to pay for it”, came back to haunt him as he lobbied for U.C. Berkeley as the real engineering school rather than the “science oriented” Stanford. Graduate schools provided the funding back then so the choice was mine. Sam Fuller, who was number one in the Michigan Engineering class of 1968, was being recruited vigorously by MIT and Stanford so, after many beer-laden discussions, we concluded that Stanford was the place to go. We rented an apartment while Sam’s wife finished her degree at the University of Maryland and we entered the world of semiconductors and computers at Stanford. Sam chose Prof. McCluskey as an advisor. I chose Dave Stevenson, who was granted a major DARPA contract to investigate III-V compounds.

Craig Barrett, who was a traditional metallurgist, decided to diversify from his background and become involved in semiconductors. Dave’s contract was the perfect opportunity. So Craig joined my PhD committee, along with Gerald Pearson, one of the group that developed the transistor at Bell Labs. Craig was the closest thing that Stanford had to an expert in electron microscopy, so he dutifully helped me analyze precipitates that were formed during the diffusion of zinc into GaAs to form light emitting diodes. As I made my way to the end of the research, Prof. Pearson told me not to worry about a job. He would take care of it.

Sure enough, Pearson was good to his word. When I told him I was ready, he picked up the phone and called Morris Chang (one of his former graduate students) at Texas Instruments. He did the same for Shang-yi Chiang my fellow lab partner who had the same advisors and later became head of R&D for TSMC. We both went to TI to begin a career in the semiconductor world. A few months after I arrived at TI, Morris was promoted to manage the entire Semiconductor Group. That ultimately led to an association that I value to this day.

20 Questions with Wally Rhines Series

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When FPGA Design Looks More Like ASIC Design

When FPGA Design Looks More Like ASIC Design
by Bernard Murphy on 06-08-2018 at 7:00 am
Categories: EDA, FPGA, Synopsys

I am sure there are many FPGA designers who are quite content to rely on hardware vendor tools to define, check, implement and burn their FPGAs, and who prefer to test in-system to validate functionality. But that approach is unlikely to work when you’re building on the big SoC platforms – Zynq, Arria and even the big non-SoC devices. It would simply take too long to converge functionality and performance. As usual, expectations keep ramping up – 400MHz performance, shorter design cycles and more designs per year, driving more reuse but still needing to meet the same regulatory and/or safety requirements. Sounds a lot like ASIC/SoC demands (except for GHz speeds in ASIC). Unsurprisingly, FPGA designers are turning to similar flows to manage these demands.


The design steps should look very familiar: planning, IP verification, full design static and formal verification, simulation, synthesis, implementation and hardware debug. Like the ASIC folks you may want a second-source option, in which case this flow needs to be able to target multiple FPGA platforms.

Planning is common in both domains, but here it must be much more tightly tied to pre-silicon functional verification. If you have to signoff to DO-254, ISO 26262, IEC 61508 or other requirements, you already know you have to demonstrate traceability between testing and specs, and completeness of testing. Which means you need linkages and as much automated correlation as possible between documents, testing activities, bug tracking, testing coverage, static code compliance metrics, and so on.

Many FPGA designers are already familiar with static verification, an elaborated version of the linting of 15+ years ago. This is still a mainstay and a requirement in many FPGA flows (DO-254 for example mandates a set of coding-style rules). Equally important here are clock-domain crossing checks. A big FPGA may host 10 or more clock domains and 10k+ clock domain crossings. If you don’t use static analysis to find and check these, you face a lot of painful debug on the board. The better static checkers do a comprehensive job in finding all crossings, while reducing the cases you have to analyze to a digestible format.

Formal verification is a newer entrant in FPGA verification but is gaining ground for some fairly obvious reasons. One is getting to acceptable code coverage. All big designs have unreachable code – from disabled or forgotten functionality in legacy or 3[SUP]rd[/SUP]-party IP. You can’t hit this in testing no matter how hard you try, but it’s still going to damage your coverage metrics unless you flag the code to be excluded. That’s not always so easy, especially if you don’t know the code. Fortunately, there are formal methods which will search for unreachable code, and will automatically create those exclusion commands.

Formal adds more capabilities through “apps” for the formal novice, such as looking for inaccessible states in FSMs or design exploration apps which will help you probe characteristics of your design without need to setup complex testbenches. In general formal can be a very valuable complement to simulation, for what-if experiments and when you want to be sure something can never happen, say in a complex control system where multiple FSMs are interacting (that’s a topic for more advanced formal users, but remember this if you run into such a problem).

The heart of verification in these flows is still simulation, which has evolved a lot from earlier simulators. Now it has to be mixed language, Verilog, VHDL and SystemC, modeling all the way from TLM through RTL and gate-level. These are big designs running at least some level of software on ARM cores, so you need all the acceleration you can get through multi-core and other techniques.

For testbenches these days you should be looking at UVM along with (SystemVerilog) assertion support and management, because you should be using assertion-based verification anyway but also because your IP and VIP will be loaded with assertions. And your simulator should provide strong constrained-random support with an excellent constraint solver, since you’re going to depend heavily on this for coverage.

Something that may be new for some FPGA teams is the need for good VIP (verification IP) in your verification plan. A lot of what you will be testing with interacts with standard protocols – the many flavors of AMBA, PCIe, USB and so on through the alphabet soup. VIP provide proven models for the testbench to simulate traffic under many possible conditions. You’ll need these not only for testing functionality but also for performance testing. Will your design hold up under heavy traffic?

You also need a very good debugger, which now has to support protocol transaction views in addition to the traditional signal waveform kinds of view. You don’t have the time or probably the expertise to figure out what’s broken in a protocol at the signal level; the right place to start looking is at the transaction level. Incidentally you really need for the same debugger to support simulation, formal and static verification, for ease of learning certainly but also for integration between the different types of verification and coverage.

Finally, what can the flow vendor do to help you in post-silicon debug and better still, bring that debug data back for drill down in the flow you used to verify pre-silicon? Again the FPGA vendors provide logic analyzer capabilities here but likely not as well-integrated with the pre-silicon flow. So that’s consideration if you think you may need to do some tracing through the RTL. When looking for a debug solution it should be easy to use and integrate easily with the verification flows for quicker turnaround times.

The flow needs a good synthesis engine. Why not just use the FPGA tools synthesis? You can; naturally they understand their underlying architecture as well as anyone, so you can expect they will do a good job in optimizing your design to the hardware. But they’ll freely acknowledge that they don’t synthesize to competing platforms and they don’t have the depth and breadth in synthesis technologies that you’ll find in the big EDA companies. Which is why they work with those companies to enable those EDA tools to also optimize on their FPGA platforms with high QoR, advanced debug and deep verification.

I haven’t talked about any preferred solution in this blog; ultimately you should decide that for yourself. But I think I have described a reasonable checklist you might want to use to grade solutions. One possible solution is described in this webinar.

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Are memory makers colluding against China?

Are memory makers colluding against China?
by Robert Maire on 06-07-2018 at 12:00 pm
Categories: Foundries, Semiconductor Advisors, Semiconductor Services
5 Comments

Maybe OMEC is the new OPEC? A bargaining chip in June trade show down?

China has started an apparent investigation into pricing of DRAM memory with Samsung, Micron and SK Hynix as targets. We find this somewhat coincidental given the current trade issues. Memory pricing has been unusually strong for a very long time. Much longer than any previous period in the usually volatile memory market. The tight supply demand and therefore pricing in a normally volatile and less profitable memory market begs the question of whats going on?

Is it simply that memory makers have finally gotten intelligence and self control? Is next generation memory so hard to make that supplies are limited by technology? Or is it potentially a more nefarious reason like the collusion that China may be searching for?

If it is collusion, whats wrong with that? It may not be illegal or even wrong for memory makers to collude. Maybe not to set prices but maybe to set supply, which in turn will support pricing, much like the oil market.

The other, potentially more plausible answer is that China may be looking to preempt the trade showdown looming from the Trump administration on June 15th and June 30th.

If China can claim that the US and others are conspiring against it then perhaps they have more of a leg to stand on in trade issues. Maybe the investigation could be a bargaining chip to be bargained away in trade negotiations. Go easy on us or we will bust your companies for colluding against us.

There is also clear precedent of anti trust behavior in the DRAM market in the US. From 2002 to 2006 there were investigations and guilt found for violating violating the Sherman anti trust act in regard to DRAM pricing for Samsung, Micron and SK Hynix.

DRAM price fixing history link
Could this simply be history repeating itself? It could. The impact of the real truth behind memory makes a significant difference in the fortunes of the memory companies and trade issues.

Looking for leverage
It would seem clear that China wants leverage in coming trade talks and raising the specter of anti trust creates a FUD factor (fear uncertainty & doubt) that helps its position. Price collusion is very plausible given the industries history, so it appears to be very solid.

It is the timing that makes us suspicious but there is nothing that can be proven as it is a legitimate concern.

We would not be surprised to hear that the Chinese are dropping their price collusion investigation in return for some concession from the US and others.

What are other concessions that Chinese may ask for?
China already asks for, and gets, “technology sharing” on the part of the selling company. In other words the price of doing business in China is giving away some of your trade secrets to the customers and would be competitors. The trick is to give away useless information or nothing of true commercial value. Many companies in the tech space have made an art form of this. Seemingly giving away things without really doing so. Intel’s first foray into China was to locate a packaging factory which gave away little if any of the company’s true crown jewels.

Given the recent ZTE scare, China may push a lot harder to get access to real, true hard core leading edge technology to reduce dependency on the US and others. We are certain this is the case as ZTE made them painfully aware. Showcase and “make believe” technology sharing will likely not suffice any more.

Is OMEC the modern day OPEC???
Maybe the US and Korea (and Japan too for Toshiba) governments should get together and form OMEC (the organization of memory exporting countries). The reason that OPEC can collude is that “sovereign states” (not companies) are immune from Sherman anti-trust.

Maybe we don’t understand the power and leverage of producing memory.

If oil was the driver of the 20th century global economy through transportation then memory is the driver of the 21st century economy through “big data” and other data driven applications. They are both truly global commodities that are central and the life blood of new economies. China is a new economy that needs memory perhaps as much or more than it needs oil.

Ratcheting up the rhetoric
One of the problems we see is that both sides seem to be ratcheting up both rhetoric and ammo for some sort of trade show down. As we have said before, this could be a big game of chicken but it becomes harder to back down and unravel all the rhetoric and come to a reasonable accord. Much as was the case with the North Korean issue, we see no resolution in sight for the China trade issue. We would feel much better if there were a hint of progress but so far we don’t see it.

No collusion?
Like and Unlike presidential politics, there appears to be little evidence of collusion among DRAM makers other than the circumstantial evidence that prices remain high and supply remains low. As is the case in US politics, the facts never stopped anyone, as China could still indict any or all DRAM companies, as enemies of the state, with or without evidence and hold them hostage and linked to trade talks. After all it appeared that ZTE and its ongoing existence was being held hostage from China’s vantage point.

The stocks
We still are very concerned about both June 15th and June 30th as things are incrementally more complicated and ratcheted up in the past day given the DRAM collusion investigation. We still think semis and semi equipment are squarely in harms way in a trade war and this DRAM issue proves the point perfectly.

While over the longer run we see little impact on the stocks there is risk of companies giving too much away to China to “pay to play” in the Chinese market.

The short term risk in the stocks remains the headline risk in June which just got a bit worse.

We still like Microns stock, and if anything, this issue just serves to underscore the immense value in a memory supplier to the global economy. Both Samsung and Micron have already seen that value reflected in their earnings if not their respective stock prices. Micron’s stock remains especially cheap.

The semi equipment names remain at risk of being sucked into the vortex of the trade dispute as they have yet to be directly involved or called out by name. The first equipment company to get caught in the trade tussle will take down the entire group. It will not be good to be the test case. If we can get past the trade talks without semi equipment getting caught up it will be a minor miracle.

In the meantime we look forward to the Trump administration publicly saying that there was “no collusion” in DRAM pricing in response to China’s allegations…

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John Lee: Market Trends, Raising the Bar on Signoff

John Lee: Market Trends, Raising the Bar on Signoff
by Bernard Murphy on 06-07-2018 at 7:00 am
Categories: Ansys, Inc., Automotive, EDA, FinFET, Mobile

I talked to John Lee (GM of the ANSYS Semiconductor BU) recently about his views on market trends and the ANSYS big-picture theme for DAC 2018. He set the stage by saying he really liked Wally’s view on trends (see my blog on Wally’s keynote at U2U). John said these confirm what he is seeing – a trend to specialization, some around new applications like autonomous vehicles, some around traditional platforms like mobile and HPC and some around new technologies like 5G.


REMINDER: Make sure you register for your free I Love DAC pass by June 8th!

He noted some other trends, one to what he calls reaggregation, especially in moves for pure-play foundries to ramp up in-house ASIC services. Another is in system vendors getting close (or close again) to silicon: Cisco acquiring Leaba Semi, Amazon acquiring Annapoorna Labs, Bosch building their own foundry and Facebook and Google clearly being very active as judged by semiconductor design job postings in Indeed.com. In all cases, chip design activity is being driven increasingly by system companies who are seeing more advantage/differentiation in dedicated rather than general-purpose solutions.

In John’s view, these shifts are triggered by hot applications moving to more complex processes and packaging, and increasingly becoming sensitive to system-level design constraints. He cited for example automotive suppliers, traditionally very conservative on process but now moving to 7nm and already starting to engage at 5nm to integrate more complex compute (AI, 5G, imaging, …) onto silicon. For similar reasons, 3D packaging is picking up, in FPGAs, network, mobile and image sensors, all to scale beyond Moore’s law.

With these moves come more challenges, one being the sheer size of the design analysis task. To take one example in John’s domain, at 16nm a typical power grid might be modelled with a billion resistors; at 7nm you now have to handle 10-20B, up 1-2 orders of magnitude. The criticality of problems is also rising. FinFETs are driving higher current density into narrower interconnects and razor-thin voltage margins in these processes amplify risks in timing, yield and reliability.

John said that at 7nm they’re seeing breakdown in the standard approach to managing timing and voltage margins, judging by the calls they’ve had from a near full-house of high-end customers. These companies have told them that they are losing important yield to performance problems they thought were covered. They’re finding they need tighter timing accuracy near the margins than traditional variability methods can offer, but MC-SPICE just can’t handle the volume of paths that need to be checked.

Meanwhile, mobile and crypto-currency applications are pushing the power envelope even harder. In 5G, serdes frequencies run above 50GHz. At these frequencies noise-coupling is no longer simply capacitive; you also have to consider induction and you can’t limit analysis to nearest-neighbor only. Thermal effects become more important; between thermal and higher FinFET drive into thinner interconnect, EM risk goes up. And when you stack die, thermal problems increase, adding potential mechanical problems – warping between die and on the interposer.

The industry has developed a lot of good tools to attack these different concerns pointwise, for example PTSI for signal integrity, RedHawk for power integrity, Calibre for manufacturability and FX and RedHawk for reliability. However these tools are siloed, each excellent in its own domain if you can rely on margins to model inter-domain variability. That’s like modeling a problem in a box with margins as the sides of the box. You can analyze one problem really well inside that box, but the analysis can’t extend beyond the sides. This works well when the box completely surrounds the problem. But if you have to make the box really big to meet that goal, the design may not be viable – too expensive, too slow, too power-hungry or too unreliable. On the other hand, if you shrink the box to meet product specs, at least some behavior will spill beyond the edges of your analysis; you don’t even look at some realistic behaviors which could lead to failure.

At DAC, ANSYS is going to talk how to more completely analyze the problem space in all dimensions by removing the box, something they call “beyond signoff”. A reasonable approach must continue to depend on the learning already built-in to best-in-class tools, which means the solution needs to be open and extensible. It also must manage vast amounts of data from all of these tools to enable the kind of true multi-physics analytics common today in other domains, such as design for aircraft engines. This is only possible if you can leverage best-in-class technologies and computational sciences. And the solution needs to enable designers to innovate beyond the democratized processes, IPs and software platforms that we all have use, letting them build on their expertise to differentiate in power, performance, cost and reliability.

To learn more about what ANSYS plans for DAC 2018, click HERE.

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Being Intelligent about AI ASICs

Being Intelligent about AI ASICs
by Tom Simon on 06-06-2018 at 12:00 pm
Categories: AI, eSilicon, IP, Semiconductor Services
1 Comment

The progression from CPU to GPU, FPGA and then ASIC affords an increase in throughput and performance, but comes at the price of decreasing flexibility and generality. Like most new areas of endeavor in computing, artificial intelligence (AI) began with implementations based on CPU’s and software. And, as have so many other applications, it has moved up this chain to the optimal trade off point for both flexibility and performance. However, unlike cryptocurrency mining, AI utilizes constantly changing algorithms and architectures, which are often specific within a given application area.

AI when implemented for ADAS, search, VR, voice recognition, image analysis etc., calls for unique solutions in each space. The inability of a general-purpose ASIC to best handle a variety of applications has created a road block to the adoption of ASICs for AI. Yet, this leaves potentially huge gains in power efficiency and performance on the table. eSilicon just announced an offering they call neuASIC that promises to solve this problem and give developers of AI ASICs much more flexibility and a well thought out methodology for implementation. Before their official announcement at the Machine Learning and AI Developer’s Conference, I had a chance to talk with eSilicon’s Carlos Macián, Sr Director of Innovation, about their new approach.

The key insight driving this approach is that while there is a common notion of what an AI ASIC looks like, the parallel processing elements in the system are most likely to vary based on the application. There’s benefit to dividing the system up so there is a chassis consisting of IOs, data and control path interconnect, a CPU for control and internal and external memory. In addition, there is an array of AI tiles which have the AI neural network processing elements and their local memory. These AI tiles and the array that connects them are the most likely elements to change with new system requirements and new applications. Of course, the base elements may need to change too, but in general they will prove more durable and hence more reusable.

eSilicon is a pioneer in applying 2.5D technology to building efficient and high-performance designs. It comes as no surprise that they are using this technology to create their solution for AI based systems. They divide the design up into two parts, the AI core die and the ASIC Chassis die. The ASIC Chassis contains scratchpad memory, CPU, NoC based scalable control path, 3D data path interconnect, bus interfaces and external memory IOs. The AI core die consists of AI tiles custom designed for the AI application that the system is targeting. Together they go into a package along with HBM to create a full system for AI.

Designers are not left on their own to design each of the pieces. eSilicon provides their Chassis Builder software, AI tile cells and the IP for the ASIC Chassis itself. They offer Giga cells and Mega Cells that contain full AI subsystems and AI primitives respectively. Putting all this together they have everything needed to design and implement optimized ASICs for AI, and this offers the ability to modify select portions for future designs as algorithms and approaches change and improve.

They also have two very interesting pieces of IP that further help improve system performance. The first is their Word All Zero Power Saving memory. It offers 1RW (1 read or 1 write access per cycle) along with an 80% reduction in power. The power for all zero word read/write is 20% lower than WC read/write. This is useful with the sparse matrices used in AI. These benefits come with a very nominal 2% overhead (16Kx64) compared to conventional memory. The second is their Pseudo Four Port memory. They use a foundry 8T bit cell and perform 2 read and 2 write per cycle. They can be configured as 2R2W, 1R2W, and 2R1W multiport memories.

As AI becomes more prevalent in silicon design we are seeing an explosion of innovation in system implementation. While nobody is standing still – witness the GPU companies adapting their silicon to meet AI market needs – it’s interesting to see the synthesis of several technologies like 2.5D, advanced data/control paths, AI tile design, etc. used to create flexibility, improved turnaround time and better performance. eSilicon has a large team working on AI IP and system integration. The results look impressive. For more information on eSilicon’s neuASIC look at their website.

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SemiWiki and SmartDV on Verification IP

SemiWiki and SmartDV on Verification IP
by Daniel Nenni on 06-06-2018 at 7:00 am
Categories: IP, SmartDV

Bernard Murphy and I spent time with the SmartDV folks in preparation for the Design Automation Conference later this month. Bernard is an internationally recognized verification expert so his feedback is often sought after by emerging and leading verification companies, absolutely. Verification IP is a crowded market so it is very important to properly articulate the value proposition of your company and products, which is a focus of SemiWiki of course.

It is common practice in verification teams to get your VIP from two or more independent sources. The reasoning is fairly simple: since these VIPs were developed by independent teams in independent companies, they are less likely to make the same assumptions when interpreting ambiguous areas of the specification. As a result, whatever you don’t catch when testing with VIP A you may catch when testing with VIP B and vice-versa. Improved coverage, lower risk of false positives, less risk of IP failure.

If you buy IP from a big supplier or get it free, you likely get VIP as a part of the package; so that’s your first set. You could get the second set from another big supplier but for some of the reasons mentioned above you might want to go a different way. You may also get both sets of big-supplier VIP and still want a third option for at least one of those reasons. So who do you pick? There are a lot of VIP suppliers out there; it can be difficult to decide who stands out. Here’s a fairly obvious way to filter. The vendor should:

  • Provide a one-stop shop for all or most of your VIP needs – and one throat to choke if you have problems with the service.
  • Have a proven track record with multiple customers and demonstrated membership on all the appropriate standards committees.
  • Support multiple verification methodologies – UVM, OVM, Vera, e, SystemC, …
  • Support emulation-based and fpga-prototyping-based verification and, if possible, provide support for assertion-based verification for formal.
  • Have a local presence near you.
  • Be cost-effective.
  • And, ideally, support customization. After all, a second set of VIP doesn’t have to be limited to the same capabilities at the first set. Perhaps you can catch more or profile more comprehensively if your supplier is prepared to tweak the VIP.One of the leading VIP companies is SmartDV, based in Bangalore, who some consider the gold standard for VIP by these measures:[LIST=1]
  • They cover 150 protocols today, multiple each for MIPI, networking and SoC verification, automotive and serial bus, defense, AMBA protocols, storage and video. They also have models for multiple types of memory/memory interface.
  • They have 100+ customers across all major geographies. You’ll have to talk to them to get more information. I suspect they probably have close relationships with companies who also have offices in India. India is an IP hot spot for the semiconductor industry.
  • They have a compiler-based approach to generating their VIPs so they can quite easily target multiple methodologies including all the standard list.
  • They support a subset of protocol VIPs through transactor interfaces on all the main emulator and FPGA prototyping platforms
  • They have a sales office in San Jose, headquarters in Bangalore and distributors in Japan, China, Israel, Taiwan, Korea and Russia.
  • You’ll have to talk to them about cost but from what I hear they are very competitive.
  • This is an India-based organization so they’re very familiar with service-based engagements. They have a standard flow for this process.When we do these interviews the big question always is: What’s new? The answer from SmartDV is the addition of Design IP and IP creation services. This seems like a natural transition since SmartDV is already a trusted VIP provider, has a very cost competitive business model, and is based in India which is the semiconductor IP capital of the world. According to the 2018 Design IP Report the IP market should hit $6B in 2022 so this addition to the SmartDV business model represents a very big upside if approached properly. This brings us to the SmartDV IP approach, portfolio, and services:Approach:
    • IPs based on standard and custom protocol
    • Can be used in ASIC and FPGA based system
    • Verified using VIPs and test-benches which arelicensed by 100+ companies
    • Checked for Lint/ CDC violations, Synthesis, DFT
    • Extensive control and status registers
    • Package includes RTL code, elaborated data-book,synthesis script

    Portfolio:

    • MIPI RFFE master, slave
    • MIPI SPMI master, slave
    • MIPI I3C master, slave
    • MIPI CSI-2 Tx/ Rx
    • MIPI DSI Tx/ Rx
    • JESD204B/ JESD204C
    • LIN, CAN controller
    • PCI master, slave
    • SPI/ I2C/ SMBus/ MIPI BIF/ Smartcard slave
    • AC97/ MIL STD 1553 controller
    • 10/100/1000 MAC controller
    • SAE J2716 sensor
    • RapidIO Endpoint

    Services:

    • We have around 30+ engineers who havedone multiple design services projects.
    • Have designed custom design IP for bigcustomers.
    • Customized existing design IP as per customerspecific requirements
    • Have in-house protocol knowledge.
    • Have robust design flow.

    Event: Design Automation Conference 2018

    Event Dates: Monday, June 25, 2018 – Wednesday, June 27, 2018

    Floor Plan:     View Exhibitors Per Search | View This Exhibitor Only

    Exhibitor: Below you will find information found for selected exhibitor.

    Name: SmartDV Technologies

    Booth:    2313

    Company Description:
    SmartDV™ offers high quality standard and custom protocol Verification IP, Memory Models, Simulation Acceleration (Emulation) IP and Design IP covering MIPI, Networking, Video, Storage, Automotive and processor interfaces. The VIP and Design IP are licensed to over 120 world-wide customers including the industry’s leading semiconductor and system companies. SmartDV also offers ASIC and FPGA design and verification services with an emphasis on quality deliverables. SmartDV VIP are 2-4x faster to compile and simulate compared to our competition. http://www.smart-dv.com

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Imec technology forum 2018 – the future of memory

Imec technology forum 2018 – the future of memory
by Scotten Jones on 06-05-2018 at 12:00 pm
Categories: Events, FinFET, Foundries
1 Comment

At the Imec technology forum in Belgium Gouri Sankar Kar and Arnaud Furnemont presented memory and storage perspectives and I also got to interview Arnaud. Arnaud leads overall memory development at Imec and personally leads NAND and DNA research.

Memory research is focused on power, energy, speed and cost with energy and throughput presenting particular challenges.

In 2018 it is estimated that approximately 30 zetabytes of data will be generated, by 2020 it is expected that 50 zetabytes of data will be generated annually and in 2025 nearly 160 zetabytes annually.

Data center energy consumption is growing so rapidly that by 2030 data centers may use as much energy as Europe, Africa and much of Asia do today.

To-date Flash memory density has been keeping pace with the increases in data but with the transition to 3D NAND the log trend cannot be maintained. Energy and speed are far from keeping up with the data growth rate (see figure 1).


Figure 1. Growth rates for main memory roadmaps

SRAM and cache
For cache memory Imec is working on MRAM. STT MRAM can replace SRAM for L3 cache and shows an almost 80% reduction in energy. For L2 and below cache, where greater speed is needed Imec is working on spin orbit torque MRAM. MRAM can be formed in the interconnect layers over logic potentially reducing die area as well.

DRAM
Continued scaling of DRAM is becoming very difficult. DRAM storage capacitors used to have 20 to 25 fF of capacitance but today at the leading edge are down to 10 fF. This has required optimization of the bit line capacitance and correction code.

Roughly one half of a DRAM die is peripheral CMOS. Over the long term a move to high-k metal gates and FinFETs is expected to shrink the area.

Capacitor spacings are becoming so tight that cylinder capacitors with dielectric on the outside and in the center of the cylinder will give way to pillar capacitors with dielectric on the outside only due to spacing limitations. This change may make it possible to use thicker films of higher-k dielectrics. There is a fundamental trade-off between k value and leakage with the higher k films leaking more but a thicker layer could potentially overcome this and allow a different k value versus leakage optimization.

If a deposited thin film access transistor can be developed it may be possible to put the access transistor and capacitor over the peripheral CMOS increasing density.

Figure 2 illustrates the Imec DRAM roadmap.


Figure 2. DRAM Scaling Roadmap: Imec view

DRAM density scaling has slowed to ~1.1x per year.

NAND
2D NAND followed an exponential trend with a doubling in density per node but now 3D NAND will provide slower scaling as early double of layers becomes 1.5x and 1.33x layer increases per node.

3D NAND is transitioning to 4 bits per cell from 3 bits per cell. Peripheral CMOS under the memory array such as Intel-Micron is doing should become more prevalent but will require changes for Samsung and Toshiba who currently create epitaxial select transistors in the substrate.

String stacking has been implemented by Intel-Micron where one half of the memory array layers are put down, the channel is formed and then the second half is deposited, and the channel finished. Because Intel-Micron is a polysilicon-oxide stack that is difficult to etch they had to string stack first but Samsung and Toshiba will eventually need to string stack as well. Intel-micron may eventually need to move away from polysilicon-oxide stack based floating gate to charge traps cells based on oxide-nitride.

As the number of layers increases and the stack height grow the height of the vertical channel will require a change from polysilicon to silicon germanium and eventually III-V materials for lower resistance.

As the number of memory array layers increases the array thickness will approach the thickness of the die requiring careful stress control and optimized layer thicknesses.

Figure 3 illustrates Imec’s 3D NAND memory roadmap.

Figure 3. 3D NAND …. And Beyond


DNA
In the longer term Imec is investigating DNA for storage. DNA is very dense with >>1Tb/cm2 and in a 3D storage structure all the data in the world could fit in your car. DNA is very stable with biologists planning to bring back the woolly mammoth in 2019. Imec’s goal is to make it cost effective.

Conclusion
MRAM offers a lot of promise as a replacement for SRAM in cache applications. DRAM scaling is slowing and approaching fundamental limits. 3D NAND offers a NAND scaling path but will be slower than 2D NAND was delivering. In the long term DNA may offer the ultimate in archival storage density.

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Single-Chip Narrow-Band IoT

Single-Chip Narrow-Band IoT
by Bernard Murphy on 06-05-2018 at 7:00 am
Categories: Ceva, IoT, IP

Many factors go into building a competitive solution for the IoT, but few are as important for high-volume applications as low cost – not just chip cost but total system cost. If your customers are going to deploy thousands, tens of thousands or even millions of your devices in cities, factories, logistics applications, power grids or homes, products above ~$5 a piece are going to be a very hard sell. I’m not talking here about high-functionality user equipment with high-end sensor fusion, graphics and so on. I’m talking about the little devices that don’t need to do a lot, just a little data-gathering, compute and communication, and should run on a battery for 10+ years.

The trend here is no mobility (eg for parking meters or street lights) or very low mobility, with need to send only a few bytes periodically (how often do you need to be reminded “still working and still no car parked at this meter”?). Battery life is incredibly important; maintenance costs to replace batteries, even annually, could undermine the value of the solution. Compute isn’t going to be a big power factor so low-power communication becomes very important. That’s why the Narrow-Band IoT (NB-IoT) standard was developed – to provide a low-power, low-datarate cellular communication solution.

Compared to standard LTE at rates of mega-bits per second, NB-IoT only has to support ~100Kbps, using only a small fraction of the bandwidth. It also can run at much lower power and need only provide half-duplex support. The smaller bandwidth allows for a much smaller RF bill-of-materials (BOM), reduced power means that the RF and power amplifier can be integrated on the same die with the rest of the functionality, and half-duplex further reduces the RF BOM. Together this allows all the communication hardware to be integrated on one die, it provides long-range communication eliminating the need for gateways, and it is reasonable to expect a 10-year battery life.


So far I’ve just talked about the standard (NB-IoT, also known as Release 13, also known as LTE Cat-NB1) because there is an upcoming revision (eNB-IoT, also known as Release 14, also known as LTE Cat-NB2) which I’ll talk about more in a later blog (*). CEVA provides a product to support this standard in their Dragonfly NB1 solution IP. They’re an acknowledged leader in communication IP building on their core DSP strengths, so it’s no surprise that they’re all ready to serve this domain. The solution is built on their X1 core (interestingly designed after the X2, making it a prequel?) and includes digital front-end, RF transceiver, peripherals and software stack. So far, so good – CEVA is helping their customers stay current with evolving communications options.

Where this gets interesting is that the X1 has been designed to function effectively not just as a DSP (for communication) but also as a general-purpose CPU for this domain. X1 has been tuned to deliver competitive performance as a CPU, comparable to Cortex-M4 in Coremark, and provides (they tell me) a compiler-friendly architecture, large orthogonal register file, compact code, full RTOS support, fast context-switch and more. And while M4 provides some DSP instructions for comms support, DSP is CEVA’s home turf so they’re naturally stronger in that area. OK, so X1 has the capability to handle both communication SW and general-purpose software, but won’t it be bogged down in communication when active?

CEVA ran an interesting NB-IoT benchmark, looking at load on the X1 at a typical operating frequency. They found that nearly 50% of the time, the processor was idle. Of course this core can’t run Android and other big workloads, but it doesn’t have to (honestly, if you’re trying to run Android on an NB-IoT device, you have different problems). All you want is to run is some sensor fusion and fairly simple application software. Which it looks like the X1 has plenty of capacity to support.


And that’s just what CEVA wanted – a low-cost single-chip solution for NB-IoT, no need to add a separately licensed MCU core. In fact all you have to add to Dragonfly is embedded flash. They provide all the other logic/interfaces, including cache memory to reduce latency on memory accesses. And they provide all the software. So this solution really can get down to the low unit cost that NB-IoT solution providers need. Naturally they provide a reference solution for all of this.

Emmanuel Gresset (Director Biz Dev in the CEVA Wireless Unit) tells me CEVA believes this has a lot of potential as NB-IoT takes off. Right now, solutions are commonly based around a slim modem (one chip) from a major supplier, plus your own chip to handle your requirements. Bluetooth started with similar multichip solutions, however price-pressures forced integration. The same will happen, perhaps even more so, for NB-IoT apps where pricing expectations will likely be lower still. He added another fascinating point along similar lines. Providers really want to drive solution prices down to the $2-$2.50 range. To do this, they’re looking for ways to reduce stacked margins up and down the supply chain. Some system houses are now partnering with CEVA and ASIC shops to provide the content and expertise to build and manufacture their solutions. Yet another driver of disruption in the supply chain 😎.

You can learn more about Dragonfly-NB1 HERE. You might also want to register for an upcoming related webinar chaired by Daniel Nenni: Custom SoCs for Narrowband IoT (NB-IoT).

(*) Thanks to Emmanuel for corrections to the naming :p

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Is there anything in VLSI layout other than “pushing polygons”? (10)

Is there anything in VLSI layout other than “pushing polygons”? (10)
by Dan Clein on 06-04-2018 at 12:00 pm
Categories: EDA
2 Comments

The year is 2005 and PMC Sierra decided that it is time to expand by adding a new site in Bangalore, India. We started with digital verification first but by 2006 we were ready to engage with Mixed Signal Design and Layout. I went to Bangalore in June 2006 for the first time and with the help of our local manager, Vikram Labhe, had a few layout services companies come and present their competence. Started with Wipro, SiCon, then Smartplay and Sankalp. After 2 weeks of meetings and interviews I decided that the best bet for PMC was Sankalp. The main reason was that their growth plan was “organic from inside” without stealing people from other companies, fact of pride for the other contenders. I met the management team, Vivek Pawar, Mrinal Das, Alok Pugalia, Prabhat Agarval, and Mohan R. Their dream was to build a service company by taking new grads and train them into solid layout designers. More than that, they decided to build design services centers in second tier cities attached to second tier universities, which will raise the level of these locations and their population.

This was also a good business idea from the point of retention compare to big cities like Bangalore, Noida, etc. As a person who already trained a “few” generations of layout designers in different countries this was “music to my ears”. I visited Sankalp sites and got 2 bright people with little layout experience but a lot of enthusiasm. Now we wanted to grow our Bangalore PMC Sierra team but also the Sankalp team working with us. If I wanted to get more knowledgeable people for my team I had to get involved in their training. I started by reviewing Sankalp materials and decided that they needed help. I took my Cadence 5 days training course and made it 5 weeks for new grads. As the students already had electrical knowledge I had to adjust a few things but with the help of Sankalp future trainers we got the ball rolling. Using Mohan analog experience, Alok memory expertise and Prabhat IO and design knowledge we ended up with a great material that covers 2 months training.

For the next 5 years I had sessions with all new students on tools and methodologies, and yes long nights and SKYPE video were part of the norm… But the results were astonishing and we were able to pick up the best students for our PMC team. Using these updated materials and contributions from Vivek, Mrinal and other external advisors, Sankalp trained from 2007 until today more than 1200 new grads, so I consider my time “well spent”.

I wrote and delivered in the following years a few more training for Sankalp: a Train the Trainer for the teachers of the course, an Introduction to Management and Project Management for new leaders, and helped the soft skills teachers prepare a few other courses. Later in Sankalp we developed Project management with Puneet Pandey and a lot of soft skills materials with Shilpa HP and Bhuvaneshwari Shurpali, the trainer in ekLakshya. I visited India every 6 months and all my weekends were training classes for Sankalp employees, new grads or experienced. As I said before, training was and it is, one of my favourite activities even so it was for food and board 😊

In 2013 when PMC Sierra decided to ramp down the layout team in North America I had to look for something else interesting to do. As Sankalp was my account from 2007 I knew the management, the infrastructure and most of the people, around 500 at that time. I figured that I can rebuilt some of the layout capabilities in Canada but I needed help from a low cost & big size partner. The obvious option was to join Sankalp and start a Canadian office in Ottawa.

All good but I cannot do only management and business, needed to get back to the “fun” activities: tools, flows, mentoring and training. One of the activities I am very proud of started with Mohan R and Sati Patil, the only CAD guy in 2013. We wanted to improve Sankalp productivity and grow people interest in automation. So we put together a plan:

1. First Sati built an internal Central CAD website where we uploaded all possible training materials we could find. DAC proceedings, CDN Live papers, vendors tools manuals, white papers, etc.

2. We worked on specialised training materials for CAD people so we can grow the group, organic again. We developed a full ticketing system to ensure the voice of inventors and innovators is recorded and addressed. This work helped building a new breed of experts with scripting skills, not only layout or design. Today Sati has more than 40 people in automation…

3. We agreed that the biggest ROI for an internal automation is “migration”. A lot of customers came to Sankalp and asked for small modifications, derivatives of IP or just IP migration between processes in the same technology node or different.

4. We also wanted to solve another Sankalp reality: even so our trainees for all specialties were much better prepared than other new grads or juniors, all customers wanted people with 2+ years’ experience in their projects.

5. Based on my personal knowledge on “compaction & migration” tools (Rubicad, Sagantec, Magma, Qdesign (Cadence VLM), etc.) I knew that we cannot succeed where more money and better trained resources failed.

We decided to build a Platform (not a software) for IP Process Migration.

I worked with 3 people: Sati Patil for CAD, Sumit Bhat for Circuit Design and Uday Pendse for Layout. For about 1 month we had brainstorming sessions to figure out the flow and then decided to put everything in a “marketing presentation” so Mrinal Das can review and approve project development and budget. We had options and processes, efforts and schedules so once we got the green light the team hit the ground running.
Sankalp can migrate analog/full custom IP today (not digital standard cell blocks or memories) and we can also help the customer make decisions. While in PMC we asked service providers if our blocks are migrate-able and the answer was always “sure”. It most cases proved to be wrong so I wanted a feasibility gate in this migration platform.

What is Sankalp Migration platform : and entire environment that contains scripts, decision points, built around CADENCE software, verification tools and a lot of manual labour. Tools cannot solve more than 80% of technology design rules so we are using the 0-2 years’ experience juniors with a few experts to bring the results to 100% compliance DRC and LVS and performance. This way they get experience in various technologies, different designs, etc. which makes them better prepared for customer challenges and we have a new business offer.
The biggest novelty is the feasibility. We are able to provide of migrate-ability factors to each IP candidate for migration.
1. Simple design rules changes – no layout architecture change (generally for same node different vendors)

2. Design rules changes that will require some layout architecture changes – process node size difference (resistors, capacitors, inductors, etc., do not change linearly with process size)

3. There are design rules limitations that impact circuit design so a circuit modification will be needed including new simulations and ECO – the case of different type of devices not available in destination process – little circuit design and a lot of layout

4. The new process has many different device options, electromigration and RC variants, etc. – a lot of circuit design changes and a lot of layout work but the circuit can me modified

5. Non migrate-able – circuits with inductors, VCO, LNA, big process variation that will require redesign

We can provide all these 5 “migration factors” including effort estimation for each and if customer decides to give Sankalp the job, we can implemented all options internally. I am very happy with this new platform that has 2 years and was used in many engagements, some complete solution and some partial as automation is useful to reduce any design effort. Not only that but parts of this platform automation is used in a variety of projects to improve team productivity.

On the other front, slowly but surely I am working with some of my industry friends to my second edition of CMOS IC Layoutbook planned to bereleased by end of 2018!

The conclusion I want the readers to take home after these 10 articles:

If you are a layout designer who just entered in the industry and wonder what else you can do, look around. Opportunities are everywhere if you want to expand your knowledge, get engaged into other activities related or not to Layout (of polygons), and have fun.

Never wait for others to offer (give, teach) you to grow, go do it on your own, I did!

I started layout in 24 January 1984 and still have fun today!

If you have ideas and would like an advice my email is cometic@ieee.org

If you want to talk to me face to face please visit Sankalp Booth 2457 at DAC 2018 in San Francisco.

Dan Clein

Pushing Polygons Series

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Mentor Siemens Update 2018

Mentor Siemens Update 2018
by Daniel Nenni on 06-04-2018 at 7:00 am
Categories: EDA, Siemens EDA

As you know I am a big fan of disruption and the Siemens acquisition of Mentor is turning out to be one of my favorite EDA disruptions. At first it was a little bit perplexing but after one short year it makes complete sense.

Siemens is acquiring Mentor as part of its Vision 2020 concept to be the Benchmark for the New Industrial Age. It’s a perfect portfolio fit to further expand our digital leadership and set the pace in the industry,” said Joe Kaeser, President and CEO of Siemens AG.

Just a quick example: User groups are a great source of information and customer engagement. EDA has a long history of user group meetings and I have attended more than my fair share of them. Great content, free food, excellent networking, and free food. This week is the Siemens PLM Connection user led conference in Phoenix Arizona. Last year close to 3,000 people attended from all over the world and they expect even more this year. Mentor is now part of PLM Connection and will be presenting more than 50 of the 400+ sessions. After the American PLM Connection event there will be one in Russia, China, Japan and Europe. Compare this with the hundreds of people that attend the average EDA user group and you will see what I mean by EDA disruption.

If you haven’t read the Siemens Wikipedia page you should take a quick look. What an incredible 171 year history with a very strong position for the future. My favorite part is the acquisitions section, Siemens is not shy about acquisitions. Not listed yet are Solido, Sarakol, and Infolyitica which are mentioned in the video below. Solido of course was the absolute best EDA acquisition of 2017 according to me.

If you want a quick update on the CAD software side of Siemens here is an interesting video with Tony Hemmelgarn, President and CEO, Siemens PLM Software and Wally Rhines, President and CEO, Mentor, a Siemens business. It’s just under 12 minutes but for those of you who don’t like videos here is the my take on the Mentor part:

Wally first talked about the Mentor integration with Siemens. According to Wally, customers are excited. From what I have seen and heard customers are not just excited, they are now believers in the Siemens industrial automation vision. The great cultural blend was also mentioned and supported by low single digit employee turnover.

This year has been an all time growth record for Mentor and the momentum continues with synergistic system level product integration with Siemens. Growth was faster than possible than when they were a separate company for sure. Large customer renewals grew 32% relative to prior contracts in terms of annualized run rate with strength across all of Mentor products. Mentor also saw continued improvement in customer satisfaction (via a survey).

The strong semiconductor market has certainly helped Mentor but there is more to the story. Example: Since the acquisition, Mentor initiated and developed a new Calibre product for memories resulting in a $50M order from a leading memory manufacturer. Mentor has also regained the lead in emulation which, from what I have heard from the SoC companies, is correct.

Wally also talked about midterm EDA trends: shrinking and miniaturization, 7nm to 5nm to 3nm where Calibre is the gold standard for verification. AI has taken off with $900M in Q4 2017 investment. Mentor’s leading product Calypto allows companies to develop AI algorithms and synthesize them into silicon. IoT and industrial IoT is causing enormous growth bringing in new companies developing complex products that can serve as sensors and actuators for gateways and edge nodes. Growth of automotive in which Mentor has a large presence representing 20% of their revenue. With leading positions in infotainment, ADAS, embedded software, etc… and continued growth of the semiconductor industry as chip design moves to system design bringing together data from all aspects of design.

No matter how you look at it, this acquisition is one for the record books and will make a nice chapter in Wally’s best selling autobiography, absolutely.