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Podcast EP263: The Current and Future Impact of the CHIPS and Science Act with Sanjay Kumar

Podcast EP263: The Current and Future Impact of the CHIPS and Science Act with Sanjay Kumar
by Daniel Nenni on 11-29-2024 at 10:00 am

Dan is joined by Sanjay Kumar. Most recently, Sanjay was senior director at the Department of Commerce on the team implementing the CHIPS and Science Act. Before that, he was in the industry for more than 20 years, up and down the semiconductor value chain working at systems companies such as Meta, fabless companies such as Infineon, NXP, Broadcom and Omnivision and manufacturing companies such as Intel Foundry.

Sanjay provides a detailed analysis of the impact across the semiconductor value chain resulting from the CHIPS and Science Act. He details the significant industry investments that have resulted from the initial funding from the US Government.

Sanjay describes the collaboration between ecosystem companies and what the impact has been, and could be in the future. He discusses the impact AI has had as well. He describes possible future collaboration scenarios and the potential positive impact on the US semiconductor manufacturing sector.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.


CEO Interview: Dr. Yunji Corcoran of SMC Diode Solutions

CEO Interview: Dr. Yunji Corcoran of SMC Diode Solutions
by Daniel Nenni on 11-29-2024 at 6:00 am

Dr. Yunji Corcoran (1)

Dr. Yunji Corcoran is the Chairwoman and CEO of SMC Diode Solutions. Dr. Corcoran has managed a successful career in the power semiconductor field for over 30 years, specializing in design, manufacturing, and global sales. She holds a bachelor’s degree in physics from Nanjing University and a PhD in semiconductor materials from Stony Brook University in New York. She currently focuses on management functions but still considers herself to be a dedicated engineer. Outside of the semiconductor business, Dr. Corcoran is passionate about traveling, cooking, and collecting cookbooks from around the world.

Tell us about your company?
SMC Diode Solutions is an American-led semiconductor design and manufacturing company based in Nanjing, China.

Since the company’s founding in 1997, SMC has provided customers with high-quality products and timely delivery. SMC’s products have been designed with great attention to detail and performance while focusing on the needs of customers.

The SMC team designs and manufactures its own products that are widely distributed in global markets. SMC’s portfolio includes Silicon Carbide Schottky rectifiers and MOSFETs, Silicon Schottky rectifier diodes, ultrafast recovery rectifier diodes, TVS diodes, Schottky and rectifier modules, and many more.

What problems are you solving?
At SMC, we focus on solving two major problems: the first is power conversion and the other is efficiency. The function of the devices we produce is to convert the voltages, whether that’s from AC to DC, DC to DC or DC to AC. During the conversion, we ensure our products minimize the conversion loss while increasing efficiency.

What application areas are your strongest?
In general, we work with any market segment that has to do with power conversions and protections such as power supply, AC-DC and DC-DC converters, and inverters. We also create products for the aerospace, automotive, and medical industries. With the opening of our new fab in June 2024 and growth of our silicon carbide capacity, we are also growing our presence in the electrical vehicle and renewable energy markets.

What keeps your customers up at night?
I think the thing that keeps our customers up at night is exactly the same thing that keeps us up at night: how to survive in this very competitive market. In today’s market, you not only need to make great products that satisfy your customers’ needs, but you also need to be constantly researching, innovating, and striving to be better than your competitors. Our customers choose to work with us because they know they will receive good, quality products from us to in turn provide quality products to their customers. So, in short, the constant question and pressure of how to keep improving upon their products is what keeps our customers up at night. We have a strong focus on research and development at SMC, so I hope our dedication to creating better products helps to ease the pressure and concern our clients also face.

What does the competitive landscape look like and how do you differentiate?
The discrete power semiconductor market is a very competitive market, and there are quite a few players with very similar products. What makes SMC different is our unique products and services. From the initial design to manufacturing, we use the most advanced technology and software to create the best products possible. For example, our power diodes and MOSFET products have a lower power loss compared to our competitors which is a very important parameter for those types of products. Not only do our products perform well and have really great reliability, but we also bring a personal touch through our customer care. Our whole company is dedicated to providing a personal service to our customers, and we approach everything with flexibility and care.

What new features/technology are you working on?
As always, SMC’s focus is on our products. We pride ourselves on making quality products and delivering enhanced performance through technology innovations. Currently, we are working on expanding our products portfolio now that we have more than quadrupled our production capability with the recent opening of our new fab. We are also looking into extending our existing power module capability as the next step to strengthen our market position.

We’re excited about what’s to come and are continuously innovating and updating our products and product offerings. Our focus remains on our products and with growing interest in those, we will continue to grow our business and provide the best power product for our customers.

How do customers normally engage with your company?
As a company with a presence in the United States, Germany, China, and South Korea, we have distributors and clients all over the globe. You can contact our distributors or a local sales representative in your area for additional information about our company and products. Detailed contact information is on our website.

Additionally, more often than not, you will find someone from our company at any major semiconductor event. For general questions, feel free to contact us at sales@smc-diodes.com or check our website updates to see where you can find us next.

Also Read:

CEO Interview: Sandeep Kumar of L&T Semiconductor Technologies Ltd.

CEO Interview: Dr. Sakyasingha Dasgupta of EdgeCortix

CEO Interview: Bijan Kiani of Mach42


CEO Interview: Rajesh Vashist of SiTime

CEO Interview: Rajesh Vashist of SiTime
by Daniel Nenni on 11-28-2024 at 10:00 am

Fotosbyt/san jose

Rajesh Vashist is SiTime’s Chairman and Chief Executive Officer and has served in this role since September 2007. Prior to joining SiTime, Mr. Vashist served as CEO and chairman of the board of directors of Ikanos Communications, Inc., a semiconductor and software development company, from July 1999 to October 2006. Mr. Vashist led the organization from a two-person pre-revenue startup to a public company with 90% market share and a market value of $600M. Prior to Ikanos, Mr. Vashist served as a general manager of a $450M business unit at Adaptec, a storage company, and held various general management and marketing positions at Rightworks, an ERP software company, Vitelic Semiconductor and Samsung Semiconductor.

Tell us about your company.
Precision Timing is the heartbeat of modern electronics. Whether it’s in AI data centers, networking infrastructure, automated vehicles, personal mobility or IoT, nothing works without precise timing. In today’s connected intelligence era, SiTime’s uniqueness lies in delivering Precision Timing to enable electronic products that are smarter, faster and safer. We are taking a new approach to the highly fragmented timing market, using semiconductor technology and processes to reimagine time. SiTime is the only company that is solely focused on all aspects of timing, from components to systems and software. We are using microelectromechanical systems (MEMS) technology to transform the $10 billion timing market with products that offer higher performance, smaller size, lower power consumption and unmatched reliability. What makes SiTime unique, apart from our Precision Timing technology, is the diversity of applications, products, customers, and our team.

What problems are you solving?
The timing market has been historically fragmented, but with the need for today’s electronics to be faster, always connected, more intelligent, and safer, a differentiated approach is vital. To meet these requirements, electronics are now being deployed in the “real world,” outside pristine environments such as air-conditioned offices. Here, electronic devices are being subjected to environmental stressors such as rapid temperature changes, extreme temperatures, shock and vibration. The incumbent timing technology for the past several decades, quartz, is susceptible to these stressors, which can impact the performance and reliability of intelligent, connected electronics. Our MEMS and analog technologies solve this problem. We deliver Precision Timing solutions that are orders of magnitude more resilient to these environmental stressors and help make electronics smarter, faster, and safer. For example, we are enabling higher timing performance and accuracy in AI data centers and 5G networks, where nanosecond-level synchronization is required, even in the presence of environmental stressors.

Our semiconductor-based MEMS technology enables us to offer the smallest size, more features, and higher stability, which, again, meets the requirements of modern electronics. With our fabless semiconductor supply chain and built-in programmability, we deliver better supply reliability and the flexibility to configure a device to each customer’s exact application requirements. Over the past decade, we have improved our Precision Timing performance by several orders of magnitude, something that the incumbents have not been able to do. To summarize, we deliver higher performance, more features, higher reliability, smaller size and lower power to our customers.

What application areas are your strongest?
Our strongest markets for Precision Timing include AI data centers and all the networking electronics within, communications, automotive safety and infotainment, IoT, and aerospace and defense. Specific applications within these markets include 800G/1.6T optical modules, smart network interface cards (SmartNIC), 5G remote radio units (RRUs), advanced driver assistance systems (ADAS) cameras, radar and LiDAR, smartwatches and low-Earth orbit (LEO) satellites. For example, AI networking requires ultra-low jitter and latency, which our timing products deliver. Similarly, in autonomous vehicles, Precision Timing is critical for sensor synchronization and rapid decision-making. Our Endura Epoch Platform, for example, is making inroads in aerospace and defense applications, offering unmatched performance and reliability for critical applications such as positioning, navigation and timing (PNT) services. In fact, because of the various benefits of our timing technology, it’s safe to say that we are crucial to the future of electronics.

What keeps your customers up at night?
We’ve realized that we have two kinds of customers: the ones who have experienced and seen the benefits of our programmable timing chips and those who we are working closely with to come up with creative ways to address their timing issues. Our customers are concerned about keeping pace with rapid technological advancements. Whether they’re developing AI, communications, automotive or IoT applications, they must continuously innovate with their products. With the explosion of data-driven applications, companies also worry about achieving low-latency, high-reliability networks, especially as 5G and AI infrastructures continue to scale.

Another point is the ability to meet customers’ needs for scaling fast when the demand for their products increases. SiTime’s silicon manufacturing process ensures a stable, reliable, and independent supply chain with shorter lead times for the highest-quality timing products in the market. Our job is to be inventive and dependable so customers can be comfortable.

What does the competitive landscape look like and how do you differentiate?
After being asleep for so many years and considered a commodity product, timing technology is undergoing a transformation, led by SiTime. Traditional quartz-based timing solutions have been incumbents for the past several decades, but they are rapidly being displaced, given their lack of differentiation and programmability as customers demand smaller, more resilient and reliable, and energy-efficient Precision Timing solutions that our MEMS technology offers. SiTime differentiates itself as the only pure-play silicon timing company, which gives us a unique position to drive innovation in this market. Our programmable clock and oscillator solutions enable customers to tailor their timing devices for specific application needs, a major advantage in high-performance sectors like AI computing and data centers. We also focus heavily on system-level solutions, combining silicon MEMS technology with analog circuitry, advanced algorithms and high-volume packaging, which enables us to deliver unmatched precision, reliability, small size and low power consumption.

What new features/technology are you working on?
As the world becomes more connected and intelligent, we are focused on developing more Precision Timing solutions that meet the demand for stability, resilience, and lower power consumption.

For example, we have design wins with our Precision Timing products in all key applications of the AI ecosystem, including GPU and CPU boards, interconnect switches, optical modules, NIC cards, accelerator cards, active cables, and switches. To provide a sense of scale of our focus on AI, in 2024, we shipped 70 unique part numbers across 14 product families to 30 different customers developing AI hardware.

One of our key product innovations for the world of AI is our Chorus clock generator—the industry’s first integrated clock system-on-a-chip (ClkSoC) designed for AI data center applications. The Chorus ClkSoC integrates a clock IC, a silicon MEMS resonator, and oscillator circuitry into a single chip. By integrating the resonator and eliminating the need for external quartz crystal devices, Chorus simplifies system clock architectures for AI systems, accelerates design time by up to six weeks, and improves reliability and resilience. Chorus clocks are engineered to deliver 10 times better performance in half the size of equivalent quartz-based devices.

Another recent innovation is the Endura Epoch Platform, a ruggedized MEMS-based oven-controlled oscillator (OCXO) that provides significant improvements in size, weight, and power (SWaP) while delivering benchmark timing performance for AI data centers and 5G infrastructure. Epoch OCXOs solve critical timing issues that were previously insurmountable with quartz technology, especially when deployed under extreme environmental conditions. We’re also expanding the use of MEMS technology in emerging markets like aerospace and defense with our Endura Epoch Platform, which offers enhanced performance and resilience for critical PNT services.

How do customers normally engage with your company?
We collaborate closely with each customer’s technical team to design and deliver Precision Timing solutions that meet their unique application needs. This collaborative, system-level approach allows us to build deep, long-lasting relationships with industry leaders and ensures that our timing technology continues to meet their evolving requirements. We also engage with our customers’ commercial teams to ensure adequate supply and other business terms. In addition to the large players in electronics, we also support smaller players who might be developing new applications, devoting equal attention to their developments.

How do you see Precision Timing evolving in the future, and what role will SiTime play in that transformation?
Precision timing will become even more critical as the world continues to embrace AI, 5G-Advanced and 6G communications, automated driving, personal mobility, and IoT. We’re not only addressing today’s timing technology needs but also anticipating future demands. SiTime will continue to innovate in the areas of MEMS technology, analog circuits, packaging, integration, and software to develop Precision Timing solutions that push the boundaries of what’s possible. We envision a world where SiTime’s Precision Timing products are embedded in every critical application, from the cloud to the edge, enabling faster, smarter and more connected systems everywhere.

Also Read:

CEO Interview: Dr. Greg Newbloom of Membrion

CEO Interview: Sandeep Kumar of L&T Semiconductor Technologies Ltd.

CEO Interview: Dr. Sakyasingha Dasgupta of EdgeCortix

CEO Interview: Bijan Kiani of Mach42


CEO Interview: Dr. Greg Newbloom of Membrion

CEO Interview: Dr. Greg Newbloom of Membrion
by Daniel Nenni on 11-28-2024 at 6:00 am

Greg Nebloom Membrion

Greg Newbloom, Ph.D., is the founder & CEO of Membrion, a cleantech startup focused on recycling wastewater from harsh industrial processes. Membrion makes electro-ceramic desalination (ECD) membranes out of the same material as the silica gel desiccant packets found in the bottom of a beef jerky package. Dr. Newbloom’s leadership and entrepreneurial efforts have been recognized by a half-dozen regional and national awards including a “35 under 35” from the American Institute of Chemical Engineering and a 2024 Meaningful Business 100 award (MB100).

He has 50 patents in addition to co-authorship of a textbook and 300+ citations in many publications. His work is regularly featured in both local and national media. Dr. Newbloom has a BA in Science from Oregon State University, an MA in Science from The University of Washington, and holds his Doctor of Philosophy (Ph.D.), in Chemical Engineering also from The University of Washington.

Tell us about your company:
Membrion is a pioneering technology company that specializes in electro-ceramic desalination membranes. We help industries manage some of the toughest wastewater challenges, providing innovative solutions that handle high-salinity, acidic, and heavy-metal-laden wastewater in addition to advanced recovery objectives in water stressed areas. Our focus is on sustainable water reuse, ensuring that companies can meet their environmental goals without compromising on efficiency.

What problems are you solving?
We address the critical need for efficient and cost-effective wastewater treatment, especially in industries dealing with corrosive and complex effluents. Traditional filtration methods often struggle with these challenging conditions, but our ceramic membranes excel where others fail, providing an effective way to treat and recycle water in even the harshest environments.

What application areas are your strongest?
Our strongest applications are in industries with highly complex wastewater streams, including semiconductor manufacturing, metal finishing, mining, and chemical processing. These sectors often face the most stringent regulations and operational challenges when it comes to wastewater treatment, and Membrion’s solutions are tailor-made to meet those needs.

What keeps your customers up at night?
Our customers are concerned about staying compliant with changing environmental regulations, reducing their water consumption, and finding cost-effective ways to manage wastewater. They also worry about system downtime due to trucking delays and fouling or corrosion in their current water treatment systems, which can halt production and increase costs. Membrion alleviates these concerns by offering onsite, durable, reliable, and high-performing membrane technology that minimizes these risks.

What does the competitive landscape look like and how do you differentiate?
The water treatment industry is full of conventional polymeric membranes and chemical-based treatments. Membrion stands out by offering a unique ceramic membrane that is more durable and resistant to harsh conditions. Unlike competitors, our technology thrives in highly acidic, saline, and heavy metal-contaminated wastewater, offering a longer lifespan and better performance over time. This differentiation enables our customers to reduce operating costs while achieving their sustainability goals.

What new features/technology are you working on?
We are continually improving the efficiency and longevity of our ceramic membranes, exploring advanced applications in emerging markets such as mineral extraction (copper, lithium, and others) and battery recycling. We are also working on expanding our modular membrane systems to be more scalable and easier to integrate into existing industrial setups.

We offer a Water Service Agreement to our customers which provides a no-risk, performance-based model where you only pay for treated water that meets your specifications. With no upfront costs for equipment or maintenance, Membrion guarantees effective wastewater treatment at a lower price than traditional methods.

How do customers normally engage with your company?
Customers typically engage with us through direct consultations, where we assess their specific wastewater challenges and design customized solutions. We also partner with engineering firms and integrators to implement our technology into new or existing water treatment systems. Additionally, we offer pilot programs to allow customers to test our membranes in their operations before committing to full-scale adoption. If you think Membrion solutions will be a good fit for your facility, let us know your wastewater challenges: https://membrion.com/contact-us/.

Also Read:

CEO Interview: Sandeep Kumar of L&T Semiconductor Technologies Ltd.

CEO Interview: Dr. Sakyasingha Dasgupta of EdgeCortix

CEO Interview: Bijan Kiani of Mach42


MZ Technologies is Breaking Down 3D-IC Design Barriers with GENIO

MZ Technologies is Breaking Down 3D-IC Design Barriers with GENIO
by Mike Gianfagna on 11-27-2024 at 10:00 am

MZ Technologies is Breaking Down 3D IC Design Barriers with GENIO

3D-IC design can be both exciting and frustrating. It’s exciting because it opens a new world of innovation possibilities – opportunities that aren’t constrained by the rules of monolithic chip scaling. It can be frustrating because of the large array of complex technical challenges that must be overcome to make this new paradigm accessible. MZ Technologies’ mission is to conquer 2.5D & 3D design challenges for next generation electronic products by delivering innovative, ground-breaking EDA software solutions and methodologies. MZ’s flagship product is GENIO, and the company recently announced a comprehensive roadmap for it. If 2.5 & 3D design are in your future, this is big news. Let’s examine how MZ Technologies is breaking down 3D-IC design barriers with GENIO.

What’s Coming

GENIO™ is an integrated chiplet/packaging co-design EDA tool. The announced roadmap calls for improvements to the product throughout 2025, starting with four significant additions that will be unveiled in mid-January.  Other new features will be added around the middle of the year and at year’s end.

The features coming at the beginning of the year address some truly difficult design challenges. The focus is thermal and mechanical stress. These enhancements will also include an improved and modernized user interface.  

These new features tackle next-generation 3D-IC design challenges head-on.  To provide some background, 3D heterogeneous devices suffer from thermal stress that comes from uneven heat distribution during operation, potentially leading to warping and even reliability failures. To address thermal challenges, robust management strategies are essential. Application of the right tools will minimize temperature differentials. The result is optimal performance and longevity of the chiplets used in the design.

Mechanical stress can result from processes such as thermal expansion mismatch and substrate flexing. These effects can cause interconnect failures and even delamination. A robust approach is needed to maintain structural integrity and performance across varying operational conditions and material interfaces. The new version of GENIO delivers enhanced capabilities in both areas. Mid-year, the company is expected to add additional thermal and interconnect features to GENIO.

Anna Fontanelli

These enhancements build on the momentum already achieved by GENIO. Anna Fontanelli, Founder and CEO of MZ Technologies commented, “MZ Technologies rolled out the first commercially available co-design tool three years ago and we feel an obligation to the EDA community to continue to innovate.”

What’s Already Here

MZ Technologies has already released several enhancements. GENIO 1.7 saves even more design time than the previous version thanks to its ability to track and classify potential design process issues.

Using a dedicated, always-on dock, the newest version alerts designers to a full list of problems classified by severity, scope, and category. This extensive check provides a real-time update after any operation and new violations are added to something called the Issues Dock. The user can select an issue in this dedicated dock and all errors and warning are highlighted with a severity-driven color across the GUI and the 2D/3D design views. The amount of data associated with 2.5 & 3D design is massive and this feature helps to manage that complexity.

The new version performs several categories of checks, including placement rules during floor planning to catch violations such as overlapping instances, out of boundary placement, and ignored keep-out zones. Other checks spot vertical routing connectivity issues such as broken nets and crossing fly lines. The graphic as the top of this post shows an example of this capability.

To Learn More

MZ Technologies provides automated solutions that facilitate the design and optimization of complex, heterogeneous IC systems. You can learn more about this unique company on SemiWiki here. You can read the full text of MZ Technologies roadmap announcement here. And you can find out more about GENIO here. And that’s how MZ Technologies is breaking down 3D-IC design barriers with GENIO.


Compiler Tuning for Simulator Speedup. Innovation in Verification

Compiler Tuning for Simulator Speedup. Innovation in Verification
by Bernard Murphy on 11-27-2024 at 6:00 am

Innovation New

Modern simulators map logic designs into software to compile for native execution on target hardware. Can this compile step be further optimized? Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas. As always, feedback welcome.

The Innovation

This month’s pick is Efficient Compiler Autotuning via Bayesian Optimization. This was published in in the 2021 IEEE/ACM International Conference on Software Engineering and has 22 citations. The authors are from Tianjin University, China and Newcastle University, Australia.

Compiled code simulation is the standard for meeting performance needs in software-based simulation, so should benefit from advances in compiler technology from the software world. GCC and LLVM compilers already support many optimization options. For ease of use, best case sequences of options are offered as -O1/-O2/-O3 flags to improve application runtime, determined by averaging over large codebases and workloads. An obvious question is whether a different sequence delivering even better performance might be possible for a specific application.

This is an active area of research in software engineering, looking not only at which compiler options to select (eg function inlining) but also in what order these options should appear in the sequence, since options are not necessarily independent (A before B might deliver different performance versus B before A).

Paul’s view

Using machine learning to pick tool switches in Place & Route to improve PPA is one of the best examples of commercially deployed AI in the EDA industry today. A similar concept can be applied to picking compiler switches in logic simulation to try and improve performance. Here, there are clear similarities to picking C/C++ compiler switches, known as “compiler autotuning” in academic circles.

In this month’s paper, the authors use a modified Bayesian algorithm to try and beat -O3 in GCC. They use a benchmark suite of 20 small ~1k line C programs (matrix math operations, image processing, file compression, hashing) and consider about 70 different low level GCC switches. The key innovation in the paper is to use tree-based neural networks as the Bayesian predictor rather than a Gaussian process, also during training to quickly narrow down 8 “important” switches and heavily explore permutations of these 8 switches.

Overall, their method is able to achieve an average 20% speed-up over -O3. Compared to other state-of-the-art methods this 20% speed-up is achieved with about 2.5x less training compute. Unfortunately, all their results are using a very old version of GCC from 12 years ago, which the authors acknowledge at the end of their paper, along with a comment that they did try using a more recent version of GCC and were able to achieve only a 5% speed-up over -O3. Still, a nice paper, and I do think the general area of compiler autotuning can be applied to improve logic simulation performance.

Raúl’s view

Our 2024 penultimate paper for the year addresses setting optimization flags in compilers to achieve the fastest code execution (presumably other objective functions like code size or energy expended during computation could have been used). In the compilers studied, GCC and LLVM using 71 and 64 optimization flags respectively. The optimization spaces are vast at 271 and 264. Previous approaches use random iterative optimization, genetic algorithms, Irace (tuning of parameters by finding the most appropriate settings given a set of instances of an optimization problem, “learning”). Their system is called BOCA.

This paper uses Bayesian optimization, an iterative method to optimize an objective function using the accumulated knowledge in the known area of the search space to guide samplings in the remaining area in order to find the optimal sample. It builds a surrogate model that can be evaluated quickly, typically using Gaussian Process (GP, you can look it up here, it is not explained in the paper) which doesn’t scale to high dimensionality (number of flags). BOCA uses a Random Forest instead (RF, also not explained in the paper). To further improve the search, optimizations are ranked into “impactful” and “less impactful” using Gini importance to measure the impact of optimizations (look it up here for more detail). Less impactful optimizations are considered only in a limited number of iterations, i.e., they “decay”.

The authors benchmark the 2 compilers on 20 benchmarks against other state of the art approaches, listing the results for 30 to 60 iterations. BOCA achieves given desired speedups in 43%-78% less time. Against the highest optimization setting of the compilers (-o3) BOCA achieves a speedup of 1.25x for GCC and 1.13x for LLVM. Notably, using around 8 impactful optimizations is best, as more can slow BOCA down. The speedup is limited when using more recent GCC versions, 1.04-1.06x.

These techniques yield incremental improvements. They would certainly be significant in HW design where they can be used for simulation and perhaps for setting optimization flags during synthesis and layout, where AI approaches are now being adopted by EDA vendors. Time will tell.

Also Read:

Cadence Paints a Broad Canvas in Automotive

Analog IC Migration using AI

The Next LLM Architecture? Innovation in Verification

Emerging Growth Opportunity for Women in AI

 


Scaling AI Data Centers: The Role of Chiplets and Connectivity

Scaling AI Data Centers: The Role of Chiplets and Connectivity
by Kalar Rajendiran on 11-26-2024 at 6:00 am

Building the Modern Data Centre AI Compute Nodes

Artificial intelligence (AI) has revolutionized data center infrastructure, requiring a reimagining of computational, memory, and connectivity technologies. Meeting the increasing demand for high performance and efficiency in AI workloads has led to the emergence of innovative solutions, including chiplets, advanced interconnects, and optical communication systems. These technologies are transforming data centers into scalable, flexible ecosystems optimized for AI-driven tasks.

Alphawave Semi is actively advancing this ecosystem, offering a portfolio of chiplets, high-speed interconnect IP, and design solutions that power next-generation AI systems.

Custom Silicon Solutions Through Chiplets

Chiplet technology is at the forefront of creating custom silicon solutions that are specifically optimized for AI workloads. Unlike traditional monolithic chips, chiplets are modular, enabling manufacturers to combine different components—compute, memory, and input/output functions—into a single package. This approach allows for greater customization, faster development cycles, and more cost-effective designs. The Universal Chiplet Interconnect Express (UCIe) is a critical enabler of this innovation, providing a standardized die-to-die interface that supports high bandwidth, energy efficiency, and seamless communication between chiplets. This ecosystem paves the way for tailored silicon solutions that deliver the performance AI workloads demand, while also addressing power efficiency and affordability.

Scaling AI Clusters Through Advanced Connectivity

Connectivity technologies are the backbone of scaling AI clusters and geographically distributed data centers. The deployment of AI workloads in these infrastructures requires high-bandwidth, low-latency communication between thousands of interconnected processors, memory modules, and storage units. While traditional Ethernet-based front-end networks remain critical for server-to-server communication, AI workloads place unprecedented demands on back-end networks. These back-end networks facilitate the seamless exchange of data between AI accelerators, such as GPUs and TPUs, which is essential for large-scale training and inference tasks. Any inefficiency, such as packet loss or high latency, can lead to significant compute resource wastage, underlining the importance of robust connectivity solutions. Optical connectivity, including silicon photonics and co-packaged optics (CPO), is increasingly replacing copper-based connections, delivering the bandwidth density and energy efficiency required for scaling AI infrastructure. These technologies enable AI clusters to grow from hundreds to tens of thousands of nodes while maintaining performance and reliability.

Memory Disaggregation for Resource Optimization

AI workloads also demand innovative approaches to memory and storage connectivity. Traditional data center architectures often suffer from underutilized memory resources, leading to inefficiencies. Memory disaggregation, enabled by Compute Express Link (CXL), is a transformative solution. By centralizing memory into shared pools, disaggregated architectures ensure better utilization of resources, reduce overall costs, and improve power efficiency. CXL extends connectivity beyond individual servers and racks, requiring advanced optical solutions to maintain low-latency access over longer distances. This approach ensures that memory can be allocated dynamically, optimizing performance for demanding AI applications while providing significant savings in operational costs.

The Emergence of the Chiplet Ecosystem

A thriving chiplet ecosystem is emerging, fueled by advances in die-to-die interfaces like UCIe. This ecosystem allows for a wide variety of chiplet use cases, enabling modular and flexible design architectures that support the scalability and customization needs of AI workloads. This modular approach is not limited to high-performance computing; it also has implications for distributed AI systems and edge computing. Chiplets are enabling the creation of custom compute-hardware for edge AI applications, ensuring that AI models can operate closer to users for faster response times. Similarly, distributed learning architectures—where data privacy is a concern—rely on chiplet-based solutions to train AI models efficiently without sharing sensitive information.

Summary

AI is redefining data center infrastructure, necessitating solutions that balance performance, scalability, and efficiency. Chiplets, advanced connectivity technologies, and memory disaggregation are critical enablers of this transformation. Together, they offer the means to scale AI workloads affordably while maintaining energy efficiency and reducing time-to-market for new solutions. By harnessing these innovations, data centers are better equipped to handle the demands of AI, paving the way for more powerful, efficient, and scalable computing solutions.

  • Chiplet technology enables tailored silicon solutions optimized for AI workloads, offering affordability, lower power consumption, and faster deployment cycles.
  • Optical communication technologies, such as silicon photonics and co-packaged optics, are vital to scaling AI clusters and distributed data centers.
  • Memory disaggregation via CXL maximizes resource utilization while reducing costs and energy consumption.

Learn more at https://awavesemi.com/

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How AI is Redefining Data Center Infrastructure: Key Innovations for the Future

Elevating AI with Cutting-Edge HBM4 Technology

Alphawave Semi Unlocks 1.2 TBps Connectivity for HPC and AI Infrastructure with 9.2 Gbps HBM3E Subsystem


One Thousand Production Licenses Means Silicon Creations PLL IP is Everywhere

One Thousand Production Licenses Means Silicon Creations PLL IP is Everywhere
by Mike Gianfagna on 11-25-2024 at 10:00 am

Spread Spectrum Modulator RTL IP provides industry standard and custom modulation patterns for Silicon Creations fractional N PLLs

If you sell sneakers, 1,000 pair is called a humble beginning. On the other hand, selling 1,000 licenses for specialized analog IP is a home run.  Silicon Creations celebrated a home run for a critical piece of analog IP that finds its way into a diverse array of applications. Succeeding in so many markets is noteworthy, and I want to share some significant facts around this achievement. You will see how 1,000 production licenses mean Silicon Creations PLL IP is everywhere.

About Silicon Creations

Silicon Creations is a self-funded, leading silicon IP provider. The company provides high-quality IP for precision and general-purpose timing (PLLs), oscillators, low-power, high-performance multi-protocol and targeted SerDes, and high-speed differential I/Os.  The IP finds diverse applications including smart phones, wearables, consumer devices, processors, network devices, automotive, IoT, and medical devices. As you can see, the company provides a lot of IP to multiple markets.

The just-announced milestone centers on its Fractional-N PLL IP. This IP delivers a multi-function, general-purpose frequency synthesizer. Unlike an integer-N PLL, the output frequency of a fractional-N PLL is not limited to integer multiples of the reference frequency. This significantly expands the scope of where the IP can be used. The complexity of the circuit also significantly increases, making it challenging to deliver reliable performance across all applications.

Silicon Creations has tackled this problem to deliver ultra-wide input and output ranges along with excellent jitter performance, modest area, and application-appropriate power. The result is a PLL that can be configured for almost any clocking application in complex SoC environments.

About the Achievement

Randy Caplan

In the press announcement, Silicon Creation’s principal and co-founder, Randy Caplan expanded on this achievement. He explained the company’s Fractional SoC PLLs have been deployed on more than 6 million wafers, translating to billions of chips in the market today.

Those are some very impressive numbers. Randy went on to highlight that the IP is available in a wide range of process nodes, from 2nm to 180nm. This is a testament to the robustness and adaptability of the technology, as it continues to meet the demands of the most advanced applications.

The Silicon Creations Fractional-N PLL IP is successfully deployed in a wide range of application areas, including:

  • High-performance digital clocking
  • PHY reference clock generation (e.g., DDR, PCIe, Ethernet, USB)
  • Fast frequency hopping
  • Spread-spectrum modulation
  • Micro-degree resolution phase stepping

Thanks to its broad feature set, robustness, and reliability, the IP finds application in many markets, including AI, automotive, consumer electronics, IoT, and high-performance computing (HPC).

Customer Testimonials

Kiran Burli

Key members of Silicon Creation’s customer base also weighed in with their perspectives.  Kiran Burli, vice president of Technology Management, Solutions Engineering, Arm, commented, “Arm has successfully utilized Silicon Creations’ Fractional-N PLL to clock our prototype chips across leading edge process nodes for more than a decade. Our collaboration with Silicon Creations ensures optimized performance of the Arm compute platform across a wide range of markets and use cases.”

 

Shakeel Peera

Shakeel Peera, vice president of marketing and strategy for Microchip’s FPGA business unit, commented, “Silicon Creations’ PLL technology is used throughout the PolarFire® FPGA family, including our RT line for space and high-reliability applications. The flexibility and performance of these PLLs support a wide range of use cases, allowing our customers to tailor their designs to meet specific demands across various applications.” Peera added, “We look forward to continuing our collaboration with Silicon Creations as we advance FPGA technology.”

To Learn More

You can read the full text of the press release from Silicon Creations here and listen to Randy Caplan explain the unique business model of Silicon Creations on the Semiconductor Insiders podcast here.  The full library of IP available from Silicon Creations can be found here. And that’s how Silicon Creations PLL IP is everywhere.

Also Read:

Silicon Creations is Fueling Next Generation Chips

Silicon Creations at the 2024 Design Automation Conference

Silicon Creations is Enabling the Chiplet Revolution


Cadence Paints a Broad Canvas in Automotive

Cadence Paints a Broad Canvas in Automotive
by Bernard Murphy on 11-25-2024 at 6:00 am

automotive trends min

Cadence recently launched a webinar series on trends and challenges in automotive design. They contribute through IP from their Silicon Solutions Group, a comprehensive spectrum of design tooling and through collaborative development within a wide partner ecosystem. This collaboration aims to support and advance progress through reference architectures and platforms co-developed with auto OEMs, AI solution builders, foundries and others. I’m writing here on the overview webinar. Check-in with Cadence on upcoming webinars in the series which will dive more deeply into these topics.

Market trends

Automotive options today can be overwhelming: BEVs versus HEVs, ADAS versus different flavors of autonomous driving, in-cabin features galore, often at eye-popping prices. No wonder auto OEMs are juggling architectures, production priorities and radical ideas to monetize mobility. Yet all this churn also represents expanding opportunities in the supply chain, for Tier1s, semiconductor suppliers, foundries, and beyond. Automotive semiconductors are expected to deliver a CAGR of 11% through 2029 and the silicon carbide market (critical to support EV trends) is expected to grow even faster, at a CAGR or 24% through the same period.

Growth is driven in part by electrification and in part by increased sensing and AI content to add more intelligence to ADAS, autonomous driving (AD) and the driver/passenger safety and experience. All this new capability adds cost in hardware, creating pressure tο mitigate costs by consolidating electronics content into a smaller number of devices through zonal architectures. It also adds complexity in software/AI modeling, further contributing to cost and amplifying safety concerns through disaggregated software and AI model development and support, in turn pushing for more vertical integration in the supply chain.

Robert Schweiger (Group Director, Automotive Solutions at Cadence) observed that, as a key supplier in this design chain, Cadence sees a clear trend to vertical integration among auto OEMs and Tier1s now wanting to be hands-on in critical semiconductor and systems design. This isn’t necessarily bad news for automotive semiconductor companies; they too will participate but markets for advanced systems are becoming more competitive.

Robert recapped some sensor trends from this year’s AutoSens conference, some of which I have talked about elsewhere but I think are worth repeating here. Hi-res (8MP) cameras will become mainstream in support of AI. Low-cost, “unintelligent” cameras will also play a role in transferring raw video streams to the central processor on which AI-based inferences can be overlaid. 4D imaging radar (4DR) is catching up fast versus Lidar (except so far in China) thanks to lower pricing. In-cabin sensing for driver monitoring systems (attention, alertness) is now a requirement for a top safety rating according to the EURO-NCAP standard. Similarly, occupancy detection (did I leave a child in the backseat when I locked the car?) is becoming more popular. Both systems use in-cabin cameras or radar.

Cadence automotive technology update

In interest of brevity here I will just call out recent updates. The Tensilica group has been very active, introducing new vision cores (3xx series) and a 4DR hardware accelerator that can be used for vision and radar applications, to which you can add a Neo (or other) NPU for higher-performance AI tasks. I found a zonal controller graphic very interesting here, a single controller connecting to multiple radar and vision sensors, processing vision and radar streams before handing off to a fusion accelerator for enhanced point cloud generation. Clearly, the zonal controller must be close enough to the sensors with a high-speed link  to manage bandwidth/latency between sensors and that controller.

On connectivity, Robert anticipates Automotive Ethernet will play a big role between central and zonal ECUs. At the edges between sensors and zonal ECUs, options are not yet quite so standardized, trending to SERDES-based interfaces to provide necessary bandwidth or MIPI in cases that aren’t quite as demanding. Cadence SSG has connectivity solutions to support all these options.

3D-IC is another important objective in total system cost reduction. Notable recent additions here are Integrity 3D-IC to guide planning, co-design, cross-die optimization, Allegro for package layout co-design and Virtuoso with 3D analysis. Together with UCIe controller, PHY, and verification IP.

In verification, there has been a variety of Verification IP updates. The Helium platform plus integration with Palladium and Protium platforms enables a hybrid virtual prototyping design flows allowing for software development in the cloud as hardware is under development. The MIDAS safety platform drives verification of safety requirements through the Unified Safety Format (USF) with both digital and analog design to ensure compliance with ISO 26262/ASIL requirements. Also now Palladium emulation platforms are fault-simulation-capable, making full-SoC analyses with software stacks practical for system-level safety validation.

In system design and analysis I didn’t see recent updates but of course Cadence hosts a full suite of thermal, RF, EM, SI/PI and CFD solutions, applicable from chip, to board, to rack, even to datacenter.

Finally, Robert also introduced a new Power Module Flow for the design of silicon carbide-based power electronic systems for advanced EV powertrain applications. This flow targets power module design considering thermal, EMI and mechanical stress factors plus die and package co-optimization.

Partnerships / collaborative development

Getting to convergence in this massive re-imagination of a modern car is only possible through major collaborations, prototyping, building reference designs, and integrating with cloud-native software development platforms.

One example is the ZuKiMo government-funded project, taped out on GF22nm and demoed at Embedded World 2024, featuring DreamChip’s latest automotive SoC, hosting Automotive Ethernet, Tensilica AI accelerator IP, and BMW AI image recognition.

At Chiplet Summit 2024 Cadence demonstrated a 7-chiplet system connected through their UCIe in a standard package, running at up to 16GT/s.

Cadence is also collaborating with Arm in support of the SOAFEE initiative, supporting cloud-native design starting with Helium-based virtual prototyping, while allowing subsystems to progressively transition to hardware-based modeling for more precise validation as a design stabilizes.

As one last telling example of collaboration, Tesla has partnered with Cadence to develop their DOJO AI platform, their next step in a full self-driving solution.

In summary, Cadence is plugged into automotive whichever way markets go. You can sign up for the next webinar in the series HERE.

Also Read:

Analog IC Migration using AI

The Next LLM Architecture? Innovation in Verification

Emerging Growth Opportunity for Women in AI

Addressing Reliability and Safety of Power Modules for Electric Vehicles


Podcast EP262: How AI is Changing Semiconductor Design with Rob Knoth

Podcast EP262: How AI is Changing Semiconductor Design with Rob Knoth
by Daniel Nenni on 11-22-2024 at 10:00 am

Dan is joined by Rob Knoth, Solutions Architect in the Strategy and New Ventures group at Cadence. He is a technologist focusing on corporate strategy and the interfaces between domain specific solutions. A key area of expertise is the digital implementation of safety critical and high reliability systems. He has extensive experience in both semiconductor design and EDA.

In this wide-ranging and informative discussion, Dan explores the impact AI is having on semiconductors and semiconductor design with Rob. AI in the EDA flow is discussed, including areas such as harvesting past data to improve future designs, impacts to analog design, verification, and packaging/3DIC.

Rob describes the three layers of EDA within Cadence. These areas include AI-enhanced design engines, AI-assisted optimization and the use of generative AI as a “co-pilot” to assist with tasks such as optimization, verification and generation of new designs.

Rob reviews many examples and use cases for this technology across diverse applications. He also discusses the future of AI-assisted design and the positive impact he expects to see on designer productivity and innovation.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.