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The ASIC business has always been a key enabler of the semiconductor industry but it is a difficult business. In my 40 years I have seen many ASIC companies come and go but I have never seen one like Alchip.
Alchip Technologies Ltd. was founded more than 20 years ago, about half way through my career. I know one of the founders, a fiercely competitive man equally matched with intelligence and charm. The founding Alchip team was from Simplex Solutions, a design and verification company, which was acquired by Cadence for $300M, a very big number in 2002.
Simplex had a close relationship with Sony (the Playstation 2 ASIC) and that relationship continued with Alchip. TSMC was also a key relationship for Alchip as an investor and manufacturing partner. TSMC at one time owned 20% of Alchip. At the same time (2002/2003) TSMC also invested in another ASIC provider Global Unichip (GUC) and is now the largest shareholder. As I mentioned, ASICs are a key semiconductor enabler and TSMC is a big reason why.
Bottom line: Alchip has passed the test of time with flying colors and is the one to watch for complex ASICs and SoCs, absolutely.
Here is their latest press release:
Taipei, Taiwan August 31, 2024 – Alchip Technologies’ Q2 2024 financial results set second-quarter records for revenue, operating income, and net income.
Second-quarter 2024 revenue notched a record $421 million, up 62.8% from Q2 2023 revenue of $258.5 million and up 26.2% over Q1 2024 revenue of $333.6 million. Operating income for the second quarter of 2024 was a record $51.2 million, representing an 80.2% increase over Q2 2023 operating income of $28.4 million, and a 32.8% increase over Q1 2024 operating income of $38.5 million.
At the same time, second-quarter 2024 net income set a record of $49.3 million, 105.8% higher than Q2 2023 net income of $23.9 million, and up 26.3% compared to Q1 2024 net income of $39 million. Earnings per share for Q2 2024 were NTD 20.1.
Commenting on the record results, Alchip President and CEO Johnny Shen cited revenue growth driven by higher-than-expected AI ASIC shipments to a major customer; in particular the shipments of AI ASIC to a North America service customer and the ramp-up of a 5nm AI accelerator to a North America IDM customer.
In total, AI and high-performance computing applications accounted for 91% of Q2 2024 revenue, with networking contributing 6%, niche applications adding 2%, and consumer uses accounting for the remaining 1%.
On a process technology basis, revenue derived from designs at 7nm and more advanced nodes accounted for 96% of Q2 2024 revenue and 95% of first-half 2024 revenue. The North America region accounted for 78% of Q2 2024 revenue, while the Asia Pacific region contributed 8%, with Japan and other regions made up the remaining 14%.
About Alchip
Alchip Technologies Ltd., founded in 2003 and headquartered in Taipei, Taiwan, is a leading global provider of silicon and design and production services for system companies developing complex and high-volume ASICs and SoCs. Alchip provides faster time-to-market and cost-effective solutions for SoC design at mainstream and advanced process technology. Alchip has built its reputation as a high-performance ASIC leader through its advanced 2.5D/3DIC design, CoWoS/chiplet design and manufacturing management. Customers include global leaders in AI, HPC/supercomputer, mobile phones, entertainment device, networking equipment and other electronic product categories. Alchip is listed on the Taiwan Stock Exchange (TWSE: 3661).
You could be forgiven for thinking of hearing aids as the low end of tech, targeted to a relatively small and elderly audience. Commercials seem unaware of advances in mobile consumer audio, and white-haired actors reinforce the intended audience. On the other hand, the World Health Organization has determined that at least 6% of people worldwide have at least some hearing loss, and they expect this number to grow to 9% by 2050. Even more remarkably, in the US 20% of people in their 20’s are already reported to have noise-induced hearing loss.
Image courtesy of Jeff Miles
Given the rapid technology and consumerization advances we are seeing in consumer audio, particularly in earbuds, slow progress in hearing aids seems odd since you would think these should share similar growth opportunities. A welcome shift therefore is a recent FDA announcement that Apple Airpods Pro (with an added software feature) is authorized to sell over the counter as a hearing aid. If Apple sees meaningful business expansion in this direction, then I assume other earbud and hearing aid makers will follow quickly.
A different kind of consumerization
In fairness to traditional hearing aid makers there are reasons they didn’t jump on this opportunity immediately. These are partly cost and partly reliability – elderly users on a fixed income don’t want to pay thousands of dollars for devices which may not immediately fit their needs, and they certainly don’t want to upgrade every 2 years.
But more than that, the abundance of features we expect in regular consumer devices can be an active negative for non-tech-aware users, judging by high return rates on early attempts. Such users will certainly enjoy the benefits: increased clarity, TWS support, making phone calls. But don’t ask them to install apps, deal with a bewildering range of options, or figure out what steps to take when something doesn’t work.
This presents a challenge because configuring the aids to a user’s personal hearing needs is critical in making this technology effective. An audiologist can tune a configuration the first time, but hearing needs evolve over time and audiologist visits are inconvenient and perhaps expensive. Even more inconvenient when the aids stop working, especially if you wanted to save money by buying over the counter (OTC).
For this reason, there’s an active trend towards hearing aids self-calibrating through AI, with minimal user feedback. In fact AI-based model opportunities are sparking growth of an early software ecosystem around these devices. According to Casey Ng (Audio Product Marketing Director at Cadence), this 3rd party software market has come as a surprise to some product builders who are not used to the demands of an ecosystem expecting increased memory, APIs, and developer support.
Calibration, or more popularly now personalization, has important value for the rest of us. Wherever we are on the hearing disability spectrum, our ears are unique enough that our hearing experience can benefit from a personalized configuration. This is good news for younger users who need help. Rather than suffer the stigma of wearing classic aids they can use their earbuds (almost a fashion statement these days) which they can optimize to their hearing needs.
Cadence Tensilica Audio DSPs are ready to help
In support of audio applications, the Cadence Tensilica HiFi DSP family offers a range of DSP options from the ultra-low-power HiFi 1 DSP, to the HiFi 5s which is most interesting to me in the context of this hearing aid discussion. This platform is designed to manage TWS, active noise cancellation, also automatic speech recognition for voice-based commands, plus support for more general AI-based applications. Cadence also offers access to a rich supporting audio and voice ecosystem (300 packages) which should accelerate time to market for OEMs.
Among these, noise cancellation options go beyond conventional noise/echo suppression. HiFi 5s offers AI to distinguish and select speech over other audio sources, an important refinement for the hearing impaired.
Importantly these advances (including AI) demand enhanced processing capability. Cadence’s power-efficient HiFi platforms are able to offer that performance yet still extend battery life between recharges, a very important benchmark when users need their hearing aids to last for a complete work-day.”
Casey tells me that the Cadence Tensilica group are also working closely with OEMs who are building their own learning-based personalization models and software. They have also joined a venture with Hoerzentrum Oldenburg GmbH, Leibniz University Hannover, and Global Foundries to build a prototype Smart Hearing Aid Processor (SmartHeAP).
Looks to me like serious commitment to advancing technology in hearing aids! You can learn more about this topic HERE.
Dan is joined by Christopher Vick, the Vice President of Engineering at Lemurian Labs, bringing over three decades of experience from top tech companies such as Qualcomm, Oracle, and Sun Microsystems. Throughout his distinguished career, Christopher has played a key role in developing technologies used by billions.
Notably, Vick led the creation of software development tools for Qualcomm’s 5G modems and was one of the original developers of the HotSpot Java Virtual Machine at Sun Microsystems. In his role at Lemurian Labs, he drives engineering strategy, focusing on creating innovative solutions to make AI development more efficient, accessible, and performance-driven.
In this very informative podcast, Christopher provides an overview of new development approaches that can be applied to AI training and algorithm development to make the process more efficient and predictable. The result is a democratization of AI, making the technology available to a wide range of applications.
The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.
Tobias began his journey with a strong academic foundation in electronic design automation, studying at a leading university in Germany that specialized in formal verification. After graduating, Tobias gained hands-on experience in the semiconductor industry, where he quickly recognized the challenges and inefficiencies in the traditional formal verification process.
Driven by a passion for innovation, Tobias co-founded LUBIS EDA with a clear vision: to automate and simplify formal verification, making it more accessible to companies of all sizes. Under his leadership, LUBIS EDA integrated a dedicated team of software developers focused on automating verification processes. He also pioneered the adoption of AI techniques to enhance debugging and setup.
Acknowledging the shortage of skilled formal verification engineers, Tobias launched the Formal Bootcamp, a training program designed to bridge the talent gap and prepare the next generation of experts.
Today, as CEO, Tobias leads LUBIS EDA in helping semiconductor companies around the world overcome the most challenging aspects of formal verification, driving both innovation and industry standards.
Tell us about your company?
At LUBIS EDA, we specialize in uncovering simulation-resistant and corner-case bugs in high-risk silicon designs by automating the formal verification process. We go beyond the traditional, labor-intensive methods, integrating cutting-edge tools and AI techniques to make formal verification more accessible and effective.
Our team is based in Germany, close to one of the few universities in the country that teach formal verification, ensuring we stay at the forefront of industry knowledge. We don’t just provide solutions; we also empower our customers through consulting-based formal sign-off and our specialized Formal Bootcamp training program.
Whether it’s working on complex IPs like caches, routers, and controllers, or addressing the talent gap in formal verification, we’re committed to helping our customers succeed. Our goal is to simplify the verification process, allowing our customers to focus on innovation, not bugs.
What problems are you solving?
First, finding bugs at the Sub-IP level is notoriously difficult. Simulation often falls short in achieving comprehensive coverage, especially for detecting deadlocks and livelocks. Our automated formal verification tools simplify this process, making it more accessible and effective.
Second, there’s a significant shortage of skilled professionals capable of executing complex formal verification tasks. Traditionally seen as a “PhD-level technique,” formal verification requires years of practice to master. At LUBIS EDA, we are dedicated to formal verification, and over the past year, we’ve built one of the largest talent pools for formal verification worldwide.
What application areas are your strongest?
We excel in various types of IPs, but where we truly shine is helping our customers maximize the potential of formal verification. We’ve added the most value in working on caches, routers, controllers, and all sorts of pipelines.
What keeps your customers up at night?
Imagine you’re a lead engineer at a small semiconductor company, and you’re nearing the final stages of a critical chip design. The pressure is mounting—deadlines are looming, and you can’t afford any last-minute surprises. What keeps you up at night? It’s the fear that somewhere, buried deep in the complexity of your design, there’s a lurking bug—one that could derail months of hard work.
What does the competitive landscape look like and how do you differentiate?
In the realm of formal verification, much of the work remains manual and time-consuming, with a few other consulting firms offering similar services. However, we’ve taken a different approach. Rather than simply adding more people to tackle the problem, we’ve integrated a dedicated team of software developers into our company from the start. Their mission is to automate every aspect of the formal verification process. Recently, we’ve also begun incorporating AI techniques to streamline debugging and setup, further setting us apart from the competition.
What new features/technology are you working on?
We are currently focused on two main development areas:
Browser-Based Automated Verification Solution:
We’re working on a web-based tool that simplifies formal verification to the point where users require no training or prior knowledge. Our initial release will feature a RISC-V formal verification app, where users simply click a “run” button. The tool handles everything, including licensing and resource management. If a bug is detected, the user receives a comprehensive, AI-generated description of the issue directly from the waveform. This app is just the beginning—we plan to expand its capabilities to include protocol and cache checks in the coming months.
C++ Based FV AppGenerator:
We have developed a tool that generates SVA assertions from a SystemC/C++ model. This tool, which has been years in the making and proven invaluable in our consulting projects, allows users to run assertions in simulation or formal verification without any prior expertise.
How do customers normally engage with your company?
The easiest way to connect with us is via LinkedIn or email, and we’re committed to responding promptly. We also schedule regular sync-ups with all our customers to address questions and provide ongoing support throughout their formal verification journey.
Artificial intelligence (AI) is driving a transformation in data center infrastructure, necessitating cutting-edge technologies to meet the growing demands of AI workloads. As AI systems scale up and out, next-gen compute servers, switches, optical-electrical links, and flexible, redundant networking solutions are crucial. Key innovations—such as advanced connectivity technologies, custom silicon solutions via chiplets, and the proliferation of optical connectivity—are redefining how AI clusters are deployed and operated.
Tony Chan Carusone, CTO at Alphawave Semi gave a talk on this subject at the AI Hardware and Edge AI Summit held in September 2024.
Connectivity Technologies: Enabling Scalable AI Clusters
Scaling AI clusters, whether housed in a single data center or distributed across multiple locations, hinges on high-performance connectivity technologies. AI’s front-end networks, handling data flow, and back-end ML networks, processing large-scale AI computations, require low-latency, high-speed communication. This is increasingly supported by optical-electrical links and flexible, redundant networking, ensuring smooth operation even as demands grow.
A key innovation is the shift from copper-based systems to advanced optical connectivity solutions like pluggable optical modules and co-packaged optics (CPO). These technologies boost performance by reducing latency and increasing bandwidth, critical for AI tasks requiring rapid data exchange.
CPO integrates miniature optical engines directly into chip packages, replacing electrical interconnects with optical fiber. Combined with electrical I/O chiplets, CPO chiplets offer a mix-and-match solution optimized for different applications, enhancing AI processing speed and efficiency.
Chiplets: Optimized Silicon Solutions for AI Workloads
As AI workloads grow more complex, custom silicon solutions are essential. Chiplets enable specialized hardware tailored to specific AI tasks. Built on low-cost substrates, chiplets enhance affordability without sacrificing performance. Their flexible configurations help data centers meet diverse computational needs.
The chiplet ecosystem, built around die-to-die interfaces like Universal Chiplet Interconnect Express (UCIe), enables seamless communication between I/O, compute, and memory chiplets. For instance, I/O chiplets may feature multi-standard SerDes with controllers for PCIe Gen6, CXL 3.0, or 112Gbps Ethernet, while compute chiplets utilize Arm-based cores for high-performance processing. Memory expansion chiplets with low-latency DDR or HBM ensure faster data access, further enhancing AI performance.
Scaling Performance Affordably and Efficiently
The modular nature of chiplets allows for scalable performance at lower costs. Traditional monolithic chips are expensive and time-consuming to develop, but chiplets, with pre-validated reusable components, reduce development timelines and production costs. This is crucial for AI-driven industries, where efficiency and faster time-to-market are essential.
Chiplets also help manage power consumption—important as data centers scale. Innovations in die-to-die interfaces address challenges related to signal and power integrity, such as crosstalk and interconnect losses. Advances in power delivery and packaging technology, along with improved clocking solutions, are also increasing efficiency in dense signal routing and clock/data alignment.
The Rise of Optical Connectivity in AI Infrastructure
Optical connectivity technologies, particularly within chiplet ecosystems, are transforming the AI data center landscape. CPO and high-density optical I/O solutions are pushing the boundaries of AI clusters’ capabilities. By integrating optical components directly into chip designs, AI systems can handle greater data volumes with lower latency and increased energy efficiency.
Dense fiber arrays, multiple wavelengths, and advanced fan-out techniques ensure that optical I/O meets the increasing data demands of AI. These innovations not only improve speed but also enhance energy efficiency, critical in AI’s power-hungry landscape. The ability to mix optical and electrical I/O chiplets modularly enables tailored solutions for various AI applications, from large-scale training models to real-time inference.
The Future: Chiplet Ecosystem and Die-to-Die Interfaces
The expanding chiplet ecosystem, enabled by die-to-die interfaces, allows for a wide range of custom AI systems. This includes I/O, compute, and memory expansion chiplets, each optimized for specific tasks. Multi-standard SerDes I/O chiplets support high-speed protocols like PCIe Gen6 and 112Gbps Ethernet, while Arm-based compute chiplets provide the processing power for AI workloads. Memory expansion chiplets, with low-latency DDR or HBM, ensure fast data access for AI models.
Die-to-die interfaces like UCIe enable signal integrity by managing crosstalk and compensating for interconnect losses. Advances in power integrity and packaging technology further ensure scalability and reliability in AI systems.
Summary
As AI evolves, so must its supporting infrastructure. Connectivity technologies, chiplet architectures, and an ecosystem of optical and electrical solutions are driving the future of AI data centers. From advanced optical-electrical links and co-packaged optics to customizable chiplet designs, AI infrastructure is being built on scalable, flexible, and efficient solutions.
These innovations enable AI clusters to scale in performance and geographic distribution, allowing data centers to meet AI’s growing computational demands while keeping costs and energy consumption in check. As AI continues to expand, these technologies will unlock new levels of performance, efficiency, and scalability for data centers worldwide.
To learn about Alphawave Semi’s solutions addressing the AI Infrastructure revolution, visit https://awavesemi.com/
If the thought of a silicon respin keeps you awake at night, you’re not alone. Re-fabricating a chip can cost tens of millions of dollars. An unplanned respin also risks a delay in getting a product to market, which adds tremendous costs in terms of lost business.
Undoubtedly, adding to your sleep loss is the recent rise in respins. What’s causing this increase of failures when the design gets to silicon? As electronics products add increasing numbers of features and faster performance, things have gotten complicated. A patchwork of silicon IP, 100s of millions or billions of transistors, and the challenge of getting analog and digital to play in the same sandbox, has resulted in Byzantine sprawls across the die. Meanwhile, the growth of electronic components needed in AI solutions, automotive, 5G connectivity, gaming, medical IoT, and more continues to mushroom. For instance, contrast the abundance of electronics in today’s self-driving cars with your uncle’s Buick.
Complexity gone wild
As they race to satisfy this demand, companies are trying to fit all circuitry on the same substrate or on a single technology node. The latest process technologies plus cost-effective innovations in transistors, such as gate-all-around (GAA), further enable engineers to pack previously unfathomable numbers of transistors onto a die. Apple’s ARM-based dual-die M2 Ultra SoC, which is fabricated using TSMC’s 5 nm semiconductor manufacturing process, packs 134 billion transistors. And TSMC is charting a course for manufacturing one-trillion-transistor chips in 1nm.
This kind of complexity can cause everything from power issues to analog circuitry failing or falling out of operable range. And chipmakers are pushing into smaller and smaller nodes, which creates more challenges to success in manufacturing. For example, “The data suggest smaller node size and larger gate count are a contributing factor to power-related respins,” according to a recent article on Siliconengineering.com. “That means power could be the number one cause of respins for the biggest designs at the latest nodes, and that is before adding in the failures that are not recorded as ‘power-related’.”
Compounding the challenges of finding and fixing bugs or functional defects early in a design is the shortage of experienced designers. Complex SoC is a complex endeavor, which requires, for example, the ability to interpret design intentions from the schematics and understand arcane topics like transistor matching, noise tolerance, and parasitics.
Advanced device modeling to the rescue
So, how can you get your sleep back and avoid costly respins? Join a comprehensive webinar focused on enhancing device reliability and preventing silicon respins through innovative noise and binning modeling technologies. Keysight Technology engineers will give you deep dives into two combinations of tools and techniques that will reduce your chances of a chip failing in silicon.
The first speaker covers enhancing reliability with accurate noise measurement and modeling. Precise noise data in device modeling is critical to design and manufacturing success. In the massively complex devices we just described, accurately accounting for noise is essential for ensuring reliability. You will learn how noise data across the wafer can serve as an early indicator of device performance, particularly in low-signal applications such as communications circuits, quantum computing, and image processing. Keysight will walk you through using the company’s Advanced Low-Frequency Noise Analysis (ALFNA). And you will get a first-hand look at how easy it is to use the system to measure and analyze 1/f and Random Telegraph Noise from DC to 100MHz, enabling you to refine designs and boost overall reliability. Key takeaways include:
The impact of precise noise modeling on device reliability and performance
How Keysight’s ALFNA system can improve noise data integration and analysis
Next, you’ll learn how to streamline your device modeling workflow to help you avoid respins with automated binning model extraction. As devices become smaller and more complex, traditional global models often fall short in accuracy. You’ll see how binning models offer improved precision—which is critical to the success of your complex designs—and how you can streamline the difficult and time-consuming process of developing them. A Keysight engineer will conduct a live demonstration of an automated extraction flow that enhances binning model efficiency. This will include showing you how Keysight automation techniques and fast QA methods simplify and accelerate the binning process. Key takeaways include:
Techniques for automating binning model extraction to avoid costly respins and enhance modeling efficiency
Strategies to streamline the QA process and accelerate model development
So, if rising device complexity and shrinking process nodes make you anxious about functional flaws or bugs getting away and causing re-spins, this webinar will hopefully lower your stress levels. The advanced device modeling tools and techniques covered by Keysight experts are not only easy-to-use but can also significantly improve device reliability and prevent costly design errors.
Many of you are already familiar with Silicon Catalyst and the value it brings to semiconductor startups, the industry and the electronics industry at large. Silicon Catalyst is an organization that supports early-stage semiconductor startups with an ecosystem that provides tools and resources needed to design, create, and market semiconductor solutions. It is the only incubator + accelerator focused on the Global Semiconductor Industry and operates with the motto “It’s about what’s next.”
Overall Tech Trends: Inspiration for Quantum and beyond
In keeping up with its motto, Silicon Catalyst invited Dr. Mena Issler from McKinsey and Company to talk about Frontier Technology Trends, at its recent Q3 Advisor & Investor meeting. Mena is an Associate Partner at McKinsey & Company and is one of the authors of “
Some Highlights from Mena’s talk
In 2023, technology equity investments fell by 30-40% to around $570 billion due to rising financing costs and cautious growth outlooks. Despite this, investors are focusing on technologies with high revenue potential, recognizing the long-term value in diversifying investments across multiple tech trends.
Generative AI (gen AI) has emerged as a standout trend, seeing a sevenfold increase in investments since 2022. Its capabilities have expanded dramatically, with large language models (LLMs) now able to process up to two million tokens, powering advancements in text, image, video, and audio generation. Gen AI is being integrated into enterprise tools for diverse applications such as customer service, advertising, and drug discovery, fueling a broader AI revolution and spurring innovations in applied AI and machine learning.
Gen AI’s rapid evolution is also driving advancements in robotics, with AI-powered robots becoming more capable and widely deployed across industries. Robotics was added to McKinsey’s 2023 tech trend analysis, reflecting its growing significance as AI technologies improve and expand robotic capabilities, making automation smarter and more efficient.
Job postings for tech-related roles declined by 26% in 2023, largely due to layoffs in the sector. However, trends like Gen AI continued to see demand for talent, with overall tech job postings up 8% from 2021, indicating long-term growth potential. Interest and innovation across 15 key tech trends remain strong, with AI and renewable energy leading the charge in Investment growth and overall investment, respectively.
This is all food for thought as we start to build and prepare for quantum and semiconductor’s future. To learn more about the latest tech trends, check out the McKinsey report.
Quantum Technologies
With the bulk of technology news these days centered around Artificial Intelligence (AI), it is easy to lose sight of other fast advancing technologies and trends. One such space is the field of quantum technologies. Silicon Catalyst stays on top of things through various means with the incubator’s annual Silicon Startups Contest conducted in partnership with Arm – being one. The overall top winner of the 2023 Contest, conducted by Silicon Catalyst in partnership with Arm, is Equal1, a quantum computing company from Ireland. Over the last two quarters, Silicon Catalyst has received a flurry of quantum space applicants to its incubator program. A couple of recent applicants are currently going through the review process for consideration for admittance into the incubator.
Quantum Computing utilizes quantum properties to process information and perform simulations, offering exponential performance improvements over classical computers in specific applications.
Quantum Communication involves the secure transfer of quantum information over distances, using optical fiber or satellites, with potential to ensure secure communication even against quantum computing attacks. Quantum Key Distribution (QKD) is a secure communication method using quantum technology to protect data against potential attacks by quantum computers.
Quantum Sensing enables ultra-sensitive measurements of physical quantities, surpassing classical sensors in accuracy, with applications in navigation, bio-imaging, and semiconductor manufacturing.
Recent Developments
Recent developments in quantum technologies include significant progress in error correction, full-stack integration, information security, and partnerships. Harvard, MIT, QuEra, and NIST demonstrated algorithms on 48 logical units with error rates below 0.5%, and Microsoft and Quantinuum achieved four reliable qubits with an error rate below 0.01%. IBM and Google also advanced in logical qubit storage and error reduction. These steps push the field toward higher-quality, scalable qubits.
In cybersecurity, companies are strengthening encryption systems to counter potential quantum threats, particularly “harvest now, decrypt later” attacks. Postquantum cryptography is being deployed as a proactive defense.
Bridging Quantum Technology and Real-world
Start-up partnerships with conventional enterprises are also expanding, such as Rolls-Royce’s collaboration with Riverlane to develop quantum algorithms for material discovery in hostile environments. Such partnerships aim to bridge the gap between quantum technology and real-world applications.
Quantum Ecosystem Required to Accelerate Market Growth
While investments into quantum technology startups, the number of such startups and the total governmental investments toward quantum all increased year-on-year, there are still many challenges to overcome. An elaborate and strong ecosystem is needed to catalyze growth and market adoption of quantum technologies. The chart from McKinsey & Company, below identifies the various partner categories required of such a quantum ecosystem.
Summary
For any entrepreneur with a groundbreaking idea in semiconductor technology, Silicon Catalyst offers the ideal environment to turn that idea into reality. Through its extensive network of partners, advisors, mentors, and industry resources, it provides startups with a unique advantage in navigating the complexities of semiconductor development. By joining Silicon Catalyst, startups not only gain access to essential tools and expertise but also become part of a global network that is driving the future of technology.
As for what is next, Silicon Catalyst is looking to build out an ecosystem of design tools, refrigeration systems and cryostat equipment to support and nurture early stage startups in the quantum space.
To learn more, visit SiliconCatalyst.com. You can meet Silicon Catalyst Partners at the Quantum to Business (Q2B) conference, December 10-12, 2024 at the Santa Clara Convention Center. Those interested in further information about Silicon Catalyst-Quantum activity, please send a note to quantum@sicatalyst.com to receive a special Q2B conference registration discount from Silicon Catalyst.
Silicon Carbide (SiC) is the superhero EV converters need, boosting efficiency, shrinking component sizes, and letting your car charge faster while handling heat like a pro. Even Tesla’s like, “Yep, we’re using it,” because who doesn’t want more range and less sweating under the hood?
Get ready for an electric ride in 2024! Global EV sales are set to zoom to between 15-17.5 million units, a 27% surge over last year. Leading the pack, China’s cranking out 9.1 million EVs—nearly 52% of all car sales—thanks to their battery tech wizardry and slick charging infrastructure. Europe’s sparking up too, with 3.9 million EVs projected, as the region shifts from government push to consumer pull. North America’s jumping in with 2.2 million units sold 1, expanding its charging grid and adding more SUVs and trucks to the mix. Buckle up—it’s going to be electrifying!
But, with all the excitement about clean driving and cutting emissions, there’s still one thing holding everyone back—range anxiety. Yes, the dreaded fear that your battery will fizzle out right when you’re miles from a charging station. Don’t worry, though; the solution isn’t about making bigger batteries or building more chargers (although that helps); it’s actually all about… a meteorite and a French chemist who thought he discovered a huge diamond deposit. Yes you heard me well: a meteorite 2… We are not in a movie but in the real world and the hero is called SiC.
EVs and SiC: A Love Story Who started in a Galaxy far, far away
Meet silicon carbide (SiC), a material that’s older than our solar system 3, literally. It’s not just space rock bling; it’s also a superhero when it comes to semiconductors. This stuff has been quietly sitting in the background while we were all obsessed with silicon devices, but now it’s finally stepping into the limelight. And SiC couldn’t have picked a better co-star than EVs. Together, they make the perfect power couple—like electric peanut butter and jelly.
So, why is SiC such a game-changer? Unlike widespread silicon, which is kind of basic at this point, SiC can handle electrical fields up to ten times stronger. That means it’s ideal for handling the high-powered energy demands of EVs. Think of it as silicon’s stronger, more resilient cousin. Plus, SiC doesn’t break a sweat when it comes to heat dissipation or power conduction. It’s like the superhero who shows up to save the day and doesn’t even get its cape dirty.
Faster, Lighter, Stronger: SiC to the Rescue!
By plugging SiC into an EV’s inverter, you can actually squeeze up to 10% more range 4 out of that battery. You know what that means: fewer panicked searches for charging stations! SiC is also a big fan of going small. It allows engineers to shrink the size and weight of power systems, which then results in a lighter car. A lighter EV means a longer driving range and, let’s be honest, nobody likes a chunky car. So, SiC trims the EV down, making it leaner and more efficient on the road.
Representation of a smaller and sleeker charger using SiC
But wait, there’s more! SiC also speeds up charging, allowing for that sweet switch from 400V to 800V battery systems. Faster charging means more time zooming around and less time staring at a charger while sipping overpriced coffee. Silicon Carbide (SiC) in fast chargers is like giving your EV a turbocharged energy drink! It boosts efficiency by reducing power loss, meaning more juice goes to your car instead of heating up the charger. SiC has many aces up its sleeve, enabling higher voltage operation that chops down charging times and making your EV ready to go in record time. And the bonus? It lets chargers be smaller and sleeker, fitting more power in a compact package.
Sure, SiC parts are pricier than regular silicon, but the trade-off is worth it: fewer cooling headaches, smaller components, and chargers that are both lighter and more powerful.
In the world of EV fast charging, where every minute counts, SiC technology is the ultimate power move. When you are charging up for a road trip, SiC makes sure your charger runs faster, cooler, and smarter—because nobody’s got time to wait around when there’s a road ahead! So yes, SiC is basically EV magic dust.
EV Converters: SiC steals the Show
Not only is SiC great at pumping miles fast into the battery, but it’s also the MVP when it comes to take those miles out though the power converters 5—the unsung heroes that turn battery juice (DC) into motor power (AC), giving them superpowers compared to boring old silicon (Si). Why? Because SiC is the overachiever in the classroom—it’s more efficient, tougher, and just plain cooler.
Tesla is the first high-class car manufacturer to integrate a full SiC power module, in its Model 3 (Yole Group)
First off, SiC is great at making sure your EV’s battery power actually gets to the motor, instead of being wasted as heat. This means more range, which every EV driver loves. Plus, the magic of SiC is that you can shrink the inverters down because power losses are lower, and devices are smaller than IGBT, allowing for more compact power converters, saving EV weight. Think of it as putting your car on a sleek, tech-savvy diet!
SiC can also handle higher temperatures without throwing a tantrum, which means your EV doesn’t need a complicated cooling system. It’s like having a car that doesn’t sweat the small stuff—literally. This makes everything simpler, cheaper, and more reliable.
Tesla got the memo way back in 2018 when they slapped SiC into the converter of their Model 3, and since then, the EV industry has been on board. By 2033, SiC MOSFETs are expected to dominate the EV inverter market 6. Prepare for a world where “SiC” becomes as well-known as “Wi-Fi”!
Soitec’s SmartSiC™: The Shiny New Superstar in Town
While SiC is amazing, Soitec’s SmartSiC™ is like SiC with a PhD. Soitec didn’t just take SiC and slap it into EVs; they gave it a makeover, making SiC still more powerful and skillful. Their SmartSiC™ substrate uses ten times less material than regular SiC, which is great news because SiC isn’t exactly lying around in abundance. But here’s the kicker: SmartSiC™ boosts performance by over 20%. So, less material, better performance—it’s like upgrading from dial-up internet to fiber optics, but for your car.
SmartSiC™ also plays a big role in the sustainability game. For every million wafers produced, it saves 40,000 tons of CO2 emissions 7. That’s like planting a tree every time you roll out a batch (25 wafers) of SmartSiC chips. Using SmartSiC™ equals fewer emissions, and higher efficiency. That’s more than win-win!
The Future of EVs and SiC: Saving the Planet, One Charge at a Time
As EVs continue their meteoric rise, SiC is going to be their trusty sidekick. And with innovations like Soitec’s SmartSiC™, we’re not just talking about more efficient EVs; we’re talking about a greener, more sustainable planet. SiC and SmartSiC™ are poised to revolutionize the EV industry, with longer ranges, faster charging, and lighter cars all in the cards.
In the race to decarbonize, SiC might just be the little bit of stardust we need to keep us on track. So, next time you plug in your EV, just remember: it’s powered by stars and some pretty smart engineering. And if you’re lucky, maybe Soitec’s SmartSiC™ is behind the wheel, giving your car a boost and saving the world one charge at a time.
Sources:
1 Canalys – Global EV market forecasted to reach 17.5 million units with solid growth of 27% in 2024 2 Wikipedia – Moissanite 3 Jim Kelly – The Astrophysical Nature of Silicon Carbide 4 Frost & Sullivan – The transition of Electric Mobility from 400V to 800V Architecture – An Inevitable move towards WBG semiconductors. 5 Electronic Office Systems – Are all EVs equipped with an on-board AC/DC Converter, or does this depend on the vehicle model? 6 IDTechEx – Power Electronics for Electric Vehicles 2023-2033: Technologies, Markets, and Forecasts 7 Medium – Vehicles of The Future: Emmanuel Sabonnadiere Of Soitec On The Leading Edge Technologies That Are Making Cars & Trucks Smarter, Safer, and More Sustainable
At the 2024 TSMC OIP Ecosystem Forum, one of the technical talks by TSMC focused on maximizing 3DIC design productivity and rightfully so. With rapid advancements in semiconductor technology, 3DICs have become the next frontier in improving chip performance, energy efficiency, and density. TSMC’s focus on streamlining the design process for these cutting-edge solutions has been critical, and 3DBlox is central to this mission. 3DBlox is an innovative framework inclusive of a standardized design language, introduced by TSMC aimed at addressing the complexities of 3D integrated circuit (3DIC) design. The following is a synthesis of that talk, delivered by Jim Chang, Deputy Director at TSMC for the 3DIC Methodology Group.
Progress from 2022 to 2023: Laying the Foundations for 3DBlox
In 2022, TSMC began exploring how to represent their 3DFabric offerings, particularly CoWoS (Chip-on-Wafer-on-Substrate) and INFO (Integrated Fan-Out), which are critical technologies for 3DIC. CoWoS integrates chips using a silicon interposer, while INFO uses RDL (Redistribution Layer) interposers. TSMC combined these approaches to create CoWoS-R, replacing the silicon interposer with RDL technology, and CoWoS-L, which integrates local silicon interconnects.
With these building blocks in place, TSMC realized that they needed a systematic way to represent their increasingly complex technology offerings. This led to the creation of 3DBlox, which provided a standard structure for representing all possible configurations of TSMC’s 3DFabric technologies. By focusing on three key elements—chiplets, chiplet interfaces, and the connections among interfaces—TSMC was able to efficiently model a wide range of 3DIC configurations.
By 2023, TSMC had honed in on chiplet reuse and design feasibility, introducing a top-down methodology for early design exploration. This methodology allowed TSMC and its customers to conduct early electrical and thermal analysis, even before having all the design details. Through a system that allowed for chiplets to be mirrored, rotated, or flipped while maintaining a master list of chiplet information, TSMC developed a streamlined approach for design rule checking across multiple chiplets.
Innovations in 2024: Conquering Complexity with 3DBlox
By 2024, TSMC faced the growing complexity of 3DIC systems and devised new strategies to address it. The key innovation was breaking down the 3D design challenge into more manageable 2D problems, focusing on the Bus, TSVs (Through-Silicon Vias), and PG (Power/Ground) structures. These elements, once positioned during the 3D floorplanning stage, were transformed into two-dimensional issues, leveraging established 2D design solutions to simplify the overall process.
Key Technology Developments in 2024
TSMC’s focus on maximizing 3DIC design productivity in 2024 revolved around five major areas of development: design planning, implementation, analysis, physical verification, and substrate routing.
Design Planning: Managing Electrical and Physical Constraints
In 3DIC systems, placing the Bus, TSVs, and PG structures requires careful attention to both electrical and physical constraints, especially Electromigration and IR (EMIR) constraints. Power delivery across dies must be precise, with the PG structure sustaining the necessary power while conserving physical resources for other design elements.
One of TSMC’s key innovations was converting individual TSV entities into density values, allowing them to be modeled numerically. By using AI-driven engines like Cadence Cerebrus Intelligent Chip Explorer and Synopsys DSO.ai, TSMC was able to explore the solution space and backward-map the best solutions for bus, TSV, and PG structures. This method allowed designers to choose the best tradeoffs for their specific designs.
Additionally, chip-package co-design was emphasized in 2024. TSMC collaborated with key customers to address the challenges of coordinating between the chip and package teams, which previously operated independently. By utilizing 3DBlox’s common object format and common constraints, teams could collaborate more efficiently, settling design constraints earlier in the process, even before Tech files were available.
Implementation: Enhancing Reuse and Hierarchical Design
As customers pushed for increased chiplet reuse, TSMC developed hierarchical solutions within the 3DBlox language to support growing 3DIC designs. With the increasing number of alignment marks required to align multiple chiplets, TSMC worked closely with EDA partners to identify the four primary types of alignment markers and automate their insertion in the place-and-route flow.
Analysis: Addressing Multi-Physics Interactions
Multi-physics interactions, particularly related to thermal issues, have become more prominent in 3DIC design. TSMC recognized that thermal issues are more pronounced in 3DIC than in traditional 2D designs due to stronger coupling effects between different physical engines. To address this, TSMC developed a common database that allows different engines to interact and converge based on pre-defined criteria, enabling efficient exploration of the design space.
One of the critical analysis tools introduced in 2024 was warpage analysis, crucial as the size of 3DIC fabric grows. TSMC developed the Mech Tech file, defining the necessary information for industry partners to facilitate stress simulation, addressing a gap in warpage solutions within the semiconductor industry.
Physical Verification: Ensuring Integrity in 3DIC Designs
TSMC tackled the antenna effect, a manufacturing issue where metal may accumulate plasma charges that can penetrate gate oxides via TSVs and bumps. By collaborating with EDA partners, TSMC created a design rule checking (DRC) deck that models and captures the antenna effect, ensuring it can be accounted for during the design process.
In 2024, TSMC also introduced enhancements in layout vs. schematic (LVS) verification for 3DIC systems. Previously, LVS decks assumed a one-top-die, one-bottom-die configuration. However, 3DBlox’s new automated generation tools allow for any configuration to be accurately verified, supporting more complex multi-die designs.
Substrate Routing: Tackling the Growing Complexity
As 3DIC integration grows in scale, so does the complexity of substrate routing. Substrate design has traditionally been a manual process. The growing size of substrates, combined with the intricate requirements of modern 3DIC designs, necessitated new innovations in this space.
TSMC’s work on Interposer Substrate Tech file formats began three years ago, and by 2024, they were able to model highly complex structures, such as the inclusion of tear drops in the model. This advancement offers a more accurate and detailed representation of substrates, crucial for the larger and more intricate designs emerging in the 3DIC space. TSMC worked with their OSAT partners through the 3DFabric Alliance to support this format.
Summary: 3DBlox – Paving the Way for 3DIC Innovation
TSMC’s 3DBlox framework has proven to be a crucial step in managing the complexity and scale of 3DIC design. From early exploration and design feasibility in 2023 to breakthroughs in 2024 across design planning, implementation, analysis, physical verification, and substrate routing, TSMC’s innovations are paving the way for more efficient and scalable 3DIC solutions. As the industry moves toward even more advanced 3D integration, the 3DBlox committee announced plans to make the 3DBlox standard publicly available through IEEE. 3DBlox will continue to play a vital role in enabling designers to meet the increasing demands of semiconductor technology for years to come.
– SPIE Photomask -all about High NA and bigger masks
– High NA will ramp very fast & is ramping fast – two already at Intel
– Doubling size of photomask will offset High NA exposure size problem
– Assembling litho tools at customer saves time/money- “Scanner Kits”
Christophe Fouquet of ASML
The new CEO of ASML, Christophe Fouquet gave a great opening/keynote speech which centered around High NA EUV.
Its clear that that High NA EUV will not likely have any of the delays that plagued the original EUV roll out. We should expect a relatively rapid rollout and adoption as High NA is more of an “upgrade” to EUV rather than a whole new product .
Christophe spoke about the new methodology of assembling scanner sub components at the customers site rather than assembling them at ASML only to take them apart and reassemble the tool a second time at the customer site.
This has already been done for less complex dep and etch tools and similar tools for a while now but doing it with a high complex litho tool is another thing entirely. But it will save a ton of time and money. This will add to the acceleration of High NA.
Mix and match lens assemblies in the future
The only real difference between a regular EUV tool and a High NA tool is the lens stack, so if you design a tool where the lens stack is in the middle you could swap in regular EUV lenses, High NA lenses or Hyper NA lenses into the same basic tool.
It makes for a ton of commonality , more cost savings, simplicity etc. The modular approach that ASML is taking is supporting this approach.
It will clearly help costs, margins and install times.
Also mentioned during the presentation is that ASML is up to a solid 740 watt source in San Diego with a clear path to 1000 Watts.
All in all, Christophe did a great job in one of his first major public appearances since taking the reigns. His overall overview was great.
Big masks are a “no brainer”- Christophe Fouquet
The idea of doubling mask size from 6″X6″ to 6″X12″ was started in earnest at last years SPIE by Intel. It picked up a lot of speed and support at this years conference with many companies in the Photomask infrastructure signing on to the effort. Chief among those , and key, was ASML (Chritophe) calling the adoption of double size masks a “no brainer” for the industry throwing ASML’s huge weight behind the change.
It also makes obvious sense for ASML as it helps overcome the die size limitation of High NA. The 40% performance improvement is well worth the switch alone
Mark Phillips of Intel underscored the High NA message
Mark Phillips of Intel followed Christophe Fouquet to continue the High NA theme. Intel now has two installed/working High NA systems in Portland.
Mark showed some very nice images from both of the systems, that show the improvement that High NA brings over standard EUV which may be better than expected. The install of the second system went faster than the first as there has been learning.
Its important to note that all the infrastructure that High NA needs is already in place and working. Actinic mask inspection for High NA is already working. So there is not much ancillary support work to be done to get it into production.
Mark was also asked a question about CAR (chemically amplified resists) versus Metal Oxide resists and he said that CAR is fine for now but that we may need metal oxide some time in the future. This seems to push out significantly the need for metal oxide resists such as Lam’s dry resist , much further into the future . Not good news for JSR or Lam.
The targeted insertion point is the Intel 14A process which will be in about 3 years, which again is likely faster than expected.
(The only glitch we heard about at the conference about High NA was that getting the huge High NA tools off the tractor trailer into the fab in Portland was problematic as the trailer bent under the extreme weight load!)
This near flawless install/turn on is good news for Intel as it is a needed “win” for their execution plans especially after being slow to the original EUV rollout
TSMC playing hard to get on High NA but will be forced to come along
As compared to its quick embrace of the original EUV rollout, TSMC has been slow to embrace High NA citing its cost. In our view, this is a bit of a positioning/negotiating game on the part of TSMC perhaps gaming for better terms from ASML.
We don’t think they will hold out very long especially if Intel starts to get a lead on High NA tools. TSMC will have to cave in and go along. TSMC has also been slow on the mask doubling Intel has championed but will also eventually go along as its a free performance increase for them.
Rumors at the conference
We heard that Christophe Fouquet of ASML and Anne Kelleher of Intel got together on Sunday before the conference opened…perhaps to talk about their partnership on the High NA rollout.
We think there may be some good news on the horizon for KLA and its long delayed Actinic mask inspection program, which is well needed.
The Stocks
We would view the conference as obviously very positive for the rollout of High NA EUV and the overall technology progress of Moore’s Law.
It was obviously positive for both Intel and ASML. Certainly good for Intel that needs all the technology wins it can get and High NA is perhaps the most critical technology change the industry is currently undergoing.
Its also positive for ASML as the stock has been shaky and under pressure in large part due to the China issue which has overshadowed the larger technology progress on High NA.
On the larger semiconductor market, it remains all about AI, AI and AI….nothing much else matters.
Trailing edge remains weak as everything revolves around AI.
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