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Last Call: Why Your Real‑World Lessons Belong in DAC 2026’s Engineering

Last Call: Why Your Real‑World Lessons Belong in DAC 2026’s Engineering
by Admin on 01-15-2026 at 6:00 am
Categories: Events

DAC Call for Contributions 2026

By Frank Schirrmeister, Synopsys
Disclaimer: This article is written in my role as Engineering Track Chair for DAC 2026

If you’ve ever walked out of DAC with a handful of practical ideas you could put to work when you return to work, you already know the value of the Engineering Track. It’s where practitioners talk to practitioners – front‑end to back‑end, IP to systems & software – about what actually shipped, what almost derailed, and what really worked.

With DAC 2026 heading to Long Beach this year (July 26–29), the submission window gives you one more week to get your story into the program: the Engineering Track Call for Contributions closes on January 20, 2026.

DAC’s Engineering Track = The Workbench of the Conference

Think of the Engineering Track as the place where the industry checks claims against data. The four pillars are well‑known:

Front‑End Design, Back‑End Design, IP, and Systems & Software.

The bar for acceptance is pragmatic impact reviewed by your industry peers: integration experience, deployment lessons, measurable outcomes. This is curated by a large Technical Program Committee – we are about 150 reviewers strong this year – precisely to keep sessions practical, concise, and dense with takeaways.

For 2026, DAC is doubling down on that ethos. The official call emphasizes practical insights and real‑world experiences across the design ecosystem, and you have until January 20th to submit your experiences.

What’s Hot – and Why Your Experience Matters Now

First, Agentic AI is moving into mainstream workflows. At DAC62, the buzz wasn’t just “AI in EDA,” it was agentic AI – multi‑agent systems reasoning over flows, data, and constraints. The Microsoft Monday keynote spotlighted reasoning agents, and live demonstrations showed agents collaborating autonomously on parts of a chip design flow.

The consensus: agents can tame complexity, but humans remain firmly in the loop for sign‑off and safety. If you’ve piloted LLMs or agents in verification, synthesis exploration, debug, or collateral generation, the community wants the gritty details—wins, misses, cost curves, and guardrails.

Zooming in, last year’s Engineering Track special session “AI‑enabled EDA” assembled startup and industry voices (ChipStack→Cadence, Silimate, Rise, ChipAgents, VerifAI, Bronco AI, VerifAIX).

The through‑line? Move beyond script helpers to agent‑driven reasoning across the silicon lifecycle. If you’ve tried that jump (even partially), your evidence—coverage movement, regression stability, debug time, data hygiene—will land well for the DAC 2026 Engineering Track.

Second, Chiplets and multi‑die aren’t hypothetical anymore. From the Chiplet Pavilion to tool vendor panels, DAC62 made clear: heterogeneous packaging, 3D‑IC, and chiplets are scaling fast – and the bottlenecks are integration discipline and automation.

The industry’s discussions around “SoC Cockpit” automation, dedicated chiplet content, and panel takeaways all point to flows that must span system spec to signoff with tighter feedback loops.

What has your team learned about interposer modeling, package‑aware verification, DFT for multi‑die, or HBM timing closure under realistic workloads? Bring the receipts.

Third, Software‑defined systems reshape verification and bring‑up. Automotive and aerospace teams at DAC62 described accelerating pre‑silicon software bring‑up using emulation, virtual models, and scenario‑based validation – because lifetime validation and OTA‑driven features demand it.

If you’ve connected emulation/prototyping to CI/CD, instrumented performance/power at scale, or fused virtual platforms with lab rigs, those “how we wired it” details are gold for peers as part of the Engineering Track in 2026.

Finally, the AI imperative touches the whole stack. Arm’s SKYTalk at DAC62 framed AI as a systems problem: technology leadership, a complete systems approach, and a robust ecosystem. That systems lens maps perfectly to the Engineering Track: cross‑discipline integration stories beat single‑point heroics every time.

If you navigated cross‑org collaboration (IP vendors, foundry, cloud, toolchains) to make an AI workload viable, that’s exactly the content the Engineering Track is built to surface.

What a Strong Engineering Track Submission Looks Like

SemiWiki readers gravitate to specifics: numbers, tooling, and lessons learned. So do DAC’s reviewers. Across the four categories, consider framing your six-page abstract submission using this structure:

  • Problem & context. One page: node, die count, workload class, volume/latency/latency‑jitter, safety/security constraints. If applicable, cite DAC alignment – AI agents, chiplets, SW‑
  • Approach & toolchain. Call out the stack – simulation + emulation, prototyping, virtual platforms, physical signoff, package/thermal analysis, LLM/agent frameworks, data backplane. Reviewers will assess architectural clarity.
  • Evidence & metrics. Be precise: % timing slack improvement post‑package‑aware optimization; coverage delta via agent‑generated tests; regression throughput speedups (x‑fold) after moving to hardware‑assisted verification; power/perf shifts under production workloads. The various DAC62 recaps made clear: people are quantifying their results.
  • Pitfalls & playbook. What failed first? Data cleanliness, model fidelity, agent drift, spec/versioning? Turn your scar tissue into a 3–5 step “do this first” list.

Remember, DAC 2026 is Chips to Systems end‑to‑end.

The conference is explicitly inviting contributions that span disciplines, not just point optimizations.

Special Sessions: Curate the Cross‑Cutting Conversations

Beyond standard talks and posters, Engineering Track Special Sessions can stitch together themes like Agentic AI across the flow, From executable spec to multi‑die signoff, or Software‑defined validation at scale. The 2025 panel on AI‑enabled EDA startups drew strong interest because it packed diverse, hands‑on perspectives. If you can convene 3–5 voices (user + tool + ecosystem), you’ll help frame where practice is heading in 2026.

Final Nudge: Your Story Will Help Someone Ship

The best DAC Engineering Track talks I’ve seen aren’t victory laps; they’re honest accounts where a team wrestled with modern complexity – agents in the loop, multi‑die realities, software‑defined validation – and found a pattern worth sharing.

DAC62 proved the appetite is huge: agentic AI is advancing quickly, chiplets are mainstreaming, and the community is aligning on systems‑level thinking.

Now it’s your turn to add to that collective playbook.

Submit by January 20 and bring your hard‑won lessons to the people who will put them to work. Start here for the Engineering Track Submissions, and here for the Engineering Track Special Sessions.

See you in Long Beach!

Disclaimer: This article is written in my role as Engineering Track Chair for DAC 2026

Also Read:

CES 2026 and all things Cycling

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2026 Outlook with Randy Caplan of Silicon Creations

2026 Outlook with Randy Caplan of Silicon Creations
by Daniel Nenni on 01-14-2026 at 10:00 am
Categories: IP, Silicon Creations

randy caplan

Randy Caplan is co-founder and CEO of Silicon Creations, and a lifelong technology enthusiast. For almost two decades, he has helped grow Silicon Creations into a leading mixed-signal semiconductor IP company with 500+ customers spanning almost every major market segment. He has driven the development of key technologies for over 700 unique SerDes and PLL IP products, in all mainstream manufacturing nodes from 350nm down to 2nm. He is well known for his promotion of an organic growth model for business and has helped guide Silicon Creations to an average annual growth rate of 25% for the past decade, with nearly 100% employee retention. Prior to Silicon Creations he was a design engineer for PLLs and SerDes at Agilent Technologies, Virtual Silicon, and MOSAID.

Tell us a little bit about yourself and your company.

Silicon Creations is a mixed-signal IP provider, specializing in low-risk, high performance clocking solutions (PLLs), high speed data interfaces (SerDes), and accurate temperature and voltage sensors. We offer designs in every foundry (TSMC, Samsung, GF, Intel, Rapidus, UMC, SMIC, and more…), and every process node (below 2nm up to 180nm, all inclusive). We were founded in 2006, are ISO9001 certified, and after 19 years, still have close to 100% employee retention.

What was the most exciting high point of 2025 for your company?

Passing 14 million (TSMC) wafers shipped using our IP. Also, we passed our 1000th production license of our Fractional SoC PLL IP.

We developed, taped out, and tested a portfolio of 2nm TSMC IP including multiple PLLs, free-running oscillators, low-noise IOs, and temperature sensor IP. We also developed select 2nm PLLs with multiple other foundries including Samsung, Intel, and Rapidus.

What was the biggest challenge your company faced in 2025?

Simultaneously developing IP in all the leading process nodes (TSMC, Samsung, Intel Foundry, Rapidus). This required new design techniques to support core-device-only requirements in GAA (gate-all-around) nano-sheet / nano-wire processes.

How is your company’s work addressing this biggest challenge?

Chip development costs in advanced nodes have gone up exponentially. We provide a substantial portfolio of low-risk, proven, foundational IP which helps enable our customers to get their designs right the first time. Our advanced design and verification flow enables fast iteration and re-verification in processes where PDKs are frequently changing. This ensures we’re not the bottleneck in our customers’ development schedule.

What do you think the biggest growth area for 2026 will be, and why?

We’re seeing growth in many parallel market segments including AI accelerator chips, consumer electronics (AR/VR/mobile), and automotive. Customer tapeouts in advanced nodes (5nm and below) are picking up. We’re even seeing active development in sub-2nm nodes. Due to long chip development schedules and fab times in advanced nodes, our IP sales tend to be a strong leading indicator of chip sales one to two years in the future. We don’t have first-hand knowledge of the end market forces, but we can infer from our IP sales which semiconductor market segments are seeing increased investment now.

How is your company’s work addressing this growth?

We use an advanced IP design flow, leveraging the latest EDA flows from Synopsys, Cadence, Siemens, Silvaco, and others. This helps to reduce IP development time, improve simulation-to-silicon correlation, and ensure our customers have the foundational blocks they need to build their high-performance chips.

What conferences did you attend in 2025 and how was the traffic?

All TSMC shows, ICCAD (China), DAC and many other foundry and EDA events (Samsung, GF, Intel, Siemens U2U, CadenceLive). Traffic was especially strong at TSMC and ICCAD, but we also had a good turn-out at our booth for the other events as well.

Will you attend conferences in 2026? Same or more?

Silicon Creations attended over 30 trade shows / conferences in 2025 and expects to attend a similar number in 2026.

How do customers engage with your company?

We already work with 18 of the top 20 TSMC customers, and over 550 companies overall. For new inquiries, please send an email to sales@siliconcr.com, or come to our booth at any trade show.

Also Read:

Silicon Creations Company Update 2025

Silicon Creations at the 2025 Design Automation Conference #62DAC

Silicon Creations Presents Architectures and IP for SoC Clocking

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Where is Quantum Error Correction Headed Next?

Where is Quantum Error Correction Headed Next?
by Bernard Murphy on 01-14-2026 at 6:00 am
Categories: 3D IC, Quantum Computing

quantum computer and QEC coprocessor min

I have written earlier in this series that quantum error correction (QEC), a concept parallel to ECC in classical computing, is a gating factor for production quantum computing (QC). Errors in QC accumulate much faster than in classical systems, requiring QEC methods that can fix errors fast enough to permit production applications. I have read of leaders in the field using FPGAs or GPUs to support QEC, which to me sounded intriguing but also difficult to scale for several reasons. Qubits can’t exist in the classical regime, seeming to imply that they must be collapsed prior to transfer, which would destroy carefully constructed superpositions and entanglement. Communication to an external chip (and back again after calculation) must travel through bulky and constrained channels with significant latencies, particularly in superconducting QC. On the return trip into the QC, the corrected qubit would need to be reconstructed. Would all this added latency undermine performance expectations for a production algorithm?

What’s really happening in QEC today

It took quite a bit of digging, including an excursion into ChatGPT (surprisingly helpful in response to a very technical question), to figure out what is really happening: a more refined partitioning than I had understood for information to be communicated off-chip, and an acknowledgement that FPGA and GPU methods are widely used but temporary expedients, allowing QC builders to research and refine QEC techniques, but not expected to survive as a part of production fault tolerant systems.

First, the primary qubits on chip aren’t measured. The additional qubits used for QEC can be measured, and that data can be communicated to an off-chip device. Said device figures out what corrections must be made per qubit, communicates that back to the QC, where quantum circuitry takes over again to apply those corrections by a mechanism which does not break coherence.

Second, latencies in this path can be significant. High noise rates require frequent correction, but frequency is limited by those latencies. Equally this limits the number of qubits that can be managed (qubits X latency all needing to channel out to the coprocessor and back again) This is why, useful though FPGA and GPU are as QEC co-processors today, they are not seen as long-term solutions for production QEC algorithms.

From prototypes to production QEC support

All prototyping systems eventually evolve to ASICs unless prototype performance is adequate and volumes are not expected to be high. Since QC vendors aim for high performance and (eventually) high qubit count, they too are planning ASICs for QEC. But these must sit very close to the QC core to minimize communication overhead. Which puts them in or very close to the deep cooling cavity for superconducting QCs. IBM plans a QEC core built with cryogenic CMOS, I’m guessing on the bottom layer in their 3D-stack architecture: qubits on the top-layer, resonators on the middle layer, and QEC on the layer under that.

This is very nice technology advance. I don’t know where other QC vendors and technologies are at in this race, but I have to believe IBM QC, already a dominant player in the QC market, is aiming to further widen its lead.

Usual caveat that this is a fast-evolving market and promises aren’t yet proven deliverables. Still, keep a close eye on IBM!

Also Read:

2026 Outlook with Nilesh Kamdar of Keysight EDA

Verifying RISC-V Platforms for Space

2026 Outlook with Paul Neil of Mach42

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2026 Outlook with Nilesh Kamdar of Keysight EDA

2026 Outlook with Nilesh Kamdar of Keysight EDA
by Daniel Nenni on 01-13-2026 at 10:00 am
Categories: Chiplet, EDA, Keysight EDA

Nilesh Kamdar Show

Tell us a little bit about yourself and your company.
I’m Nilesh Kamdar, General Manager of the Keysight EDA business unit. Keysight is an S&P 500 company that provides design, emulation, and test solutions to help engineers develop and deploy faster with less risk. On the EDA side, we focus on RFMW, high-speed digital, systems, power and photonic design challenges. These are the problems that keep semiconductor and system designers up at night: multi-physics simulation, signal integrity, power consumption, and making sure complex designs work.

What was the most exciting high point of 2025 for your company?

Acquiring Synopsys’ Optical Solutions Group and Ansys’ PowerArtist were high points. Rather than just buying market share, these additions bring innovative optical design capabilities (CODE V, LightTools, RSoft) and leading RTL power analysis (PowerArtist) to our portfolio, addressing the multi-physics imperative. We’re bringing in decades of expertise in photonics, optics, and power analysis, enabling Keysight to deliver multi-domain system design in an open, vendor-agnostic ecosystem. As thermal and power constraints tighten, these capabilities are imperative.

What was the biggest challenge your company faced in 2025?

Helping our customers on their AI journey and ensuring that the technology is carefully and securely deployed. This is often at odds with some in the C-Suite who view AI as the answer to every problem, and that substantial cost savings are inevitable.

How is your company’s work addressing this challenge?

To help our customers, we’re building AI features to solve problems in design workflows – accelerating verification, prioritizing corner-case testing, and reducing manual iterations. Part of this is educating on where AI delivers value and where human expertise remains essential. At Keysight, we believe AI is about augmentation.

What do you think the biggest growth area for 2026 will be, and why?

Multi-physics simulation. As designs push against thermal and power limits, particularly in data centers, the ability to simultaneously analyze electrical, thermal, and mechanical properties has become essential. Every milliwatt matters when data centers consume billions of watts of energy. Tools that optimize across domains will be critical for next-generation designs.

How is your company’s work addressing this growth?

We’re continuing to develop our multi-physics capabilities to improve co-design and co-verification. This includes advancing photonics integration, enhancing thermal analysis capabilities, and ensuring that designers can understand trade-offs across electrical performance, thermal management, and manufacturing constraints within workflows.

Are you incorporating AI into your products?

Keysight has been at the forefront of integrating AI. From an EDA perspective, we’re focused on integrating capabilities that augment productivity in verification and design workflows. Our goal is to harness AI to help engineers work faster while utilizing their unique expertise to design complex semiconductors.

Is AI affecting the way you develop your products?

We’re using AI to accelerate our own development cycles and improve product quality. More importantly, we’re deploying AI judiciously to solve real problems our customers face, such as workflow bottlenecks.

What conferences did you attend in 2025 and how was the traffic?

We attended various industry events spanning DesignCon, DAC (Design Automation Conference), IMS (International Microwave Symposium), DVCon India, ECOC, and European Microwave Week. Traffic was robust across all of these. Conversations focused on detailed implementation discussions around AI-enhanced tools, multi-physics solutions, and chiplet design, where the technical challenges are most acute.

Will you participate in conferences in 2025? Same or more as 2025?

Events remain an important part of our strategy to connect and I don’t see that changing anytime soon. As design complexity increases, face-to-face technical discussions are invaluable!

How do customers normally engage with your company?

There are multiple ways we engage with customers, including direct sales, technical support teams, and field application engineers who work closely with design teams. We also connect through training programs, webinars, and technical content. Personally, I spend a lot of time on the road and engage regularly with customers to understand their perspective. Keysight is solving specific design challenges with our customers, not just selling licenses.

Also Read:

From Silos to Systems, From Data to Insight: Keysight’s Upcoming Webinar on EDA Data Transformation

An Insight into Building Quantum Computers

Podcast EP317: A Broad Overview of Design Data Management with Keysight’s Pedro Pires

Video EP11: Meeting the Challenges of Superconducting Quantum System Design with Mohamed Hassan

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Verifying RISC-V Platforms for Space

Verifying RISC-V Platforms for Space
by Bernard Murphy on 01-13-2026 at 6:00 am
Categories: AI, Breker Verification Systems, EDA, RISC-V

User making a call through a satellite

Space applications are booming, prompted by rapidly declining launch costs now attainable through commercial competition. Thanks to ventures like SpaceX, the cost to put a satellite into low earth orbit (LEO) has dropped from $20k/kg to $2k/kg today and is expected to drop further to $200/kg or lower. Plummeting costs drive new opportunities including widely accessible SATCOM (satellite communication), offering phone and broadband support through large constellations of satellites from Starlink and Amazon Leo (previously Amazon Kuiper). China is also on this bandwagon, building multiple constellations of their own. Standardization through the 3GPP (cellular) consortium is accelerating and will enable competitive interoperability, already partially supported in 5G-Advanced and expected to be fully supported in 6G. This isn’t just for emergency calls but also for regular calls direct to your smartphone. Standards-based phone communication, broadband and IoT support, across 85%+ of the earth’s surface where there are no terrestrial base stations? This is an exciting time for space-ready systems.

Equally space-based services will continue to grow in importance for defense, weather and climate monitoring, disaster support, and many other applications. Across all these deployments, expect to see growth in similar directions to those we see in terrestrial applications: AI, high performance servers, security, and much more. A new space-based economy is blossoming and will demand electronics able to function reliably for many years in this harsh environment.

Space-ready is not just about rad-hard

Radiation, solar and deep space, makes space a particularly hostile environment for electronics. Protection against electron cascades triggered by high energy cosmic rays demands special radiation hardened (rad-hard) processes, logic redundancy, ECC, all the tricks we now see for high-safety automotive systems but in space much more demanding, lacking the shielding our atmosphere provides.

Rad-hard is important but alone it is not enough. Beyond remotely triggered options, electronics in space can’t be serviced cost-effectively. If something stops working and a reset or reboot won’t fix the problem, the satellite is dead. This puts much higher emphasis on bullet-proof verification while the system is still in design. Good enough for a phone, even for a car, isn’t good enough for a satellite.

Comprehensive verification against a spec

Complex specifications present some unique challenges in this respect. According to Dave Kelf (CEO, Breker) the RISC-V International ISA spec runs to around 1400 pages, all carefully considered and agreed. Now you must verify behavior not just for what you added to the ISA but also across interactions with other features, driven by as many positive and corner case use-cases as you can construct.

It is not difficult to generate comprehensive unit test cases for rad-hardening features such as ECC or redundancy. Testing individually against other spec features, one at a time, say cache coherence management, may not be too bad but difficult to test comprehensively. But where testing becomes hard is in cross verifying all relevant use cases against each other. Real systems run many objectives simultaneously, stalling as needed to deal with traffic contention in bus fabrics. Stalls, latency and congestion are where difficult bugs lurk, satellite-dooming bugs. Getting to high confidence here requires system-level test definition, with the ability to run multiple use-cases simultaneously.

Breker’s approach to testing starts with system-level test models abstracted from implementation details, allowing you to easily combine VIPs defined at the same level. Breker themselves offer several VIPs, including RISC-V-related tests, together with tests checking coherency compliance, security and other areas. You can easily add your own models following the PSS standard or using standard C++, allowing for randomization especially around test models for your ISA extensions. Running these models together, generating interwoven and high demand traffic loads, will probe every dark corner of your system behavior.

What if you missed spec corners when building your test models?

The purpose of verification is to test compliance of your implementation with the spec. As a description of what compliance should mean, the RISC-V spec may be one of the more debated and refined specifications in our industry. But there is still a fallible, human step in mapping that document to a complete implementation of intent as represented in a test specification.

As linear documents, even the best and most reviewed of specs are an awkward way to capture a web of interconnected feature dependencies. This is not an academic concern. Dave shared a real challenge in interpreting RISC-V requirements around fence instructions. Quick reminder, these are instructions inserted in assembly code to control accesses to shared memory between multiple cores, which must be correctly ordered to avoid races. Standard coherence protocols can handle many but not all such cases. Special cases are typically application specific, such as a shared memory location used as a semaphore. Core A updates the semaphore indicating it is safe for core B to perform some other action. If core B reads the semaphore before Core A has updated, it may incorrectly assume it is OK to proceed. Adding fence instructions forces sufficient delay to avoid races between read and write.

Coherency bugs can be very challenging to catch, sometimes only appearing after billions of cycles in production. Not the kind of problem you want to see in a deployed satellite. The Breker guys spotted a RISC-V spec challenge that could lead to such a bug (leading one now loyal Breker customer to a redesign). The spec is completely accurate, detailing fence behaviors early in the document. But in a later unrelated part of the document, there is a mention of a fence behavior which is also important to understand, yet is easy to miss if your reading is limited to the earlier section.

Specs are living documents and it is probably unrealistic to expect this kind of problem cannot appear again. A safer approach would be to use AI to tease out such traps and more generally the web of relationships through a spec. I have talked earlier about Breker’s approach to AI, based on NLP rather than LLM. Dave tells me this is still in development, but they have already applied it to detect these distributed fence references in the spec, which it has done very successfully. To me this looks like an essential second step to closing the understanding loop in specs. First make sure the spec is oracle-worthy (not a problem for RISC-V), second make sure that you understand all relationship webs throughout the spec when translating into test models.

Very interesting. You can learn more in this press release on the Breker and FrontGrade Gaisler collaboration

Also Read:

A Principled AI Path to Spec-Driven Verification

RISC-V Virtualization and the Complexity of MMUs

How Breker is Helping to Solve the RISC-V Certification Problem

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2026 Outlook with Paul Neil of Mach42

2026 Outlook with Paul Neil of Mach42
by Daniel Nenni on 01-12-2026 at 10:00 am
Categories: CEO Interviews, EDA, Mach42

Paul's headshot

Tell us a little bit about yourself and your company

I’m Paul, Chief Operating Officer at Mach42. As COO, I am responsible for the business growth of Mach42, as well as driving customer success. My previous roles included VP of Product at Axelera AI, Graphcore and XMOS. I hold a PhD in Electrical Engineering and an MBA in Technology Management.

Mach42 is delivering a modern solution to accelerate analog and mixed-signal verification, leveraging advanced machine learning and AI to simplify, automate, and speed up complex verification tasks. Our proprietary neural network technology enables the creation of high-accuracy surrogate models from minimal data, dramatically reducing development and computational costs. These models can be automatically exported in Verilog-A, System Verilog, and C/C++ formats, enabling seamless integration with industry-standard simulators.

What was the most exciting high point of 2025 for your company?

One of the standout high points in 2025 was successfully unveiling a breakthrough AI-powered solution for analog circuit analysis. Our Discovery Platform was enhanced to dramatically improve validation of design performance across varying spec conditions, supporting near-realtime analysis to rapidly detect out-of-spec violations.

Another major highlight was being named a finalist in four prestigious awards this year. This includes the Design Tool and Development Software Product of the Year at the Elektra Awards, the Innovation Award at the OXBA Awards and both AI Innovation of the Year and Innovative Tech Company of the Year at the Thames Valley Tech and Innovation Awards.

What was the biggest challenge your company faced in 2025?

Our main challenge was striking the right balance between long-term product innovation and near-term customer deliverables. We’ve addressed this by embedding domain-specific analog intelligence into our neural network technology, enabling near–real-time verification while remaining fully compatible with existing EDA workflows.

As a result, Mach42 can automatically generate accurate surrogate models in Verilog-A format that run on standard SPICE-class simulators, significantly reducing verification time without compromising accuracy.

How is your company’s work addressing this challenge?

Mach42 addresses this challenge by combining physics-aware neural network models with deep analog design expertise to deliver immediate, production-ready value. Our platform integrates directly into existing EDA workflows, allowing engineers to achieve near–real-time verification speeds without changing how they design or verify circuits.

By automatically generating accurate surrogate models in Verilog-A, Mach42 dramatically reduces simulation time while preserving SPICE-level fidelity, enabling faster design iteration and earlier identification of corner-case issues.

Additionally, our advisory board and dedicated technical team help shape a credible long-term roadmap. Industry recognition and programs such as Cadence’s Connections Program further reinforce trust in our technology.

What do you think the biggest growth area for 2026 will be, and why?

Looking to 2026, AI-driven verification and simulation in semiconductor design is poised for significant growth. As chips become increasingly complex and time-to-market pressures intensify, engineers will demand solutions that accelerate verification while maintaining the highest levels of accuracy. Tools that combine speed, scalability, and predictive insights will become essential to meeting these challenges.

How is your company’s work addressing this growth?

Mach42’s Discovery Platform directly addresses this growth by leveraging machine-learning–driven emulation to rapidly predict design outcomes and accelerate design space exploration, identifying out-of-spec conditions early. It also streamlines IP reuse by validating performance across varied specifications and integrates seamlessly with existing simulators and flows, making adoption straightforward for design teams. These capabilities position Mach42 as a key enabler for next-generation semiconductor design.

Are you incorporating AI into your products? / Is AI affecting the way you develop your products?

Absolutely. AI is at the heart of our platform, powering proprietary algorithms that accelerate traditionally slow simulation and verification tasks while preserving accuracy, delivering orders-of-magnitude speedups. It’s not just a feature—AI shapes both the product and how we develop it. Our models learn from past simulation data, adapt to complex analog design challenges, and continuously improve through real-world feedback, enhancing both performance and reliability.

How do customers normally engage with your company?

Customers typically start with a focused engagement to identify their key areas of interest. After this initial phase, they move to an annual subscription, which provides full access to the Mach42 Discovery Platform, R&D support, and ongoing technical assistance.

Additional comments?

Mach42’s rapid progress in 2025—from major product milestones to industry recognition—highlights the rising demand for AI-first solutions in complex engineering. Positioned at the intersection of AI, simulation, and semiconductor design, we are uniquely equipped to shape the future of chip development.

Contact Mach42

Also Read:

Video EP12: How Mach42 is Changing Analog Verification with Antun Domic

Video EP10: An Overview of Mach42’s AI Platform with Brett Larder

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Siemens and NVIDIA Expand Partnership to Build the Industrial AI Operating System

Siemens and NVIDIA Expand Partnership to Build the Industrial AI Operating System
by Daniel Nenni on 01-12-2026 at 6:00 am
Categories: AI, EDA, Siemens EDA

CES 2026 Jensen Huang founder and CEO of NVIDIA Roland Busch President and CEO of Siemens AG

At CES in Las Vegas, Siemens and NVIDIA announced a major expansion of their long-standing collaboration, aiming to create what they term the “Industrial AI Operating System.” This ambitious initiative seeks to embed artificial intelligence deeply across the entire industrial value chain—from design and engineering to manufacturing, operations, and supply chains—transforming how physical systems are conceived, built, and managed in the real world.

The partnership builds on previous efforts, including integrations between Siemens’ Xcelerator platform and NVIDIA’s Omniverse for photorealistic digital twins. Now, the companies are fusing NVIDIA’s expertise in accelerated computing, generative AI, and simulation with Siemens’ industrial software, automation, and domain knowledge to develop AI-native workflows that turn passive digital twins into active, intelligent systems.

NVIDIA will contribute its AI infrastructure, simulation libraries, models, frameworks like Omniverse and CUDA-X, and blueprints for scalable deployment. Siemens, in turn, is committing hundreds of industrial AI experts along with its leading hardware and software portfolio. As Roland Busch, President and CEO of Siemens AG, stated, “Together, we are building the Industrial AI operating system—redefining how the physical world is designed, built, and run—to scale AI and create real-world impact.”

Jensen Huang, NVIDIA’s founder and CEO, emphasized the revolutionary potential: “Generative AI and accelerated computing have ignited a new industrial revolution, transforming digital twins from passive simulations into the active intelligence of the physical world.” The collaboration closes the loop between virtual simulation and physical execution, allowing industries to model complex systems virtually, optimize in real time, and automate seamlessly.

A key focus is creating fully AI-driven, adaptive manufacturing sites. The blueprint begins in 2026 with Siemens’ Electronics Factory in Erlangen, Germany, serving as the world’s first such facility. Powered by an “AI Brain”—combining software-defined automation, industrial operations software, and NVIDIA Omniverse libraries—these factories will continuously analyze digital twins, test improvements virtually, and apply validated changes directly to the shop floor. This promises reduced commissioning times, higher productivity, lower risks, and more sustainable operations.

The partnership extends to semiconductor design, where Siemens will GPU-accelerate its electronic design automation tools using NVIDIA’s PhysicsNeMo and CUDA-X, targeting 2x to 10x speedups in verification and layout processes. Additionally, the companies are developing blueprints for next-generation AI factories that optimize power, cooling, and automation for high-density computing.

To prove scalability, Siemens and NVIDIA will first implement these technologies in their own operations before rolling them out to customers. Early adopters evaluating the capabilities include Foxconn, HD Hyundai, KION Group, and PepsiCo.

This expanded alliance positions Siemens and NVIDIA at the forefront of the industrial AI revolution, accelerating innovation while addressing challenges like energy efficiency and resilience in global infrastructure. By making AI accessible and impactful at industrial scale, the Industrial AI Operating System could usher in a new era of smarter, more adaptive manufacturing, bridging the digital and physical worlds like never before.

Also Read:

Automotive Digital Twins Out of The Box and Real Time with PAVE360

Addressing Silent Data Corruption (SDC) with In-System Embedded Deterministic Testing

3D ESD verification: Tackling new challenges in advanced IC design

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CES 2026 and all things Cycling

CES 2026 and all things Cycling
by Daniel Payne on 01-11-2026 at 2:00 pm
Categories: Events
3 Comments

segway

I just completed the annual Rapha 500 Challenge on Strava by cycling 869 km in eight days, so it’s time to give you my annual recap of CES 2026 and all things cycling. Similar to previous years the big push again in 2026 are e-bikes and even e-motos. The AI acronym was everywhere too in product names and announcements as physical AI features abound in new products. Oh, EDA and IP vendors like Synopsys, Siemens, Cadence, MIPS, Ceva , RISC-V , T2M-IP and Dolphin Semiconductor were also present at CES this year.

E-bikes

Segway

There original two-wheel self-balancing devices is hardly mentioned anymore, in favor of two new e-bikes and one e-moto.

Xaber 300, Myon, Muxi

The Xaber 300 is an electric dirt bike with full suspension, the Myon is a Class 3 commuter e-bike capable of a 28 mph top speed, while the Muxi is a more compact Class 2 commuter  e-bike with a top speed of 20 mph.

Yadea

This Chinese company showed two new e-bikes, Fatboy for fat tire lovers, and Flo for urban commuters.

Fatboy, Flo

BGL Bike

They offer a range of six e-bikes: City, Fat, Folding, Mountain, Road, Trike.

BGL Bike: Electric Fat Bike

Kamingo

How about taking your existing bike and converting it into an e-bike? Kamingo has such a conversion kit that assembles in minutes, driving the rear wheel of your bike. They also won a 2026 CES Innovation Award for this product.

Kamingo

Bosch

This German company provides the e-bike drivetrain to 100 bike brands around the world, and they showed the Family Next e-bike, using all of Bosch’s eBike system.

Bosch eBike System

C-Star

This year they showcased several new e-bikes for off-road use.

Alucard: CS-M4A

Hyper Bicycles

This vendor has both traditional bike and e-bikes, even e-bikes for kids and several models for off-road use.

Hyper Bicycles: 16in e-balance for kids

Macfox

Three e-bikes were on display for urban cyclists that prefer fat tires for a comfy ride.

Macfox

Leoguar Bikes

Hailing from Texas, this vendor provides four e-bike styles: Fat tire, Cruiser, Mountain  and Folding.

Leoguar Bikes

Mimbob

Another Chinese supplier with a wide range of e-moto for off-road use.

Mimbob

Heybike

Multiple e-bike models were shown this week: Venus – cruiser, Helio F – foldable, Mars 3.0 – fat tire, Ranger 3.0 Pro – suspension, Polaris – touring, Omega – long distance, Villain – dirt bike.

Heybike: Polaris

Radar

I’ve started using the Garmin Varia radar on my road bike and it alerts me to approaching traffic from behind by beeping and then showing how close it is on my Garmin bike computer display. Several companies have entered the bike radar business.

Segway

For only $99 you get a bare-bones radar to fit on the back of your Segway bike.

Segway Rearview Radar

Seeru

A 2026 Honoree in mobile devices the Seeru stands for See Rear for U, and can be attached to a bicycle or a powered wheelchair to report approaching vehicles.

Seeru

Miscellaneous

Bosch added a new e-bike security features so that a stolen e-bike gets marked in the eBike Flow app, alerting dealers and authorities that it has been stolen.

Bosch e-bike security

EVs have used regenerative braking for several years now and a company called Hello Space showed off a Mag Drive system that charges your e-bike battery while the bike is moving, extending the battery range. I’d love to know how this works on an e-bike, because in my Tesla the regenerative braking slows, then stops my EV.

Hello Space: Mag Drive

Livall returned to CES with their PikaBoost e-bike converter and AI Visual Smart Taillight products.

PikaBoost
AI Smart Light

Hypershell

Tony Stark became Ironman after donning a robotic suite, so Hypershell has the X Ultra Exoskeleton to deliver more power for cyclists.

Hypershell

Blequp brought their AI-powered glasses called Ranger to CES, and they have video recording, intercom and AI sports assistance. I like the idea of keeping my eyes on the road while cycling combined with these features.

BleeqUp: Ranger

Speediance showcased their smart trainer, VeloNix with adjustable controls to fit your body shape and a screen with metrics to keep you informed of your workout progress.

Speediance: VeloNix

Daniel’s Gear

Outdoor riding:

  • 2022 Cervelo R5 road bike, Zipp 404 wheels, SRAM AXS Force components
  • Garmin 1040 bike computer
  • Garmin Dual heart rate monitor
  • Specialized S-Phyre cycling shoes
  • Garmin Varia radar
  • SpeedPlay pedals
  • Continental Grand Prix 5000S TR, tubeless tires

Indoor riding:

  • 2016 Cervelo R3 road bike, Zipp 404 wheels, SRAM Red components
  • Tacx Neo 2T smart trainer
  • Wahoo KICKR Desk
  • Zwift cycling app
  • mac Mini M4, wireless keyboard, wireless trackpad
  • Raycon earbuds for Discord app

Summary

The top road bike brands shun CES, like: Trek, Specialized, Giant, Canyon, Orbea, Cannondale, Cervelo, Scott, Pinarello, Bianchi, Colnago, Factor. Many of these bike brands do offer e-bikes, but CES is just not their focused show.

What I saw virtually at CES this year is a continued strong presence of e-bikes from non-traditional bike companies that are mostly recently founded, so it’s a crowded market for sure. E-bike sales were over 1 million in 2022, and 63% of all new bikes sold from 2019 to 2023 were e-bikes. 2024 sales in the US of e-bikes were 1.7 million units.

Troubling for me when I ride my road bike around in the Portland, Oregon area is the distinct trend of seeing many e-bike riders without any helmets, as protecting your head with a helmet is a must-have for safety. I wouldn’t be alive without a helmet after my 2018 bike crash. e-motos are involved in more crashes than e-bikes, but both categories should have increased safety measures like helmets and the use of hand signals.

Also Read:

Nvidia Overcoming the Challenges of Blending Hardware Verification Expertise with AI and ML

Acceleration of Complex RISC-V Processor Verification Using Test Generation Integrated with Hardware Emulation

Revolutionizing Hardware Design Debugging with Time Travel Technology

Podcast EP326: How PhotonDelta is Advancing the Use of Photonic Chip Technology with Jorn Smeets

Podcast EP326: How PhotonDelta is Advancing the Use of Photonic Chip Technology with Jorn Smeets
by Daniel Nenni on 01-09-2026 at 10:00 am

Daniel is joined by Jorn Smeets, Managing Director for North America at PhotonDelta, an industry accelerator for photonic chip technology. Based in Silicon Valley, his mission is to advance the photonic chip industry by fostering collaboration between European and North American entities.

Dan explores the focus of PhotonDelta with Jorn, who describes the organization’s broad charter to support an end-to-end value chain for photonic chips that designs, develops, and manufactures innovative solutions to contribute to a better world. Jorn explains some of the impressive work PhotonDelta has done in collaboration with the worldwide supply chain to enhance the use of photonic chip technology.

Jorn also discusses the upcoming PIC Summit USA event. This event started last year as a small gathering of key players to explore how to better collaborate to expand the impact of photonic chip technology. He explained that this year the event has been expanded to include more topics and more participation from a world-class group of speakers and organizations.

The event will be held in Sunnyvale, CA on January 19, right before the SPIE Photonics West Exhibition in San Francisco. Attendance at PIC Summit USA is by invitation only. You can learn more about the event and request an invitation here.

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Webinar: Why AI-Assisted Security Verification For Chip Design is So Important

Webinar: Why AI-Assisted Security Verification For Chip Design is So Important
by Mike Gianfagna on 01-09-2026 at 6:00 am
Categories: AI, Caspia Technologies, Events, Security

Why AI Assisted Security Verification For Chip Design is So Important

It is well-known that AI is everywhere, and the incredible power of this new technology is enabled by highly complex, purpose-built silicon. But there is a silent enemy of this substantial, world-changing progress. Something that has the power to steal a bright future from all of us. The hardware root of trust for those advanced custom chips is at the epicenter of the story. Simply put, AI advances have made the hardware root of trust vulnerable to attack. You can see the stories in news headlines. And it’s getting worse.

Thankfully, there are companies focused on this problem. Caspia Technologies is a bright spot among those companies. It is developing an AI platform of tools, a methodology and training to fortify chip design practices against this threat to secure future innovation. The company presented an important webinar on this topic recently. If you’re involved in advanced chip design, you need to see this webinar. A replay link is coming. Let’s first look at some details about why AI-assisted security verification for chip design is so important.

Who’s Presenting

The webinar contains three parts – an overview of the problem and Caspia’s solution, a live demonstration of how to find and fix security flaws in real chip designs and an interactive Q&A session with the webinar audience. There are two well-qualified members of the Caspia team presenting:

Beau Bakken first provides an overview of security risks all design teams face today. He then describes an effective strategy to minimize these risks and illustrates how it works. Beau is VP of Products at Caspia. He works on the definition of new products and the associated go to market strategies. Beau has been with Caspia for over five years. Before that, he spent time at the National Science Foundation.

Dr. Paul Calzada then presents a live demonstration of CODAx, Caspia’s security-aware static verification solution. You will see the analysis of a real design and the identification of security weaknesses. Paul is an R&D Application Engineer at Caspia. He works with customers to ensure effective deployment of Caspia’s solutions. Paul holds a PhD in Computer Engineering from the University of Florida.

What Is Covered

Beau begins the webinar with some eye-opening information regarding the growing vulnerability of the hardware root of trust and its associated firmware and microcode. He shares alarming trends regarding the growth of hardware-focused attacks and presents some real examples of the problem taken from news headlines. 

Beau then explains how AI is making it easier to attack the same hardware that is accelerating AI workloads. He points out that AI is the problem and the solution to this dilemma. He explains that hardware is NOT patchable, and chip security flaws will cost billions of dollars to recall and repair. Security flaws are simply not an option any longer.

Beau then explains the architecture of Caspia’s secure-by-design approach to addressing this important issue. He explains how Caspia’s tools easily integrate into existing design flows, how these tools find security flaws and assist in removing them early in the design process, before a disaster occurs in the field.

Since AI is causing the problem, the solution must also use AI to see what’s coming and remove the threats. Beau also describes Caspia’s generative and agentic technology that makes every designer a security expert.

Paul then demonstrates how to find and fix security flaws in a real open-source design. He uses Caspia’s CODAx static security verification tool to do this. You learn the depth of security checks that CODAx performs so subtle security weaknesses can be found and fixed early.

Watch the Webinar Replay Now!

If you are designing advanced chips that will be part of AI workload acceleration, this is a must-see event. Watch the replay now, you’ll be glad you did.  Here is a link to watch the replay. And that’s how you can find out why AI-assisted security verification for chip design is so important.

Also Read:

A Six-Minute Journey to Secure Chip Design with Caspia

Large Language Models: A New Frontier for SoC Security on DACtv

Caspia Focuses Security Requirements at DAC