SemiWiki – Page 39 – The Open Forum for Semiconductor Professionals

January 8, 2026January 15, 2026

CEO Interview with Scott Bibaud of Atomera

CEO Interview with Scott Bibaud of Atomera
by Daniel Nenni on 01-08-2026 at 4:00 pm
Categories: CEO Interviews

Scott Bibaud has served as President, Chief Executive Officer and a director since October 2015. Mr. Bibaud has been active in the semiconductor industry for over 25 years. He has successfully built a number of businesses in his career which grew to generate over $1 Billion in revenue at some of the world’s largest semiconductor companies. Most recently he was Senior Vice President and General Manager of Altera’s Communications and Broadcast Division. Prior to that he was Executive Vice President and General Manager of the Mobile Platforms Group at Broadcom.

Tell us about your company.

Atomera Incorporated is a semiconductor materials and technology licensing company focused on deploying its proprietary, silicon-proven technology into the semiconductor industry. Our mission is to extend the life and performance of today’s semiconductor technologies through innovation at the materials level. Our Mears Silicon Technology™ (MST ®), a proprietary material/film technology, enhances transistor performance, power efficiency, and scalability, helping chipmakers achieve next-gen results utilizing their existing manufacturing infrastructure.

As AI accelerates demand for more powerful and efficient systems, advancements in materials are becoming the catalyst that makes those gains possible, enabling continued breakthroughs in power, performance, area, and cost (PPAC). Atomera is currently working with several of the world’s top semiconductor producers and playing a hands-on role in areas like advanced logic (GAA), DRAM, power, and wireless/radio frequency (RF), underscoring the industry’s growing recognition of MST’s potential benefits.

What problems are you solving?

Atomera is trying to solve key bottlenecks in the industry, including performance and power to yield and cost through MST.

For decades, Moore’s Law, which accurately predicted that the number of transistors on a chip would double around every two years, kept the industry moving forward. The steady pace of innovation is now being tested. As chips shrink to 3nm and beyond, FinFets can no longer deliver the needed performance and efficiency, so manufacturers are switching to gate-all-around (GAA) technology. However, GAA isn’t perfect. While GAA addresses electrostatic challenges, it also introduces new ones. This is where Atomera’s advanced materials come into play.

This reality is driving a growing consensus across the industry that scaling alone is not enough. In fact, a recent survey saw that 94% of respondents believe simply shrinking nodes will no longer be sufficient. Instead, 99% of those polled are pointing to innovation in new materials and technologies as essential to unlocking PPAC improvements to support AI workloads.

It turns out that materials, such as MST, can continue to improve transistor channel behavior by improving electron mobility, lowering leakage, or improving variability, enabling better performance or lower power, even as the industry carries on to the next node. These breakthroughs in advanced materials are empowering the industry to achieve higher performance with reduced space and energy requirements.

What application areas are your strongest?

One of MST’s most strategic advantages is its ability to be integrated with minimal equipment changes, allowing manufacturers to extract new levels of performance and efficiency from existing manufacturing processes, achieving more without the need for costly new tools.

In power electronics, MST helps push past today’s material and architectural limits by enabling devices to handle higher voltages and currents more efficiently through reduced on-resistance and improved breakdown voltage. This means MST can offer customers a path to better PPAC without major design changes or expensive process overhauls.

RF products are facing increasing signal performance issues with the transition to 5G. Low-noise amplifiers (LNAs) and advanced RF switching technologies are the unsung heroes ensuring signal strength, clarity, and battery life. Innovations like MST can improve signal performance and extend RF-SOI’s platforms, delivering higher gain, lower noise, and faster switching. For a mobile phone user, this translates to clearer signals, higher bandwidth, and longer battery life.

MST also has applications for memory integration. By reducing variability and leakage in memory transistors, MST enhances stability and density in DRAM and SRAM devices. And in the GAA arena, Atomera’s technology can be used to optimize performance in at least four different areas of the transistor.

Meanwhile, in GaN-on-silicon structures, MST enables improved yield for high-performance RF and power devices.

What keeps your customers up at night?

The gap between the needs of AI workloads and the capabilities of today’s silicon-based infrastructure is one of the largest industry challenges right now. In the same survey, more than 200 semiconductor engineers, materials scientists, and technical industry leaders in the United States found that 76% of decision-makers believe data centers will fall short of meeting soaring AI and high-performance computing demands. To keep shrinking and improving chips for massive AI systems, engineers are turning to advanced materials as the lever for PPAC gains and to keep progress on track.

To meet the performance and efficiency demands of the AI market, designers are turning to the most advanced semiconductor processes using GAA transistors. Today, the first wafers with this architecture are entering production, but the power, performance, and yield still have significant room for improvement. Our customers are looking for any compelling solution to help achieve those goals, and Atomera’s technology is one key piece of the puzzle.

What does the competitive landscape look like and how do you differentiate?

It is widely understood in the industry that it takes a new material roughly 18 years from first concept to volume production in the semiconductor supply chain. Atomera’s material technology has successfully navigated this journey. This level of investment and persistence in an independent company is rare, and while there are other providers of advanced materials, we feel that most are complementary, or additive, to our technology, rather than competitors. Many of our largest customers have R&D teams internally who are trying to solve the same problems that we are addressing, and Atomera’s technology provides a very well-developed tool they can leverage, making MST uniquely positioned in the market. It takes a full ecosystem of solution providers to bring the most advanced nodes to market, and Atomera is happy to play our part.

What new features/technology are you working on?

Atomera is continually working to understand the challenges faced by companies across industries we serve and refining our film and integration techniques to deliver compelling solutions to customers. For example, companies making RF front ends for cellular applications are confronted with increasing demands as phones use more bandwidth and communicate over more and more frequency bands. RF components are significant consumers of battery power in mobile phones, but these new frequency bands require radios to scan an even wider area than before, placing pressure to lower the power of their LNAs. Recently, we determined that MST can be very effective in helping them meet this goal while simultaneously improving their RF switch efficiency. We are working on solutions like these in several different markets for a variety of customers.

Another area of growing focus is compound semiconductors. Our work in GaN shows how MST can be leveraged to bring physical improvements to a material that translate well into electrical advantages. We have exploratory projects underway in other compound semiconductors, which we expect will start maturing in the near term as well.

How do customers normally engage with your company?

Today, Atomera and MST are widely recognized across the semiconductor industry, and we collaborate with a broad range of leading companies. Oftentimes, after Atomera validates how MST can be used to help a customer with a known problem or to achieve device improvements, we will meet with the team to show the supporting data. Next, our teams will conduct Technology Computer-Aided Design (TCAD) simulations to understand how MST can be used in their fabs and then wafer demos are run where MST is deposited on their wafers and other tests are conducted. If all goes well, we will license our technology to them, install it on one of their production tools, and go into a period of tuning our film and their integration method to maximize performance. Atomera’s TCAD modeling, epi deposition, and integration engineering teams provide support the whole way, helping our customers transition to mass production. At that stage, our business model is to take a small royalty on every wafer they manufacture while partnering with them to optimize the next process they’re working on.

Contact Atomera

Also Read:

CEO Interview with Masha Petrova of Nullspace

CEO Interview with Eelko Brinkhoff of PhotonDelta

CEO Interview with Pere Llimós Muntal of Skycore Semiconductors

January 8, 2026April 13, 2026

2026 Outlook with Volker Politz of Semidynamics

2026 Outlook with Volker Politz of Semidynamics
by Daniel Nenni on 01-08-2026 at 10:00 am
Categories: IP, RISC-V, Semidynamics

Tell us a little bit about yourself and your company.
I am the Chief Sales Officer for Semidynamics and I lead the global sales team and drive the overall sales process.

Semidynamics was founded in 2016 as a design service company with a focus on RISC-V. This was so successful that the CEO decided to pivot the company towards its own IP sales and started licensing IP from 2019.

We provide 64-bit RISC-V processor IP which is complimented with our leading-edge vector unit and tensor unit extensions. We have combined these technologies together to form our All-In-One AI IP that provides a much better way forward for AI projects as it is future-proof, easy to program and easy for us to create the exact hardware needed for a project. In addition, it incorporates our Gazzillion Misses technology for advanced data handling to ensure that the processor is never idle waiting for data. When it comes to handling large amounts of data, we have the fastest, best-in-class solution for big data applications.

In 2025, that positioning sharpened even further: AI is the center of gravity for us, and Cervell (our all-in-one RISC-V NPU) is the clearest expression of that focus.

What was the most exciting high point of 2025 for your company?

The highlight of 2025 was turning our all-in-one story into a complete, developer-ready stack: launching Cervell in May, and then following up with the Inferencing Tools in October to accelerate deployment from trained model to running product.

In parallel, we kept removing friction from AI software enablement—especially through ONNX Runtime integration—because adoption depends on how fast teams can get to first results.

What was the biggest challenge your company faced in 2025?

The overall economic weakness hits big companies and small companies as well delaying spending, cutting budgets and re-thinking projects as they try to adapt to the fast-moving AI landscape and the overall global trade picture.

The AI market is extremely noisy, and serious customers are more disciplined than ever about evaluation, differentiation, and long-term software support before they commit. That raises the bar for any IP vendor, even when interest is strong.

How is your company’s work addressing this challenge?

We liaise closely with our customers to tailor our offering to their precise needs. In addition, we encourage them to engage early with us to avoid gaps in the product plans later on.

We also meet the prove it fast expectation by making AI deployment straightforward (ONNX enablement, and higher-level inferencing tooling), so customers can validate value quickly and de-risk the decision.

What do you think the biggest growth area for 2026 will be, and why?

‘Anything AI’ is still driving a lot of new products – especially generative AI, large language models – because it makes possible a whole new set of features to drive innovation.

We expect increasing demand around AI in segments such as data center appliances, vision processing such as security cameras, mobile base stations and software defined vehicles and we are ideally positioned with our All-In-One AI IP to be the solution of choice.

I think 2026 is going to be a big year for RISC-V itself: you can see major industry players deepening their commitment, and consolidation through M&A is reshaping the landscape, making the remaining independent specialists more visible and important.

From a European perspective, that matters: Semidynamics is one of the few remaining independent RISC-V IP vendors in Europe with a clear AI-first product strategy.

How is your company’s work addressing this growth?

Our All-in-one AI processing element is based on highly configurable IP blocks, that enable us to customize configurations on demand when required. Through dedicated engagement with partners we can also expand the IP with unique instructions and to combine with customer’s own circuits.

We also have a software support strategy for AI that is based on ONNX, which makes the need for dedicated compilers obsolete and enables the customer to run a model they download in ONNX format to run out of the box. This helps them to move quickly to a final product as software and hardware can be developed in parallel.

And we’re extending that practicality with the Inferencing Tools layer on top of our ONNX Runtime Execution Provider for Cervell, so moving from model to deployment takes less specialist effort.

What conferences did you attend in 2025 and how was the traffic?

We attended various RISC-V.org events as well as dedicated events such as ICCAD in China, Computex in Taiwan, Embedded World in Germany and the AI Infra summit in USA.

The RISC-V Summits were especially important in 2025. For example, the RISC-V Summit Europe in Paris was a strong focal point for the EU ecosystem.

Will you participate in conferences in 2026? Same or more as 2025?

We aim to attend some new conferences to spread the word that our RISC-V IP can provide the processor needs for new projects as well as attending some of the events that we have previously attended. There is a huge wave of RISC-V being increasingly used as a viable, exciting alternative to the two processor incumbents and we are surfing that wave.

I expect the same or slightly more in 2026 than 2025, because the interest level is rising and we now have a broader product + tools story to take to customers.

How do customers normally engage with your company?

Customers can engage with our sales force or via contacts on our website and other sites where we post adverts. Once established, we have dedicated resources to facilitate the evaluation process and subsequent product selection and purchase.

Are you incorporating AI into your products?

Yes—AI is the core of our product direction. Cervell is designed as a scalable, all-in-one RISC-V NPU for AI workloads, and the software layer (ONNX enablement and inferencing tools) is explicitly about making AI deployment easier.

Is AI affecting the way you develop your products?

Absolutely. AI is changing the requirements faster than ever—especially around model portability, deployment speed, and workload diversity—so we design for programmability and customization first, and we invest heavily in a software path that keeps pace (ONNX Runtime integration, and tooling that shortens the route from trained model to running application).

Additional comments?

One final observation: between the accelerating RISC-V ecosystem support (including big-name commitments) and the consolidation happening through acquisitions, customers are looking hard at who can still offer true differentiation. Our answer is simple: flexible and scalable IP plus a pragmatic AI software path that helps teams get to working silicon faster and with less risk.

Contact SemiDynamics

Also Read:

Semidynamics Inferencing Tools: Revolutionizing AI Deployment on Cervell NPU

From All-in-One IP to Cervell™: How Semidynamics Reimagined AI Compute with RISC-V

Vision-Language Models (VLM) – the next big thing in AI?

January 8, 2026January 8, 2026

Nvidia Overcoming the Challenges of Blending Hardware Verification Expertise with AI and ML

Nvidia Overcoming the Challenges of Blending Hardware Verification Expertise with AI and ML
by Daniel Nenni on 01-08-2026 at 6:00 am
Categories: AI, Events

Verification Futures Conference 2025 Austin (USA). Keynote Challenge Paper – Sohil Sri Mani Yeshwanth Grandhi – NVIDIA Corporation

Hardware verification has always been one of the most demanding phases of system design, but today it faces an unprecedented crisis. As hardware systems grow exponentially in complexity verification resources, time, compute, and human expertise, scale far more slowly. This widening gap has resulted in endless regression cycles, overwhelming debug workloads, and a persistent mismatch between coverage metrics and real-world correctness. In this environment, AI and ML offer powerful new tools, but only if applied with realism, discipline, and a clear strategy.

The core challenge in modern verification is not merely the size of designs, but the volume of data they generate. Simulation logs can reach hundreds of megabytes, regression suites can contain tens of thousands of tests, and subtle bugs may hide behind layers of seemingly unrelated failures. Traditional approaches—manual triage, static thresholds, and brute-force regressions—are increasingly inefficient. Verification engineers often find themselves “drowning in complexity,” spending more time managing data than extracting insight from it.

AI promises a way forward by enabling prediction, optimization, and insight at a scale humans cannot achieve alone. Machine learning models can detect patterns across historical data while LLMs can interpret and summarize unstructured text such as logs, specifications, and bug reports. However, the adoption of AI in verification is frequently hindered by common pitfalls. “Magic Wand” thinking leads teams to expect instant results without sufficient data preparation. Others apply the wrong tool to the problem, such as using an LLM where a simple statistical model would be more reliable. Finally, poor-quality or inconsistent data can undermine even the most sophisticated AI system.

To avoid these traps, a practical framework is needed to decide when to use ML versus LLMs. Traditional machine learning excels at structured, numerical data test results, performance metrics, coverage statistics, and historical trends. It is well suited for tasks like predictive test selection, performance regression detection, and bug triage classification. LLMs, by contrast, shine when dealing with unstructured text. They can parse massive log files, summarize failure causes, correlate error messages across modules, and even generate documentation or coverage models from natural-language specifications. Understanding these complementary strengths is key to building an effective hybrid strategy.

Real-world case studies illustrate this distinction clearly. In compiler verification, for example, a code change may pass all functional tests yet introduce a subtle 2% performance regression on a critical benchmark. Legacy approaches based on static thresholds often fail to catch such issues reliably. A modern ML-based solution uses time-series anomaly detection, learning normal performance behavior over time and flagging deviations with much higher sensitivity and confidence. This approach reduces false positives while catching regressions early, before they reach customers.

Similarly, intelligent log analysis with LLMs addresses one of verification’s most painful bottlenecks: debugging. When a complex simulation fails and produces a 100MB log file with interleaved messages from dozens of modules, manual inspection becomes impractical. LLMs can ingest these logs, identify the most relevant error sequences, summarize likely root causes, and even suggest next debugging steps. Rather than replacing the engineer, the model acts as a force multiplier, accelerating understanding and decision-making.

Building a successful AI-driven verification strategy requires thoughtful execution. Teams should start small by targeting a specific, high-impact problem rather than attempting a full-scale transformation. AI should augment human expertise, not replace it, keeping engineers firmly in the loop for validation and judgment. A solid data foundation—clean, labeled, and consistent—is essential, as AI systems are only as good as the data they learn from.

Bottom line: The verification crisis is fundamentally a data problem, and AI provides a powerful new toolbox to address it. By being strategic, choosing the right tools, and focusing on augmentation rather than automation, verification teams can regain control over complexity. The path forward does not require perfection—only a willingness to start now and evolve incrementally.

Verification Futures Conference

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January 7, 2026January 7, 2026

2026 Outlook with Howard Pakosh of Tekstart

2026 Outlook with Howard Pakosh of Tekstart
by Daniel Nenni on 01-07-2026 at 10:00 am
Categories: AI, TekStart

Tell us a little bit about yourself and your company.
I founded TekStart Group in Ontario, Canada, in 1998 with a very clear objective: to help innovators turn breakthrough technology concepts into real, market-ready products. Over the past 25-plus years, we have worked across the full lifecycle of technology development, from early concept and architecture through funding, commercialization, and exit.

To date, TekStart has helped develop, fund, and successfully exit more than 120 companies. That experience has given us a deep appreciation for what it really takes to bring complex technologies to market, especially in semiconductors and systems where timelines are long and execution risk is high.

Today, I am most excited about the transformation underway as AI inferencing moves out of centralized data centers and into edge devices. We are seeing a fundamental shift in how intelligence is deployed, and that shift creates both technical and economic opportunities that simply did not exist a few years ago.

What was the most exciting high point of 2025 for your company?

Without question, the most exciting milestone for us in 2025 has been reaching the final stages of tapeout for our latest semiconductor product, Cognitum. This has been a five-year journey, and like most deep-tech efforts, it has involved plenty of unexpected turns along the way.

Bringing a new AI-focused chip to market is never straightforward. There were moments where progress felt incremental and others where challenges stacked up quickly. Still, seeing Cognitum reach this level of maturity has been extremely rewarding. If I ever do write a book, this program would certainly deserve a few chapters.

As we approach launch, the excitement comes not just from completing the silicon but from seeing how customers are already thinking about deploying it to solve real problems at the edge.

What was the biggest challenge your company faced in 2025?

The honest answer is that the biggest challenge in 2025 was everything at once. If there was a category of delay or disruption you could imagine, we likely encountered it.

Market uncertainty created constant pressure on planning and forecasting. We worked closely with customers whose own roadmaps were being affected by factors well beyond their control. On top of that, new tariffs introduced additional complexity around cost structures, supply chains, and contract negotiations.

Each issue on its own would have been manageable. Experiencing them simultaneously required continuous adjustment, clear communication, and a willingness to revisit assumptions more often than usual.

How is your company’s work addressing this challenge?

What I am most proud of is the resilience our team demonstrated throughout the year. There were moments when obstacles felt genuinely insurmountable, yet the team stayed focused on execution and problem-solving rather than distraction.

We concentrated on what we could control: engineering discipline, customer transparency, and forward momentum. That mindset allowed us to navigate uncertainty while continuing to move Cognitum toward final tapeout.
In semiconductors, persistence matters. Staying aligned as a team and maintaining confidence in the long-term vision is often the difference between programs that stall and programs that succeed.

What do you think the biggest growth area for 2026 will be, and why?

I firmly believe that Edge AI will be one of the most important growth areas in 2026. For several years, the industry’s focus has been heavily weighted toward cloud-based large language models and massive data center build-outs. While those investments are necessary, they do not fully address the needs of real-world autonomous systems.

There is a growing gap between what cloud LLMs are optimized for and what edge systems actually require. Latency, bandwidth, cost, power consumption, and data privacy all become critical constraints outside the data center.
In 2026, we will see greater emphasis on pushing intelligence closer to where data is generated, enabling faster, more predictable, and more economical decision-making at the edge.

How is your company’s work addressing this growth?

The demand for edge reasoning is expanding rapidly across robotics, industrial automation, infrastructure, IoT, and enterprise systems, where privacy and determinism are critical. These applications increasingly require local decision-making, yet cannot tolerate the latency, recurring costs, or lack of transparency associated with cloud-based inference.

Cognitum is designed specifically to address this gap. It enables a new class of low-cost devices capable of autonomous reasoning directly on the chip. By moving inference to the edge, customers can significantly reduce or eliminate recurring cloud inference costs.

This changes the economic model from per-token or usage-based billing to a fixed hardware cost, making large-scale deployments practical in scenarios that were previously uneconomical or operationally constrained.

What conferences did you attend in 2025, and how was the traffic?

We sponsored and attended the AI Infra Summit in September 2025, and the difference compared to the prior year was striking. Attendance was significantly higher, and the level of engagement was much stronger.
We saw more informed conversations, more qualified prospects, and a clearer understanding of why edge AI infrastructure matters. Being featured in a success story at the event was also valuable, as it allowed us to share our journey and lessons learned with a broader audience.

Will you participate in conferences in 2026? Same or more than 2025

Conferences will continue to play an important role in our marketing and business development strategy. While digital engagement is effective, there is still no substitute for in-person conversations when discussing complex technologies.

We will kick off 2026 at CES and expect to maintain, if not increase, our level of conference participation throughout the year. The quality of interaction we see at these events continues to justify the investment.

How do customers normally engage with your company?

Our business is highly specialized, and we intentionally focus on a narrow, well-defined customer segment. We have served this market for many years and have built a reputation as a trusted partner rather than a transactional vendor.
That trust works to our advantage as we introduce new products. Being a known entity means customers are already familiar with our approach and capabilities. As a result, maintaining awareness, sharing meaningful updates, and staying engaged with key stakeholders remains one of the most effective ways we work with our customers.

Additional comments?

The world has become a more complex and challenging place, both personally and professionally. Technology continues to advance at an accelerating pace, and it can be difficult to keep up with everything that is changing.

That makes it even more important for technology providers to be thoughtful and deliberate about what they build and how those technologies are brought to market. The decisions made over the next few years are likely to have an impact that extends far beyond the near term.

If we approach this moment with care and responsibility, the opportunities ahead are significant. How we move forward matters.

Also Read:

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Acceleration of Complex RISC-V Processor Verification Using Test Generation Integrated with Hardware Emulation

Quantum Computers: Are We There Yet?

January 7, 2026February 14, 2026

Automotive Digital Twins Out of The Box and Real Time with PAVE360

Automotive Digital Twins Out of The Box and Real Time with PAVE360
by Bernard Murphy on 01-07-2026 at 6:00 am
Categories: AI, Automotive, EDA, Siemens EDA

Digital twins are amazing technology, virtual representations mirroring a real physical system. Twin virtual models span software, electrical/electronic and mechanical subsystems, closing the loop with feedback from real physical counterparts. The virtual model calibrates against real sensing feedback gathered in production and prototype testing spanning braking, cornering, road surfaces, weather and traffic conditions, and other factors, all with high fidelity. Digital twins greatly accelerate development, debug, and quality control for the advanced car systems we expect today, now even more essential as these systems become more complex and more safety critical.

David Fritz (VP of Hybrid Virtual and Physical AI Systems at Siemens Digital Industries) told me that, for all their benefits, building a twin by integrating multiple parts from multiple suppliers used to take large teams years. An immense effort, out of reach for most enterprises except for the largest OEMs and Tier1s, and too slow even for them to adapt in fast-moving markets. To deliver on the real time expectation of this promise, Siemens have developed and announced at CES 2026 their “PAVE360 Digital Twin Blueprint”, a fully integrated platform providing a jumpstart not only for large OEMs and Tier1s but also for other innovators in the automotive ecosystem.

Real-time simulation for realistic workloads

Earlier generations of digital twins apparently would run a couple of orders of magnitude slower than real time. Software developers no longer consider that level of performance sufficient for their needs, given that today they must run millions of lines of code together with realistic AI workloads.

Siemens, working with Arm and AWS, announced a new approach last year based on Arm Zena CSS/cloud-native support. This can deliver near real-time performance for those target workloads, within the full scope of the digital twin. That’s a very big deal because developing and exercising ADAS, autonomous driving (AD) and infotainment (IVI) features in the twin requires that level of performance.

Equally important, SDV Digital Twin Blueprint provides a ready-to-deploy reference platform including virtual reference hardware and software stacks (AI functionality also) for ADAS, AD, and IVI. Running on day one, accessible for cloud-based collaboration. As needed you can swap in your own software stacks, replacing corresponding reference stacks. The platform builds on IPs such as Arm Zena CSS and provides mechanisms to connect to real vehicle hardware.

I asked (and I’m sure you wondered also) how AI models run inside this platform, whether cloud-based or on-prem. David said that if GPUs are available, the system will take advantage of them. If not, it will leverage Zena cores, appearing everywhere these days in cloud servers. David can’t share more details on this topic but I’m looking forward to learning more about Arm’s directions in server AI since they have already announced hardware acceleration options for AI in mobile.

Extending opportunity to the larger ecosystem

David said that they are seeing interesting adoption from organizations outside the traditional supply chain, such as engineering service suppliers. These are often OEM-sponsored ventures with trusted, specialized expertise in advanced capabilities that OEMs are targeting for 2030. Such ventures modify PAVE360 Automotive Blueprint with their own stack, to demonstrate to an OEM the value their solution can offer. Better yet, this can drop straight into the OEM’s own development platform if they also use PAVE360.

As one example, Silicon Auto is part of a joint venture with Stellantis and Foxconn, focused particularly on ADAS systems. They used PAVE360 Automotive Blueprint to model the silicon they wanted to build, putting it in the content of a whole vehicle. Silicon Auto systems are now planned to support Stellantis, Foxconn and other customers.

Another example is SAIC (Shanghai Automotive Industrial Corporation) which David calls “the Volkswagen of China”. SAICEC (EC is Engineering Corporation) is another joint venture providing design, system and applications services to SAIC and to the larger automotive industry in China. According to David, they are using Pave 360 in some interesting ways. Some no doubt like the earlier example, others exploring PAVE360 becoming a certification service to OEMs, inside of cloud.

Partnerships in addition these include AWS, AMD and Microsoft, Wipro and Cognizant. I would not be surprised to hear of OEM, Tier1, Cloud Services Provider and other partnerships in the near future.

CES 2026 demo and availability

This story hinges heavily on real time twin performance in the cloud. As proof that this capability is real, Siemens are demoing this capability at CES 2026, featuring a Volkswagen ID.Buzz in their booth connected to the Internet through Wi-Fi, with the brains of the car running in the cloud and controlling the car. You can (though the car) tell it where you want to go and watch it (virtually) navigate there. You can tell it to turn on the AC while the car is virtually enroute. From command, to cloud, back to the car in real time. Pretty impressive.

SDV Digital Twin Blueprint will be available February 2026. You can learn more about Siemens digital twin technology HERE.

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January 6, 2026April 14, 2026

Acceleration of Complex RISC-V Processor Verification Using Test Generation Integrated with Hardware Emulation

Acceleration of Complex RISC-V Processor Verification Using Test Generation Integrated with Hardware Emulation
by Daniel Nenni on 01-06-2026 at 8:00 am
Categories: EDA, Events, Synopsys

Verification Futures Conference 2025 Austin (USA)

The rapid evolution of RISC-V processors has introduced unprecedented verification challenges. Modern high-end RISC-V cores now incorporate complex features such as vector and hypervisor extensions, virtual memory systems, multi-level caches, advanced interrupt architectures, and multi-hart out-of-order execution. While these capabilities enable powerful and flexible processor designs, they also dramatically increase verification complexity. To ensure correctness and quality, verification methodologies must evolve to handle massive state spaces, long-running workloads, and extreme performance demands.

One of the most striking realities of contemporary RISC-V verification is the sheer scale of execution required. Verifying a typical high-end RISC-V core can demand on the order of 10¹⁵ cycles—far beyond the reach of traditional simulation alone. Effective verification therefore requires three essential components: stimulus derived from deep understanding of the RISC-V specification, complex and lengthy test programs that drive the design into meaningful microarchitectural states, and a fast execution platform capable of achieving verification closure within practical timelines.

The XiangShan RISC-V core exemplifies these challenges. Supporting RV64 with extensive extensions such as RVV 1.0, advanced memory management, large cache hierarchies with ECC, multi-level TLBs, and AIA-compliant interrupt handling, the design represents a realistic, high-complexity target. Verifying such a design requires stress-testing interactions across caches, memory ordering, interrupts, and multi-hart execution—scenarios that cannot be adequately covered by short, isolated tests.

To address these needs, Synopsys introduces STING, a bare-metal test generator purpose-built for RISC-V processor verification. STING employs a software-driven methodology that integrates multiple test generation approaches, including random stimulus, directed tests, workloads, and real-world scenarios. It generates both self-checking and pure stimulus tests that are portable across simulation, emulation, FPGA prototypes, and silicon. With comprehensive support for 32-bit and 64-bit RISC-V specifications, privilege modes, memory protection, virtualization, and multi-hart configurations, STING provides a scalable and reusable verification foundation. Its extensive library of over 100,000 test fragments enables rapid construction of complex test programs tailored to specific microarchitectural goals.

However, generating effective stimulus is only half the solution. Advanced RISC-V features such as cache coherency, memory ordering, atomicity, and synchronization demand long-running workloads to expose subtle corner cases. Scenarios involving true and false sharing, cache evictions, conflicting traffic, and fence ordering require sustained execution under varied conditions. For multi-processor platforms, repeating the same test sequence across different scheduling interleavings is essential to achieve thorough coverage. These demands make fast execution platforms indispensable.

Hardware-assisted verification (HAV) provides the necessary performance boost. By synthesizing the design under test and running it on emulation or prototyping platforms such as Synopsys ZeBu or HAPS, verification teams can execute tests at speeds orders of magnitude faster than simulation. In this approach, STING generates self-checking tests that embed reference model results directly into the executable. Tests are generated in parallel and streamed continuously into the hardware platform, ensuring that execution units remain fully utilized.

The streaming methodology is a key innovation in this solution. By avoiding repeated hardware re-initialization and redundant configuration cycles, and by enabling concurrent test generation and execution, streaming dramatically improves throughput. Results demonstrate performance improvements of up to 6000× per test when moving from simulation to emulation, making large-scale regression feasible for complex RISC-V designs.

Debugging failures discovered in high-speed regressions presents its own challenges. Because failures may depend on accumulated microarchitectural state across multiple tests, simple re-execution may not reproduce the issue. The recommended strategy involves replaying sequences of streaming-enabled tests to reconstruct the failing conditions. Hardware/software debug using tools such as Verdi enables synchronized analysis of CPU traces and waveforms, allowing engineers to step through execution while correlating software behavior with hardware signals.

Verification Futures Conference 2025 Austin (USA)

Bottom line: Accelerating complex RISC-V processor verification requires a tightly integrated strategy combining intelligent test generation, hardware-assisted execution, and advanced debug methodologies. By uniting STING with high-performance emulation platforms, verification teams can achieve comprehensive stimulus coverage, unprecedented execution speed, and effective debug—making verification closure achievable even for today’s most sophisticated RISC-V processors.

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CISCO ASIC Success with Synopsys SLM IPs

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January 6, 2026January 16, 2026

Quantum Computers: Are We There Yet?

Quantum Computers: Are We There Yet?
by Bernard Murphy on 01-06-2026 at 6:00 am
Categories: Quantum Computing

R&D for any fundamentally new technology takes time, especially for hardware; over 10 years passed from the first transistor to the first (very small) integrated circuit. The engineering behind quantum computers is arguably even more challenging than for electronic circuits, at least from today’s perspective. We shouldn’t be surprised that even now there are more challenges to overcome. As usual, for a quick read I will look at just a couple, a gate essential to demonstrating quantum advantage over classical computing, and quantum error correction (QEC) / fault-tolerant architectures.

T-gates

Introductions to quantum programming start with a simple set of gates called the Clifford group: H, S, and C-NOT gates. This group is important in many aspects of quantum programming and has the added advantage that algorithms based on the group can be simulated classically as efficiently as in quantum implementations. However the group is not complete for supporting general calculations, especially for algorithms that would be exponentially complex to compute on a classical system.

T-gates are a popular option to extend the set. Skimming over the details, gates in the Clifford group can modify a qubit through a very limited set of possibilities. A T-gate extends the range and can be thought of as the square root of an S gate (equivalent to S if applied twice). When combined in a sequence with Clifford gates this enables any arbitrary operation on a qubit to some desired accuracy. (Might seem surprising but the math goes all the way back to Euler.)

That’s the theory. How can a T-gate be implemented on a real quantum computer (QC)? Looking back at a couple of my earlier blogs on QC implementation (this and this), you’ll remember that gates are implemented by pulsing qubits with microwave, laser or other EM options. Naturally these mechanisms have imperfections, including finite frequency spread in pulses and imperfect focusing optics for lasers.

Add ambient noise on top of these imperfections and you can see that any intended gate operation will be performed with less than perfect fidelity. Clifford group states are in some sense maximally separated so perhaps a little less prone to errors, but a T-gate operation, as a square root of a Clifford gate, will typically be more sensitive.

The QC experts have an answer to this need. In one example, they pre-build one or more sets of purified T-gates, distilled from multiple noisy T-gates. In this approach, when considering your target algorithm, the number of T-gates you will need must be pre-determined along with the level of accuracy you must meet.

I expect the mechanism to purify T-gates will be captured in a library though given constraints on available qubit and coherence times for production systems today, any bloat will further limit allowable size and duration of your algorithm. Adding this new gate also adds complexity to verifying an algorithm on a classical computer, since complexity on a classical system grows exponentially with the number of T-gates. Recent research has shown it is possible to simulate relatively shallow circuits with T-gates so there is still hope for debugging noisy quantum circuits.

QEC and fault-tolerant computing

I touched on QEC in my blog on physical implementation of quantum computers. I’ll expand a bit more here. The basic concept in QEC is the same as in classical error correction – “copy” onto redundant qubits, run an operation, detect single qubit errors through majority voting and correct any errors (also work hard to make the probability of 2 or more errors very small). An operation starts with a qubit, adds redundancy, performs the operation, detects and corrects errors, from that reconstructing a corrected post-operation qubit.

There are complications.

Simply copying real qubits breaks coherence, instead they are entangled with the redundant qubits. After an operation, the method detects incorrect entangled states and uses that result to correct errors. However, qubit error possibilities aren’t just bit-flips; they can also be phase flips (e.g. |0>+|1> flips to |0>-|1>), requiring more circuitry to detect and correct. QEC around gates outside the Clifford group (like a T-gate) is more complicated to protect. Of course, error detection and correction circuitry will contribute further errors.

If this sounds difficult, you are not wrong. This is a race between error creation and error detection and correction. Some views held that ~1000 physical qubits would be required per logical qubit, clearly not scalable. Very active research is going into this area, in higher reliability qubits and in fault-tolerant computing, computing with accuracy using faulty systems.

I can’t find data on superconducting versus ion trap qubit reliabilities. Before considering external noise, I feel that ion trap reliabilities should be intrinsically high simply thanks to the physics of a single ion, whereas manufactured superconducting qubit will have inevitable tolerance errors.

IBM recently published breakthrough results, to reduce noise in memory (a set of qubits) though this does not touch on gate operations. Here is a nicely readable version, including some background on evolution of error correcting codes from Hamming to surface codes and now their latest “gross code”. For gate operations IBM points to next steps in the readable link immediately above. I couldn’t find reported results. In my (possibly faulty 😀) reading this suggests greatly reduced overhead for error correction, partly through choice of error-correcting codes and partly through pre-distillation of more error-prone operations such as T-gates (see above).

More background

There is a great video tutorial series from Artur Ekert (professor of quantum physics at Oxford) that I mentioned in an earlier blog. This is a deep dive into quantum information science, not for the timid or anyone looking for a quick summary. But I found it illuminated many points for me, especially in viewing any quantum computation as essentially a very elaborate quantum interference experiment. If you are familiar with regular wave interference (drop 2 stones in a pond and watch how the ripples interact) and/or the double-slit experiment this will make complete sense.

Also Read:

Simulating Quantum Computers. Innovation in Verification

Quantum Advantage is About the Algorithm, not the Computer

Quantum Computing Technologies and Challenges

January 5, 2026January 7, 2026

Chips&Media and Visionary.ai Unveil the World’s First AI-Based Full Image Signal Processor, Redefining the Future of Image Quality

Chips&Media and Visionary.ai Unveil the World’s First AI-Based Full Image Signal Processor, Redefining the Future of Image Quality
by Daniel Nenni on 01-05-2026 at 12:00 pm
Categories: Chips&Media, IP

In a groundbreaking announcement that is poised to transform digital imaging, Chips&Media, a leading provider of video codec and image processing hardware IP, has partnered with Visionary.ai, an innovative startup specializing in AI-driven vision technology, to unveil the world’s first fully AI-based Image Signal Processor (ISP). This revolutionary solution marks a significant shift from traditional hardware-fixed ISPs to a dynamic, software-powered system that leverages artificial intelligence for unparalleled image quality and adaptability.

Traditional Image Signal Processors have long been the backbone of digital cameras, smartphones, security systems, and automotive sensors. These hardware-based pipelines handle raw sensor data, performing tasks like demosaicing, noise reduction, color correction, and exposure adjustment. However, they are rigid, power-hungry, and limited in handling challenging conditions such as low light, high dynamic range (HDR), or fog. Visionary.ai has pioneered a software-based ISP that replaces conventional algorithms with AI models, achieving superior noise reduction. Results in low light show over 75% increase in detection, 91% reduction in false positives, and real-time performance that rivals or exceeds non-real-time alternatives.

By integrating Visionary.ai’s AI ISP technology with Chips&Media’s expertise in efficient hardware IP for image signal processing and computer vision, the collaboration delivers the first complete AI-native full ISP pipeline. This hybrid approach combines the flexibility of software with optimized hardware acceleration, enabling devices to process raw images with machine learning at every stage. The result? Dramatically sharper, more accurate colors, better low-light performance, and enhanced detail preservation, all while reducing power consumption and allowing over-the-air updates to improve performance post-deployment.

This innovation redefines image quality across industries. In consumer electronics, smartphones and action cameras will capture vibrant, noise-free videos in near-darkness. For automotive applications, ADAS and autonomous vehicles gain more reliable object detection in adverse weather. Security and surveillance systems benefit from clearer identification, while drones, medical imaging, robotics, and IoT devices see boosted accuracy in machine vision tasks. The AI ISP can be tuned for specific needs emphasizing greens in agriculture or reds in medical diagnostics and offering customization unmatched by fixed hardware.

What sets this apart as the “world’s first” is its end-to-end AI integration: unlike partial AI enhancements from competitors like Ambarella or Sony, this is a comprehensive replacement of the traditional ISP pipeline with predictive, learning-based processing. Running efficiently on edge devices, it addresses the “garbage-in, garbage-out” problem in AI vision systems by providing cleaner input data from the start.

As AI becomes a standard feature in imaging, this partnership signals a new era where cameras evolve intelligently over time. Chips&Media and Visionary.ai are not just improving image quality, they are future-proofing vision technology, empowering devices to see the world more like the human eye, but better. This breakthrough promises to accelerate advancements in edge AI, making high-performance imaging accessible and affordable worldwide.

Contact Chips&Media

Also Read:

2026 Outlook with William Wang of ChipAgents.ai

2026 Outlook With Mahesh Tirupattur of Analog Bits

Silicon Catalyst: Searching for the Next Great Start-up

January 5, 2026March 6, 2026

2026 Outlook with William Wang of ChipAgents.ai

2026 Outlook with William Wang of ChipAgents.ai
by Daniel Nenni on 01-05-2026 at 10:00 am
Categories: AI, CEO Interviews, ChipAgents AI, EDA

William Wang is a world-leading expert in artificial intelligence, specializing in generative AI and large language models. As the Founder, CEO, and Chairman of Alpha Design AI, he brings a wealth of experience from academia and industry, having previously shipped Amazon Q at Amazon AWS Bedrock

A Mellichamp Chair Professor of AI at UCSB, William has been recognized with prestigious honors such as the IEEE Laplace Award, BCS Karen Spärck Jones Award, NSF CAREER Award, IEEE AI’s 10 to Watch, and the DARPA Young Faculty Award.

William has published over 250+ articles at premier AI venues and widely cited in top academic conferences and media outlets such as VentureBeat, Wired, Fortune, and SemiWiki.com. William is at the forefront of AI innovation, driving the next generation of AI-powered semiconductor design and verification.

Tell us a little bit about yourself and your company.

I’m William Wang, founder and CEO of ChipAgents.ai. I’m also a professor of AI at UC Santa Barbara. ChipAgents builds an agentic AI platform for semiconductor design and verification, helping RTL, DV, and CAD teams accelerate spec-to-silicon workflows using AI agents that integrate directly into existing EDA environments.

What was the most exciting high point of 2025 for your company?

In 2025, we achieved large-scale production deployments with multiple tier-1 semiconductor companies and saw rapid expansion from pilot teams to hundreds of engineers at a single customer. The scale of real usage, measured in billions of tokens and daily active engineers, strongly validated product-market fit.

What was the biggest challenge your company faced in 2025?

The biggest challenge was scaling from early adopters to enterprise-wide deployments while meeting strict security, infrastructure, and workflow integration requirements across very different semiconductor organizations.

How is your company’s work addressing this challenge?

We invested heavily in enterprise readiness, including different deployment environments, fine-grained access control, auditability, and deep integration with customers’ existing RTL, DV, and CAD toolchains, without forcing workflow changes.

What do you think the biggest growth area for 2026 will be, and why?

The biggest growth area in 2026 will be AI-native verification, debug, and system-level reasoning. As designs grow more complex, verification productivity, not raw RTL coding, is becoming the primary bottleneck.

How is your company’s work addressing this growth?

ChipAgents focuses on multi-agent reasoning for root-cause analysis, coverage closure, testbench generation, and design-verification co-optimization. Our agents operate across code, waveforms, logs, and specs, not just text.

What conferences did you attend in 2025 and how was the traffic?

We attended major industry events including DAC, DVCon, and several private semiconductor and EDA executive summits. Traffic and engagement were very strong, with a noticeable increase in hands-on technical discussions rather than exploratory conversations. It’s great to see the industry embracing our new AI agents platform to be a force multiplier for their tapeout projects.

Will you participate in conferences going forward? Same or more?

Yes. We plan to participate in more conferences, with a stronger focus on targeted executive meetings, closed-door technical sessions, and customer-led use-case discussions rather than broad booth marketing.

How do customers normally engage with your company?

Customers typically start with a technical evaluation or pilot, followed by expansion into production teams. Engagement is highly collaborative, with close interaction between our engineering team and customer CAD, RTL, and DV groups.

Are you incorporating AI into your products?

Yes. AI is core to our product. ChipAgents is built around multi-agent systems designed specifically for semiconductor design and verification workflows.

Is AI affecting the way you develop your products?

Absolutely. We use AI internally for rapid prototyping, testing, and workflow optimization, and customer feedback from real production usage directly shapes how our agents evolve.

Additional comments?

AI in semiconductors is shifting from experimentation to mission-critical infrastructure. The winners will be platforms that integrate deeply, respect existing workflows, and deliver measurable productivity gains.

CONTACT ChipAgents

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January 5, 2026January 7, 2026

2026 Outlook With Mahesh Tirupattur of Analog Bits

2026 Outlook With Mahesh Tirupattur of Analog Bits
by Daniel Nenni on 01-05-2026 at 6:00 am
Categories: Analog Bits, CEO Interviews, IP

Tell us a little bit about yourself and your company.

As CEO of Analog Bits, I am quite excited to be at the helm of a company that plays a critical role in managing power both efficiently and in an intelligent manner. The sustainability challenges resulting from the explosive growth in AI demand this. I joined the company over 22 years ago and became CEO in 2024. I have seen very strong growth for the company during 2025.

So, you asked about Analog Bits. Well, we are the industry’s leading supplier of mixed signal IP for intelligent energy and power management in a broad range of semiconductor products. We have a track record spanning over 30 years delivering silicon-proven IPs on the latest process nodes. We have an established reputation for easy and reliable integration into advanced SoCs through all the major silicon foundries, and Analog Bits has an outstanding heritage of first-time working IP that lowers risk. Our leading low-power integrated clocking, sensors, and interconnect IP are pervasive in virtually all of today’s semiconductors, resulting in billions of our IP cores fabricated in customer silicon, from 0.35 micron to 2nm processes.

What was the most exciting high point of 2025 for your company?

Demonstrating first working silicon of several of our IPs on test chips using TSMC N2P and demonstrating N3 IPs on our customers’ products. And demonstrating power observability and delivering power savings on our power sensors and LDO IPs. We presented five joint TSMC OIP papers with customers such as ARM, Cerebras, NXP, Socionext and Semidrive in three continents. This work demonstrated successful use cases of our IPs in AI, data center and automotive applications. Furthermore, we received the Analog IP Partner of the Year Award from TSMC.

What was the biggest challenge your company faced in 2025?

The biggest challenge was to keep up with the fast pace of demand from the industry because of AI driving growth. We had to make sure we built not only the best engineering products, but also achieve the scale needed to support market demands. We had to build teams that were scalable and able to adapt quickly to changing needs and requirements to deliver solutions with the highest quality. Another challenge we addressed was to enhance financial discipline and structure to help the IPO process of our parent company.

How is your company’s work addressing this challenge?

In addition to our engineering team continuing to grow their skills on advanced node designs, we also stayed close to our customers to ensure we understood their needs. So, our customer-facing team not only participated in many industry events to present papers and showcase our solutions but also spent a lot of time directly with customers. This meant spending a lot of time on planes to ensure first-hand that our IP solutions were meeting their needs.

What do you think the biggest growth area for 2026 will be, and why?

Clearly AI is the buzzword of the moment, but that is a very broad term. For Analog Bits, it translates to huge growth opportunities in areas like data centers and automotive. Today, we see that helping our customers manage power will also optimize performance. These qualities go hand in hand. We see the biggest growth opportunity is helping our customers to gain greater insights into power and managing power for the best performance.

How is your company’s work addressing this growth?

A key benefit of our technology is something we call the Intelligent Power Architecture. This means providing a way to manage the power within an SoC in a smart way, monitoring power on-chip so that you can optimize power utilization, while not compromising on performance. High accuracy temperature sensors and power glitch sensors are key IPs that can detect abnormalities in SoC designs. And our LDOs, regulators and PLLs help balance performance and power.

Is AI affecting the way you develop your products?

Of course, we are not different than anyone else in this industry in that AI is certainly going to change the way we develop products. For example, Analog Bits collaborates with large system companies designing AI SoC’s who face a myriad of energy efficiency challenges. This allows us to develop smart mixed-signal IPs to solve these application needs.

What conferences did you attend in 2025 and how was the traffic?

We attended several conferences around the world addressing many parts of the value chain, from design (e.g., DAC) to manufacturing (e.g., TSMC, GF and Samsung events globally). These days, most of these conferences are not about traffic but about engaging with customers and partners around the world so that we can be highly responsive to their rapidly changing needs.

Will you participate in conferences in 2026? Same or more as 2025?

Indeed, this will be an important part of our strategy for customer and partner engagement in 2026. We will continue as we did in 2025 but also review and explore what makes sense to do more of.

How do customers normally engage with your company?

Our customers are truly global. They reach out to us through events we attend, our website and our sales channels. We license over 200 IPs each year for 90+ customer engagements. It is exciting to see more system companies license IPs from us directly even though they work with large ASIC houses. This is a good indication that we are solving problems that have system-level importance.

Additional comments?

The analog IPs we are developing are no longer an end of the line purchase decision. The IPs we develop deliver architectural-level impact and we are excited to build upon our success of 2025 and look forward to even more success in 2026.

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