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2026 Outlook with Cristian Amitroaie, Founder and CEO of AMIQ EDA

2026 Outlook with Cristian Amitroaie, Founder and CEO of AMIQ EDA
by Daniel Nenni on 01-20-2026 at 8:00 am
Categories: AMIQ EDA, EDA

AMIQ DAC Cropped

Cristian Amitroaie is the Founder and CEO of AMIQ EDA,  specializing in software tools for the semiconductor design and verification industry. He co-founded AMIQ in 2003 as a consulting services company and established the AMIQ EDA business unit in 2008 to productize internal tools as commercial solutions. These tools, including DVT IDE and Verissimo SystemVerilog Linter, are used by engineers to improve coding quality and efficiency in hardware design and verification.

Can you tell us a little bit about your company?

Since 2008, we have been providing innovative software tools to benefit both designers and verification engineers. We help our users increase the speed and quality of new code development while implementing best practices. We make it easier to maintain legacy code, accelerate language and methodology learning, simplify debugging, and automatically generate accurate documentation. Our users say they can’t imagine coding without our tools.

What was the most exciting high point of 2025 for your company?

When we introduced our AI Assistant in our DVT IDE family back in 2024, we embarked on a journey to find appropriate ways to leverage AI for the benefit of our users. This past year has been quite exciting on this front. We’ve added new AI-based features to DVT IDE, leveraging all the design and testbench knowledge we’ve compiled from the user code. For example, AI Assistant can now insert context-aware code completion generated from any large language model (LLM) as the user types. AI Assistant also has the ability to auto-correct and explain compilation problems, saving even more time for users.
What was the biggest challenge your company faced in 2025?

The AI space is huge, and it’s challenging to identify the technologies that best apply to our products and can provide the most benefit to our users. It takes significant time and resources to add these new AI features, and we always wonder whether they will be used enough and provide sufficient value to be worth our investment. In addition, the AI space is evolving and expanding rapidly, so today’s state of the art will be outdated within a few months.

How is your company’s work addressing this biggest challenge?

We cast a wide net as we look for potentially useful AI technologies, and we bring in experts to guide us when appropriate. We also work closely with our most advanced users to validate AI features before we roll them out to our complete customer base. The good news is that this approach is working. We’ve seen rapid uptake of AI features among our users and a lot of enthusiasm for more capabilities going forward.

What do you think the biggest growth area for 2026 will be, and why?

Maybe it’s obvious at this point, but we certainly expect AI to become a bigger part of our product suite and to drive our business. AI Assistant will do more in DVT IDE, and we’re integrating more AI-enabled features to further help our users create and debug design and verification code. We’re also working on ways to provides access to our internal models for both IDE users and AI developers. In addition, we’re adding AI features to both Verissimo SystemVerilog Linter and Specador Documentation Generator as we speak.

How is your company’s work addressing this growth?

We just need to keep doing what’s working now: keep a close eye on AI technologies, call in experts as needed, and work with users to validate the value of new features. In addition, we use our DVT compilers and Verissimo to ensure that all code generated by all AI agents is correct.

Is AI affecting the way you develop your products?

Part of our constant monitoring of AI technologies includes looking for ways to help our internal development process. Like many programming teams, we’re finding that AI can suggest solutions to real problems and help us develop code more quickly. Using AI ourselves helps us to understand its strengths and limitations, plus think of more ways to help our users develop their own code.

What conferences did you attend in 2025 and how was the traffic?

Traffic at conferences and conventions remains strong. We attended and exhibited at our usual three in-person events: the Design Automation Conference (DAC) and the Design and Verification Conference (DVCon) in the U.S., as well as DVCon Europe. Our international distributors also represent us at local events, including SemIsrael and workshops in Japan.

Will you attend conferences in 2026? Same or more?

We love it when our users stop by our booth to say hello and of course we always meet some new potential users as well. So we will be attending all the same events again this year.

Additional questions or final comments?

2025 was another year of growth and success for AMIQ EDA, and we anticipate the same for this year. Thank you for the chance to discuss the status of our company and our industry. We’ll continue posting on SemiWiki to keep you up to date on our progress.

Contact Amiq EDA

Also Read:

Runtime Elaboration of UVM Verification Code

Better Automatic Generation of Documentation from RTL Code

AMIQ EDA at the 2025 Design Automation Conference #62DAC

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Pushing the Packed SIMD Extension Over the Line: An Update on the Progress of Key RISC-V Extension

Pushing the Packed SIMD Extension Over the Line: An Update on the Progress of Key RISC-V Extension
by Daniel Nenni on 01-20-2026 at 6:00 am
Categories: Andes Technology, Events, IP, RISC-V

Pushing the Packed SIMD Extension Over the Line Andes RISCV Summit

The rapid growth of signal processing workloads in embedded, mobile, and edge computing systems has intensified the need for efficient, low-latency computation. Rich Fuhler’s update on the RISC-V Packed SIMD extension highlights why scalar SIMD digital signal processing (DSP) instructions are becoming a critical architectural feature and how the RISC-V ecosystem is moving closer to standardizing and deploying them at scale.

Packed SIMD, sometimes referred to as scalar SIMD, occupies a middle ground between purely scalar execution and full vector or GPU-style parallelism. Rather than operating on long vectors, packed SIMD instructions perform the same operation on multiple narrow data elements packed into a single scalar register. This approach is particularly effective for DSP-heavy workloads such as audio codecs, image processing, and communications algorithms, where operations like saturated arithmetic, multiply-accumulate (MAC), and bit manipulation dominate execution profiles.

One of the primary motivations for packed SIMD instructions is their suitability for latency-sensitive and deterministic workloads. Many DSP applications must meet strict real-time deadlines and cannot tolerate the overhead or nondeterminism associated with offloading computation to GPUs or wide vector units. Scalar SIMD instructions reduce instruction count and execution cycles while remaining tightly integrated into the scalar pipeline, enabling predictable timing behavior that is essential for real-time systems such as audio processing chains or control loops in industrial applications.

Power and silicon area efficiency are equally important drivers. In embedded and IoT devices, full SIMD or vector units often impose prohibitive costs in terms of energy consumption and die area. The presentation highlights a striking comparison from Andes Technology: a vector extension with two vector processing units can require roughly 850K logic gates, whereas the packed SIMD extension can be implemented in approximately 80K gates. This order-of-magnitude difference makes packed SIMD an attractive solution for designers who need higher performance than scalar code can deliver but cannot afford the overhead of full vector hardware.

As a result, a wide range of markets stand to benefit from the standardization of packed SIMD in RISC-V. These include mobile and edge AI, automotive and industrial IoT, consumer electronics, communications infrastructure such as 5G and satellite systems, and even microcontroller-class devices. In all of these domains, workloads frequently involve fixed-point arithmetic and repetitive DSP kernels that map naturally to packed SIMD operations.

From a standardization perspective, the Packed SIMD extension has reached an important consolidation phase. Instruction definitions that were previously scattered across multiple documents are being combined, with the majority now captured in the v0.92 draft of the specification, albeit with some renaming. New architectural tests have been written, and discussions are ongoing with the Architecture Review Committee to finalize instruction layout and formatting before formal review. An asciidoc version of the specification is expected to be published to GitHub, signaling increasing maturity and openness of the extension.

Toolchain support is also progressing rapidly. Updates for GCC, LLVM, and binutils-gdb have already been pushed upstream, ensuring that compiler and debugger ecosystems can take advantage of packed SIMD instructions. Work on C and C++ intrinsic functions is underway, which will make it easier for application developers to explicitly leverage the extension without resorting to hand-written assembly. In addition, architectural models and compliance tools such as SAIL, ACTs, and RISCOF are being prepared for public availability, alongside simulators like QEMU and Spike.

Bottom line: Benchmarking results presented using the Andes D23 core demonstrate substantial performance gains across a wide range of audio codecs and DSP workloads when packed SIMD is enabled, compared to configurations without DSP support. These results reinforce the extension’s practical value and underline why pushing the Packed SIMD extension “over the line” is a key milestone for the RISC-V ecosystem

Also Read:

RISC-V: Powering the Era of Intelligent General Computing

Navigating SoC Tradeoffs from IP to Ecosystem

S2C, MachineWare, and Andes Introduce RISC-V Co-Emulation Solution to Accelerate Chip Development

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2026 Outlook with Richard Hegberg of Caspia Technologies

2026 Outlook with Richard Hegberg of Caspia Technologies
by Daniel Nenni on 01-19-2026 at 10:00 am
Categories: AI, Caspia Technologies, Security

Richard Hegberg

Tell us a little bit about yourself and your company

Richard Hegberg

I’m Rick Hegberg and I’ve been CEO of Caspia Technologies since 2024. I have a deep semiconductor background, including CEO roles at three semiconductor start-ups and executive roles at SanDisk/WD, Qualcomm, Atheros, Numonyx/Micron, ATI/AMD, and VLSI Technology.

Throughout my career I’ve worked with the global semiconductor supply chain to solve many challenges, both technical and otherwise. Thanks to the growing use of AI, the recent rise in hardware-focused cyberattacks caught my attention.

Something needed to be done to protect the security of the hardware root of trust and I felt this could only be accomplished with a ground-up approach to chip design that incorporated rigorous hardware security verification and validation. This is the mission of Caspia Technologies. I felt the company was developing a truly holistic and effective approach to ensure superior security for future chip designs and so I joined them to help take the vision to the next level.

What was the most exciting high point of 2025 for your company? 

We had many breakthrough events over the course of the year. Part of that was discovering real security flaws in popular open-source designs. There is a lot of work ahead for the entire industry to tighten hardware security.

I would say the most memorable event for me was the introduction of our first product, CODAx, which performs static security analysis on early RTL designs. The idea is to find and fix weak security practices early, before they lead to potential catastrophic security breaches in the field. Think of CODAx as a static “linting” tool that is specifically focused on secure design practices. This is the tool we used to find the weaknesses in the open-source designs I mentioned.

What was the biggest challenge your company faced in 2025?

In a word, education. We have found a wide range of awareness of the risks and pervasiveness of hardware attacks across the semiconductor supply chain. Some companies are at the forefront of addressing these problems, but many have yet to see the breadth of the problem and prioritize an approach to address it.

Related to this is a discussion we’ve had regarding the difference between security IP and secure IP. While using a commercially available hardware root of trust is a good idea, this by itself does not assure your design will be secure. The attacks that are developing are very sophisticated and protecting against them requires a larger perspective of the problem.

You can check out a recent blog post from Caspia on this topic.

How is your company’s work addressing this challenge?  

Caspia simplifies the adoption of robust security for the enterprise. This includes tools that easily fit into existing EDA flows, well-developed physical assurance methodologies, and training and curriculum development for hardware security.

Regarding tools, Caspia is currently working on a platform that contains three products:

CODAx is the static security checker I mentioned. It contains over 150 security rules that are constantly updated with trained security large language models (LLMs).

SVx tunes formal verification to look for security robustness with AI-generated security-focused assertions.

PFx facilitates dynamic security validation of completed designs using AI to harness existing co-simulation and emulation technologies.

What do you think the biggest growth area for 2026 will be, and why?

The semiconductor industry is undergoing a major shift to enhance the security hardness of chip designs. Caspia will play a key role in that shift with our security platform, methodologies, and training.

All three of the products I mentioned will move to mainstream deployment in 2026 and this will fuel significant growth for the company.

How is your company’s work addressing this growth?

I’ve already described the product pipeline we have and the expected impact that will have on our growth. Beyond that, we are working with several large players in the industry to facilitate easier adoption of our robust security technology.

Expect more information about this work in the months ahead.

Are you incorporating AI into your products? / Is AI affecting the way you develop your products?

The answer is Yes to both. Cyberattacks are continually enhanced with new AI approaches. That demands security enhancements that are also AI-driven, and Caspia has made extensive use of AI technologies to meet this challenge.

We have access to the world’s largest security threat databases. Caspia has helped to build some of them. We use the previously mentioned LLMs to continually analyze these threats to enhance our tools. Caspia is also developing a growing array of AI agents to identify threats and design weaknesses and take corrective action.  

Agentic security verification/hardening is clearly the way forward. One of our founders, Dr. Mark Tehranipoor recently did a podcast with the DAC folks that provides some good perspectives on these topics. You can listen to it here.

How do customers normally engage with your company?

We will be attending a growing number of events in 2026. For example, we are a Corporate Sponsor at the IEEE International Symposium on Hardware Oriented Security and Trust (HOST), and we will likely be presenting at conferences such as GOMAC and DAC. You can find us at these events, and you can also reach out to us at our website here. We’d be happy to explore how we can help.

Additional comments? 

Security hardening for chip design is no longer an option; it is a requirement for continued success and growth in the market.  Caspia is ready to show you the way forward with well-developed methodologies, training and easy-to-adopt tools. Let us help you secure the future of your next design.

WEBINAR: Why AI-Assisted Security Verification For Chip Design is So Important

Also Read:

A Six-Minute Journey to Secure Chip Design with Caspia

Caspia Focuses Security Requirements at DAC

CEO Interview with Richard Hegberg of Caspia Technologies

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Siemens EDA Illuminates the Complexity of PCB Design

Siemens EDA Illuminates the Complexity of PCB Design
by Mike Gianfagna on 01-19-2026 at 6:00 am
Categories: EDA, Siemens EDA

Siemens EDA Illuminates the Complexity of PCB Design

As heterogeneous multi-die design becomes more prevalent, the focus on advanced analysis has predictably shifted in that direction. While these challenges are important to overcome, we shouldn’t lose sight of how complete systems are built. Short and long reach communication channels, system-level power management and the all-important PCB are still fundamental building blocks for every complex system.

Siemens Digital Industries Software takes a broad and holistic view of system design, and a recent white paper is a great example of that perspective at work. The paper is titled How long is that trace? and it illustrates the complexity of PCB analysis and why it’s so important to get it right. If you are engaged in delivering complex systems, this white paper provides important information to ensure a successful project. A download link is coming but first let’s examine some of the topics covered when Siemens EDA illuminates the complexity of PCB design.

Getting it Right – Signal Analysis

Measuring and matching propagation delay for complex signal traces is both critical for performance and quite challenging to accomplish.  The white paper points out that:

To match the signal propagation time of two traces, PCB designers make the length of the two traces match down to a few thousandths of an inch (mils). While this is a good place to start, other factors influence the delay of the signal.

The impact of how high frequency signals and vias affect propagation delay is discussed in some detail. The piece explains how to use phase angle to calculate trace delay for example.  The question is posed:

Since different frequencies propagate at different speeds, how does that speed difference affect a digital signal that is not a sine wave?

Fourier analysis is used to show how digital signals containing high frequency components are affected by the interconnect. The relationship of magnitude and phase is discussed across a spectrum of the harmonic frequencies of the signals involved.  The figure below is an example of a plot to examine the composition of a digital signal. There is a lot more to getting this right than you may think. This white paper does a great job explaining what’s involved.

A digital signal and the harmonics that create the edge rate

Getting it Right – Via Design

The white paper also discusses how vias impact the edge rate and thus the trace delay. The piece explains an important point related to this issue:

If vias passed all frequencies of a signal equally, their impact would not be as significant. But vias impact some frequencies more than others, so via characteristics also affect signal delay.

There is a lot of rich and relevant detail presented regarding how via design impacts trace delay. Slightly different via geometries are analyzed in detail. It turns out that via geometry can have significant and non-intuitive impact on overall trace delay and thus overall system performance.

Again, frequency analysis and harmonics play a role in finding the right answers. The impact of various via return paths are also examined. The detail presented will get your attention.

To Learn More

After reading this white paper you will realize that copper length is not the only factor impacting the performance of a PCB trace. It is pointed out that vias have an inherent delay due to their span, but other characteristics add delay and distortion to the signal. The bottom line is the time it takes a signal to rise above the switching threshold at the driver to the time it takes to cross the switching threshold at the receiver.

Edge rate is key. The piece points out that the signal edge is composed of a fundamental sine wave and multiple higher frequency harmonics, all of which must have a certain amplitude and phase to reproduce the signal. When you want to know what the final performance will be, using a simulator is the best way. To find out more about this important system level analysis and optimization process download your copy of the Siemens Digital Industries white paper here. And that’s how Siemens EDA illuminates the complexity of PCB design.

Also Read:

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Accelerating Advanced FPGA-Based SoC Prototyping With S2C

Accelerating Advanced FPGA-Based SoC Prototyping With S2C
by Daniel Nenni on 01-18-2026 at 12:00 pm
Categories: EDA, Prototyping, S2C EDA

Prodigy S8 100 Logic Systems

Having spent a significant amount of my career in EDA and IP I can tell you first hand how important picking the right prototyping partner is. I have known S2C since my interview with CEO Toshio Nakama in 2017. It has been a pleasure working with them and I look forward to seeing an S2C update at DVCon the first week of March here in Silicon Valley. Specifically I am looking forward to seeing the new Prodigy Logic System.

The Prodigy S8-100 Logic System-VP1902 is a high-performance FPGA-based prototyping platform designed to accelerate advanced System-on-Chip (SoC) and ASIC development in demanding applications such as AI, high-performance computing (HPC), networking, and RISC-V processor design. Built and marketed by S2C Inc., a leader in FPGA prototyping solutions, the S8-100 series harnesses the latest AMD Versal™ Premium VP1902 adaptive SoC as its core building block. This integration enables developers to prototype large-scale digital logic designs with unprecedented gate capacity and I/O flexibility compared to previous generations of prototyping systems.

At its core, the Prodigy S8-100 platform is about bridging the gap between RTL design and full hardware validation before production silicon is available. FPGA prototyping has become essential because software development, validation, and system-level debugging often cannot wait for the final ASIC to be manufactured. The S8-100’s modular architecture enables hardware teams to test, refine, and validate entire SoCs—right down to peripheral interfaces—on reconfigurable hardware. Unlike simple simulation environments, this FPGA-based approach allows real execution of logic under real timing conditions, enabling much earlier detection of integration bugs and performance bottlenecks.

A defining feature of the Prodigy S8-100 is its massive logic capacity, with each VP1902 FPGA supporting up to 100 million ASIC equivalent gates.

Systems can be configured in three variants:

In multi-FPGA configurations, the total effective capacity scales up to 400 million gates, providing headroom for extremely complex designs that incorporate multiple cores, accelerators, memory hierarchies, and communication fabrics.

Resource-wise, the S8-100 offers rich internal capabilities including tens of thousands of logic cells, megabits of on-chip RAM, and thousands of DSP slices per FPGA. It also boasts advanced I/O support with high-speed transceivers and contemporary interface standards such as PCIe Gen5, enabling real-world connectivity with host systems and other devices. The result is a prototyping system capable of both high throughput and real-world system integration testing.

Beyond raw hardware, the Prodigy S8-100 ecosystem includes a suite of productivity tools to streamline prototyping workflows. S2C’s software, including PlayerPro-CT for partitioning and ProtoBridge for co-simulation, helps automate complex multi-FPGA design partitioning and bitstream generation. An extensive catalog of “Prototype Ready IP” daughter cards further expands the platform’s usability, offering pre-validated interface modules (for memory, Ethernet, GPIO, and more) that plug into the system without consuming valuable FPGA logic. These tools together reduce setup time, simplify board bring-up, and allow teams to concentrate on verification and software development instead of hardware plumbing.

The Prodigy S8-100 is also gaining traction in emerging markets such as RISC-V SoC development, where developers need to validate not just CPU cores but entire subsystems that include custom extensions and accelerators. In a recent collaboration with Andes Technology, the S8-100 platform has been used to prototype advanced RISC-V designs with custom instructions and high-bandwidth interfaces, demonstrating its value in next-generation CPU and SoC workflows.

Bottom line: The Prodigy S8-100 Logic System-VP1902 represents a state-of-the-art prototyping solution that addresses the challenges of modern digital design: huge logic capacity, flexible I/O, scalable configurations, and robust toolchains. For semiconductor developers working on cutting-edge chips—from AI accelerators to custom processors—platforms like the S8-100 make it possible to validate complex designs thoroughly, accelerate software readiness, and reduce the risk associated with first-silicon prototypes. As design complexity continues to grow, FPGA-based prototyping systems like the Prodigy S8-100 will remain essential tools in the semiconductor development cycle.

 

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Also Read:

S2C, MachineWare, and Andes Introduce RISC-V Co-Emulation Solution to Accelerate Chip Development

FPGA Prototyping in Practice: Addressing Peripheral Connectivity Challenges

S2C Advances RISC-V Ecosystem, Accelerating Innovation at 2025 Summit China

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CEO Interview with Moshe Tanach of NeuReality

CEO Interview with Moshe Tanach of NeuReality
by Daniel Nenni on 01-16-2026 at 2:00 pm
Categories: CEO Interviews

Moshe Tanach

Moshe Tanach is co-founder and CEO of NeuReality. Prior to founding the company, he held senior engineering leadership roles at Marvell and Intel, where he led complex wireless and networking products from architecture through mass production. He also served as AVP of R&D at DesignArt Networks (later acquired by Qualcomm), where he led development of 4G base station technologies.

Tell us about your company? What problems are you solving?

NeuReality was established by industry veterans from Nvidia-Mellanox, Intel, and Marvell, united by a vision to transform datacenter infrastructure for the AI era. As computational focus shifts from CPUs to GPUs and specialized AI processors, we recognized that general-purpose legacy CPU and NIC architectures had become bottlenecks, limiting high-end GPU performance and efficiency. Our mission is to redefine these system components, prioritizing efficiency and cost-effectiveness for next-generation AI infrastructure.

We address a critical challenge in today’s AI datacenters — underutilized GPUs idling while waiting for data. Whether in distributed training of large language models or in disaggregated inference pipelines, the network connecting these GPUs is increasingly vital both in bandwidth and latency. The core challenge is to move large volumes of data between GPUs instantly, enabling continuous computation. Failure to do so results in significant cost inefficiencies and undermines the profitability of AI applications.

Our purpose-built heterogeneous compute architecture, advanced AI networking, and software-first philosophy led to the launch of our NR1 product. NR1 integrates an embedded AI-NIC and is delivered with comprehensive inference-serving and networking software stacks. These are natively integrated with MLOps, orchestration tools, AI frameworks, and xCCL libraries, ensuring rapid innovation and optimal GPU utilization. We are now developing our second-generation of products starting with the NR2 AI-SuperNIC, focused exclusively on GPU-direct, east-west communication for large-scale AI factories.

What is the biggest pain point that you are solving today for customers?

The paradigm in datacenter design has shifted from optimizing individual server nodes to architecting entire server racks and clusters, scaling up to hundreds or thousands of GPUs. The interconnect between these GPU nodes and racks must match the performance of in-node connectivity, delivering maximum bandwidth and minimal latency.

Our customers’ primary pain point is that current networking solutions, such as those from Nvidia and Broadcom, are neither wide nor fast enough, resulting in wasted GPU resources and increased operational costs due to power inefficiencies. To address this, we developed the NR2 AI-SuperNIC, purpose-built for scale-out AI systems. Free from legacy constraints, NR2 offers 1.6Tbps bandwidth, sub-500ns latency, and native support for GPU-direct interfaces over RoCE and UET. A flexible control plane and full hardware offload to the data plane supports all distributed collective libraries, orchestration, and MLOps protocols. By eliminating unnecessary overhead, NR2 achieves industry-leading power efficiency, a critical advantage as the number of NIC ports and wire speeds continue to rise.

Once you secure the best GPUs and XPUs for AI, network performance and integration into AI workflows becomes the ultimate differentiator for AI datacenters and multi-site “AI brains.”

What keeps your customers up at night?

Our customers are focused on three core challenges:

  • Maximizing the ROI of their GPU investments
  • Managing AI infrastructure growth in a cost-effective, sustainable manner
  • Avoiding lock-in to proprietary, closed solutions

From the outset, we addressed these concerns with a software-first, open-standards approach. This gives customers the flexibility to mix accelerators, adapt architectures, and scale without overhauling their entire system while leveraging the power of the developers’ communities. Customers recognize that superior hardware alone is insufficient. Robust, open software that leverages community-driven innovation and supports new algorithms and deployment models, is essential to unlocking the full value of their infrastructure. Our software-first strategy has earned significant trust and respect from customers using our NR1 AI-NIC with our Inference Serving Stack (NR-ISS) and our Scale-out Networking Stack (NR-SONS) and those preparing to adopt NR2 AI-SuperNIC.

What does the competitive landscape look like and how do you differentiate? What new features/technology are you working on?

The competitive landscape is dominated by Nvidia’s ConnectX and Broadcom’s Thor General-purpose NIC products. While these solutions are advancing in bandwidth, their latency remains above 1 microsecond, which becomes a significant bottleneck as speeds increase to 800G and 1.6T. Hyperscalers and other leading customers are demanding faster, more efficient networking to pair with Nvidia GPUs and their own custom XPUs. Without such solutions, they are compelled to develop their own NICs to overcome current limitations, a task found to be long and complex.

NeuReality differentiates itself by delivering double the bandwidth and less than half the latency of competing products. We then deliver exclusive AI features in the core network engines, such as the packet processors and the hardened transport layers, and the integrated system functions, such as PCIe switch and peripheral interfaces.

We defined and designed NR2 AI-SuperNIC die, package and board in collaboration with market leaders to accommodate diverse system topologies. Features include:

  • Integrated UALink for high-performance in-node connectivity between CPUs and GPUs, bridging scale-up and scale-out networks
  • Embedded PCIe switch for flexible system architectures
  • xCCL acceleration for both mathematical and non-mathematical collectives, a unique capability
  • Exceptional power efficiency—2.5W per 100G, setting a new industry benchmark
  • Comprehensive, open-source software stack with native support for all major AI frameworks and libraries.

Looking at this table, you can clearly see the advantage of NR2 AI-SuperNIC compared to today’s solutions and to future roadmap solutions from our competition:

How do customers normally engage with your company?

We work directly with hyperscalers, neocloud customers, and enterprises, providing support both directly and through system integrators and OEMs. Our engineering team invests in understanding each customer’s unique needs, collaborating closely to deliver tailored solutions. Most customers approach us not simply seeking a new networking solution but aiming to maximize the value of their GPU investments.

Engagements often begin with proof-of-concept (POC) projects. With our NR1 AI-CPU product, we established a robust ecosystem of partners, channels, and lead customers to ensure early product validation and customer satisfaction. For NR2, we are inviting partners to join the AI-SuperNIC Partnership and validate interoperability with their hardware, software stacks, and communication libraries well before full-scale deployment.

What is next in the evolution of AI infrastructure?

Looking ahead, we anticipate two key trends will shape customer focus and industry direction.

First, as AI workloads become increasingly dynamic and distributed, customers will demand even greater flexibility and automation in their infrastructure. This will drive the adoption of intelligent orchestration platforms that can optimize resource allocation in real time, ensuring maximum efficiency and responsiveness across diverse environments. To me, it’s crystal clear that Rack-scale design is not enough. Scale-out must evolve together with scale-up to support ease of deployment that is less dependent on the location of GPUs in the node, server, rack, or cluster of racks.

Second, we expect sustainability and energy efficiency to become central decision factors for enterprises building or using large-scale AI infrastructure. Organizations will seek solutions that not only deliver top tier performance but also minimize environmental impact and operational costs. As a result, power-efficient networking and hardware offload will become critical differentiators in the market.

CONTACT NEUREALITY

Also Read:

2026 Outlook with Paul Neil of Mach42

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Podcast EP327: Third Quarter 2025 Electronic Design Market Data Report Overview and More with Dr. Walden Rhines

Podcast EP327: Third Quarter 2025 Electronic Design Market Data Report Overview and More with Dr. Walden Rhines
by Daniel Nenni on 01-16-2026 at 10:00 am

Daniel is joined by Wally Rhines, CEO of Silvaco, about the Electronic Design Market Data report that was just released. Wally is the industry coordinator for the EDA data collection program called EDMD. SEMI and the Electronic System Design Alliance collect data from almost all of the electronic design automation companies in the world and compile it by product category and region of the world where the sales occurred. It’s the most reliable data for the EDA industry and provides insight into what design tools and IP are in highest demand around the world.

Dan explores the results of the current report in detail with Wally, who explains that the current report documents another good quarter for EDA with an 8.8% overall growth compared to last year. Total revenue was $5.6B for the quarter, with EDA now solidly delivering over $20B in annual run rate. Dan and Wally explore the details of the report and discuss worldwide trends in EDA, IP and services across various regions. Some of the insights are surprising. Worldwide EDA employment is also discussed, which grew 17.3% compared to last year representing approximately 73,000 employees.

Dan also discusses Wally’s recent decision to join Silvaco as CEO. Wally offers some excellent insights into what drove that decision and what the future looks like.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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Verification Futures with Bronco AI Agents for DV Debug

Verification Futures with Bronco AI Agents for DV Debug
by Daniel Nenni on 01-16-2026 at 6:00 am
Categories: AI, Bronco AI, EDA, Events

Bronco AI Verification Futures 2025

Verification has become the dominant bottleneck in modern chip design. As much as 70% of the overall design cycle is now spent on verification, a figure driven upward by increasing design complexity, compressed schedules, and a chronic shortage of design verification (DV) engineering bandwidth. Modern chips generate thousands of tests per night, producing massive volumes of logs and waveforms. Within this flood of data, engineers must find the rare, chip-killing bug hidden among hundreds of failures. Verification today is fundamentally a large-scale data analysis problem, repeated daily under intense time pressure.

Traditional approaches struggle to scale with this reality. Human engineers are exceptionally strong at deep, creative reasoning about a single complex failure, but they cannot efficiently process thousands of datasets simultaneously. Classical machine learning techniques, while powerful in narrow contexts, face severe limitations in DV. They often fail to generalize across architectures such as CPUs, GPUs, NoCs, or memory subsystems. Training data is difficult to collect due to IP sensitivity, labeling requires expert engineers, and constant design evolution creates distribution shifts between chip versions. These constraints limit the long-term impact of conventional ML in verification.

Bronco AI agents for DV represent a step change. Instead of relying on narrow models trained for specific tasks, agent-based systems leverage large reasoning models combined with tool use, memory, and decision-making loops. These agents generalize more effectively because they are trained on internet-scale code and problem-solving data rather than proprietary design specifics. They can be steered through natural language, allowing DV engineers to guide investigations intuitively. Crucially, agents learn from metadata and patterns rather than memorizing raw data, reducing overfitting and mitigating IP and security concerns by selectively handling and discarding context.

In DV workflows, Bronco AI agents operate much like a highly scalable junior-to-senior engineer hybrid. When a simulation fails, the agent autonomously decides how to investigate, executes standard DV actions such as log parsing and waveform inspection, and iterates until it identifies a likely root cause. If the issue exceeds its confidence threshold, the agent escalates with a well-formed ticket for a human engineer. This approach allows routine debug work to be handled automatically while preserving human expertise for the hardest problems.

The impact of this agentic approach is measurable. In real subsystem-level UVM test failures on next-generation ASICs, Bronco AI agents were able to index new regressions within minutes, adapt to unfamiliar error signatures, and build an understanding of designs containing hundreds of thousands of lines of RTL.

In one case, an agent analyzed over 100,000 lines of logs and approximately 20 GB of waveform data to identify a deeply nested root cause in less than 10 minutes, work that a DV lead estimated would have taken hours, or days for a less experienced engineer.

AI agents also fundamentally change how waveform debug is performed. Traditional waveform analysis forces engineers to scroll through laggy GUIs, manually correlating thousands of signals across time windows and following one hypothesis at a time. Agents, by contrast, can examine many signals, hierarchies, and failure modes simultaneously. They can correlate errors across CPU, memory controllers, fabrics, and accelerators, classify failures, and recognize recurring patterns across regressions.

Perhaps most importantly, these systems improve over time. By learning from past failures, tickets, and human feedback, AI agents build reusable debug playbooks, discover efficient shortcuts, and develop generalized intuition—such as recognizing which issue types tend to appear in certain subsystems. This continuous learning enables faster time-to-value without custom AI training and allows seamless integration into existing EDA flows.

Bottom line: AI agents deliver value in verification not by replacing human insight, but by amplifying it through scale, speed, and learning. As verification complexity continues to grow, agentic AI offers a practical path to closing the verification gap.

Contact Bronco for a Demo

Also Read:

Superhuman AI for Design Verification, Delivered at Scale

AI RTL Generation versus AI RTL Verification

Scaling Debug Wisdom with Bronco AI

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AI Bubble?

AI Bubble?
by Bill Jewell on 01-15-2026 at 12:00 pm
Categories: Semiconductor Intelligence, Semiconductor Services
4 Comments

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The currently strong semiconductor market is being driven by AI applications. A McKinsey survey showed 88% of businesses used AI in 2025 compared to just 55% in 2023. According to Inc.com, 306 of the S&P 500 companies mentioned AI in their third quarter 2025 earnings conference calls, up from only 53 citations three years earlier in third quarter 2022.

The WSTS December 2025 forecast called for 22% semiconductor market growth in 2025 and 26% in 2026, following 20% growth in 2024. This growth has been driven by the memory and logic categories. Memory is forecast to grow 28% in 2025 and 39% in 2026. Logic is predicted to grow 37% in 2025 and 32% in 2026. Excluding the memory and logic categories, the remainder of the semiconductor market declined 3% in 2024 and is projected to grow only 6% in 2025. The memory companies have all cited AI as their major growth driver in the last two years. Nvidia, the largest AI semiconductor company, grew its revenue 114% in 2024 and is guiding for 63% growth in 2025. Most Nvidia AI semiconductors are included in the logic category.

How long will the AI boom last? What will happen to the semiconductor market? We can look at previous bubbles in the semiconductor market for clues.

PC Bubble

The introduction of the IBM PC in 1981 led to a boom in the PC market. With IBM setting a standard for PC hardware and software, businesses felt safe investing in PCs. PC unit shipments grew 85% in 1983 and 29% in 1984. The PC boom led to a boom in the semiconductor market, especially for memory and Intel microprocessors. However, the PC boom came to an abrupt halt in 1985, as PC unit shipments fell 11 percent. The weakness in 1985 was due to several factors. Clones of IBM PCs from Compaq, Dell and HP disrupted the market. U.S. GDP growth slowed from 7% in 1984 to 4% in 1985.

The PC bust in 1985 led to a 17% decline in the semiconductor market. Memory fell 38% and Intel revenues dropped 16%. The decline was short-lived. In 1986 PC unit shipment grew 22% and semiconductors grew 23%. Memory and Intel revenues returned to strong growth in 1987.

Internet Bubble

Internet use began to explode in the 1990s as major businesses established links and the World Wide Web created standards and enabled browsing. The number of Internet users roughly doubled each year in 1995 and 1996. Users grew around 50% a year from 1997 through 2000. In 2001, growth in Internet users slowed to 21%. The rapid growth of the Internet led to the creation of numerous dot-com companies fueled by venture capital. By early 2000, rising interest rates and the lack of profitability of most dot-com startups led to a slump in investment. The NASDAQ-100 index, which was heavily weighted with dot-coms, dropped 78% from March 2000 to October 2002.

The collapse of many dot-com companies resulted in telecommunications companies having over capacity in Internet infrastructure. Cisco, the largest provider of Internet infrastructure hardware, saw revenue change from 50% plus growth in 1999 and 2000 to a 23% decline in 2001. In 2001, the semiconductor market dropped 32% with memory down 49%. The semiconductor and memory markets returned to double-digit growth in 2003.

AI Bubble?

The chart below shows the change in the semiconductor market during the PC bubble (blue line), the Internet bubble (red line) and the current AI period (green line). In the PC and Internet bubbles, the semiconductor market had two years of strong growth in the 19% to 46% range followed by major declines when the bubbles burst. In the current cycle, semiconductor growth was 20% in 2024 and is projected at 23% in 2025 and 26% in 2026.

The question is not if the AI bubble will burst, but when. Basically, all major new technologies go through a period of strong growth in the first few years. Many new companies emerge to try to take advantage of the new technology, largely driven by investments from venture capital funds. Eventually, the growth of the new technology slows or declines. Investment funds then begin to dry up. The revenues of hardware companies enabling the new technology fall, leading to semiconductor market declines. History suggests a possible bursting of the AI bubble in the next year or two.

The bubbles are not the end of the new technologies, but an adjustment. Certainly, PCs and the Internet are major economic drivers which have transformed the way of life for both business and consumers. AI also promises a major transformation. How smoothly the transformation is implemented remains to be seen.

Semiconductor Intelligence is a consulting firm providing market analysis, market insights and company analysis for anyone involved in the semiconductor industry – manufacturers, designers, foundries, suppliers, users or investors. Please contact me if you would like further information.

Bill Jewell
Semiconductor Intelligence, LLC
billjewell@sc-iq.com

Also Read:

Semiconductors Up Over 20% in 2025

U.S. Electronics Production Growing

Semiconductor Equipment Spending Healthy

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There is more to prototyping than just FPGA: See how S2C accelerates SoC Bring-Up with high productivity toolchain?

There is more to prototyping than just FPGA: See how S2C accelerates SoC Bring-Up with high productivity toolchain?
by Daniel Nenni on 01-15-2026 at 10:00 am
Categories: EDA, Prototyping, S2C EDA

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System-on-Chip designs continue to grow in scale and interface diversity, placing greater demands on prototype capacity, interconnect planning, and bring-up efficiency. These challenges arise not only in large multi-FPGA programs but also in smaller designs implemented on a single device or a small FPGA cluster. In all cases, teams must build a representative verification environment, manage logic operating at different rates, and isolate functional issues with minimal iteration time.

S2C’s FPGA solution addresses these needs through a structured prototyping ecosystem that combines automation software, implementation flows, system IP, and hardware expansion options to support efficient and predictable SoC bring-up across a wide range of design scales.

Building a Scalable System-Level Prototyping Methodology

A predictable and efficient bring-up process depends on tight coordination between software automation and hardware infrastructure. S2C’s PlayerPro™ CT software supports both automatic and guided partitioning, including interconnect planning for designs that span multiple FPGAs. Timing-driven and congestion-aware algorithms help improve partition quality and stability. For designs that do not require partitioning, PlayerPro CT also enhances gated-clock conversion and memory mapping, improving overall implementation robustness.

The RTL Compile Flow (RCF) further streamlines implementation by reducing memory footprint, improving iteration turnaround, and maintaining RTL-level visibility for downstream debug. These capabilities are valuable not only for large multi-FPGA designs, but also for projects that ultimately fit into a single FPGA yet still require controlled timing convergence and manageable compile cycles during early architectural exploration.

Clock-domain and rate matching are common requirement when integrating subsystems with different clock frequencies or operating characteristics. In practical SoC bring-up, many IP blocks—such as memory controllers, external interfaces, or third-party subsystems—are often unable to operate at their final target frequencies during early prototyping stages.

S2C addresses this challenge by providing Memory Models and Speed Adapters that decouple functional validation from frequency constraints. These mechanisms allow subsystems to run at reduced or independent rates while preserving correct transaction ordering, protocol behavior, and system-level interactions.

A representative system environment also depends on access to the appropriate peripheral interfaces without extensive custom hardware development. S2C offers a broad portfolio of daughter cards covering high-speed connectivity, memory, storage, display, and general-purpose interfaces. PCIe EP/RC, Mini-SAS, USB PHY, and SFP+/QSFP+ modules support high-bandwidth links; DDR4, LPDDR4, eMMC, and Flash modules enable memory subsystem evaluation; HDMI, DisplayPort, and MIPI D-PHY daughter cards support video and imaging use cases. GPIO headers, JTAG modules, and SerDes extensions enable signal probing and low-speed peripheral access. Together, these hardware options help teams reproduce system-level conditions that closely reflect the target deployment environment.

System-Level Debug Visibility

Debug is a critical part of prototype validation, and S2C provides mechanisms that deliver visibility at multiple levels of the system.

At the I/O level, engineers can validate basic functionality using push buttons, DIP switches, GPIOs, and UART interfaces. PlayerPro also enables virtual access to these controls, supporting remote operation and simplifying early functional checks.

For bus-level visibility, S2C offers ProtoBridge, which uses a PCIe connection to provide high-throughput transaction access suitable for software-driven stimulus generation and data movement. NTBus provides an alternative lower-bandwidth access path over embedded Ethernet.

Signal-level visibility is supported through probe insertion and waveform capture. MDM Pro enables concurrent capture of up to 16K signals across as many as eight FPGAs, with deep trace storage and support for both IP-mode and compile-time configurations—often without requiring a full recompile.

Conclusion

With a structured prototyping ecosystem and a comprehensive debug infrastructure, S2C’s Prodigy prototyping solution provides a stable foundation for building, scaling, and validating FPGA-based prototypes. Whether used for single-FPGA bring-up or large multi-board configurations, S2C enables teams to create representative verification environments, balance subsystem operation, and efficiently isolate functional issues throughout the SoC development cycle.

Contact S2C

Also Read:

S2C, MachineWare, and Andes Introduce RISC-V Co-Emulation Solution to Accelerate Chip Development

FPGA Prototyping in Practice: Addressing Peripheral Connectivity Challenges

S2C Advances RISC-V Ecosystem, Accelerating Innovation at 2025 Summit China