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Semiconductor Expert Forum

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Bringing Low-Frequency Noise into Focus

Bringing Low-Frequency Noise into Focus
by Admin on 12-23-2025 at 6:00 am
Categories: EDA, Primarius

1. Primarius offers a one stop RTN solution

Key takeaways

  • The challenge of acquiring high-quality, reproducible noise data becomes achievable with Primarius’ wafer-level low-frequency noise characterization solution, which is essential for advanced nodes.
  • The Primarius 981X family raises the bar for low-frequency noise measurement metrology with its unique advantages demonstrated below, along with recent innovative solutions such as the 9812HF and 9812AC.
  • Process engineers should use low-frequency noise as a key figure of merit for process quality monitoring and improvement during technology development. Design teams also require accurate low-frequency noise models to characterize devices and enable effective design optimization.

Noise, defined as any unwanted signal superimposed on an ideal one. Low-frequency noise is dominated by 1/f noise and RTN, both directly linked to crystalline defects in semiconductor materials. As semiconductor devices continue shrinking, even a single trap can cause current fluctuations. Consequently, this noise effect is emerging as a latent failure mechanism that threatens system performance.

Since the 28 nm technology node, low-frequency noise models have become a standard component of PDKs. Accurate RTN modeling not only supports circuit design and process optimization but also opens new avenues for statistical 1/f noise modeling and circuit simulation. High quality noise data is therefore a key modeling requirement.

Primarius offers a one-stop RTN solution
Practical challenge VS Technical breakthrough

Accurate low-frequency noise characterization demands more than a sensitive amplifier.

You need:

  • An instrument with ultra-low background noise.
  • Wide impedance matching to cover different types of DUTs.
  • High dynamic range to capture tiny fluctuations.
  • The ability to report both time-domain RTN signatures and frequency-domain PSDs with traceable statistics.

One practical breakthrough for noise test systems is the automatic, signal-aware switching between AC and DC coupling. With Primarius’ advanced low-frequency noise filtering and amplification technologies, the 981X Series Noise Testing System achieves high speed, high precision, and stable data acquisition. This core technology elevates noise testing to a new performance tier.

981X series supports automatic AC/DC coupling

9812DX: Golden standard

The Primarius 981X series Noise Testing System has been the golden standard for low frequency noise testing in the semiconductor industry for decades. It sets new records in measurement speed, system resolution, and coverage of different types of measurement requirements for flicker noise and RTN. The 9812DX, succeeding 9812D, has been adopted by leading foundries as the new golden tool for lowrequency noise testing. 9812DX stands out for its rare ability to measure both high impedance and low impedance devices with consistent accuracy.

Notable 9812DX highlights:

  • Wide voltage and current range: 200V, 200mA
  • Broad impedance matching range: 3 Ω to 30 MΩ
  • Lots of device types: Suitable for devices such as MOSFETs, BJTs, FinFETs, LDMOS, JFETs, HBTs, Diodes, Resistors, etc.
  • Hight resolution & bandwidth: 10 e-27A^2/Hz @ 20KHz
  • Ready for all advanced process nodes: 7/5/3nm and more
9812HF: VHF reach

Launched as the high bandwidth extension of the 981X family, the 9812HF is designed to bridge traditional low-frequency noise analysis and higher frequency noise concerns. This extension matters for applications where noise mechanisms span large frequency ranges.

Notable 9812HF highlights:

  • VHF bandwidth: Brings low-frequency noise measurement into 100 MHz range so designers can observe how low frequency mechanisms interact with the front-end up conversion and wideband circuits.
  • Maintains series sensitivity: Keeps low-current sensitivity and wide impedance coverage as 9812DX while extending frequency reach—so you don’t trade sensitivity for bandwidth.
  • Application fit:
    Meeting growing demands in satellite communications, automotive electronics, and other advanced applications requiring wideband noise analysis.

 

9812AC: Noise under realistic dynamic drive

Historically, most noise research and device qualification have focused exclusively on DC bias conditions. Yet, recent studies reveal that RTN under AC bias exhibits statistical properties distinct from DC-based measurements. While DC-based analysis provides a safe and conservative reliability estimate, it may unnecessarily constrain the circuit design space for advanced CMOS technologies.

To address this industry gap, Primarius launched the commercial grade 9812AC test system in 2023. The 9812AC enables designers to measure noise under dynamic operating conditions, delivering a comprehensive understanding of device behavior. This insight is crucial for making smarter design and verification trade-offs.

Noise data from 9812AC: behaviors not observable under DC bias
M9800: Industry parallel system

To meet wafer-level production demands for higher throughput and lower cost, M9800 system becomes a preferred choice for large-scale testing. Compared with conventional solutions, the M9800 increases overall test efficiency by 2-4×, accelerating process development for advanced technology nodes.

M9800 system
9812 & FS-Pro: Integration to speed up noise measurement

FS-Pro, Primarius’ all-in-one semiconductor parameter analyzer, is another flagship product in the portfolio. Compared with traditional IV meter or SMU, FS-Pro compact size and light weight (less than 8kg) makes it easier to be assembled with 9812DX as a whole system. While maintaining measurement accuracy and resolution, FS-Pro can significantly speed up DC measurement thus enable more efficient overall measurement with 9812DX.

FS-Pro delivering high accuracy and wide dynamic range for device characterization
Summary

Low-frequency noise has evolved from a niche laboratory characterization to a critical process and system-level metric in silicon development. Great low-frequency noise metrology can shorten the feedback loop between process engineers, device physicists, and circuit designers: it turns poorly quantified risk into actionable defect localization, process optimization, and realistic design margins.

The Primarius 981X family gives teams a practical, wafer-scale toolkit to measure what matters—across time, frequency and operating conditions—so they can design and qualify chips with less guesswork and more physics-backed evidence.

Also Read:

Primarius Technologies at the 2024 Design Automation Conference

Free Webinar on SPICE Simulation

Low Frequency Noise Challenges IC Designs

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A Brief History of TSMC Through 2025

A Brief History of TSMC Through 2025
by Daniel Nenni on 12-22-2025 at 10:00 am
Categories: Foundries, TSMC

About TSMC 2025

Taiwan Semiconductor Manufacturing Company, the world’s largest dedicated semiconductor foundry, has transformed from a modest startup into a global technology powerhouse. Founded on February 21, 1987, by Morris Chang, a veteran of Texas Instruments, TSMC pioneered the “pure-play” foundry model. This innovative approach separated chip design from manufacturing, allowing fabless companies to outsource production without competing directly with integrated device manufacturers (IDMs).

Historically, IDMs dominated the industry before the 1980s rise of specialization. Companies like Intel pioneered this model, optimizing processes for proprietary designs. Major IDMs today include Intel, Samsung Electronics, Texas Instruments, Infineon, STMicroelectronics, and Renesas.

Chang, recruited by Taiwan’s government to head the Industrial Technology Research Institute (ITRI), envisioned TSMC as a neutral partner. Initial capital came from the Taiwanese government (48%), Philips (28%, with technology transfer), and private investors. Located in Hsinchu Science Park, TSMC’s early focus was on mature processes like 1-micron CMOS, serving fabless startups.

The 1990s brought rapid growth. TSMC went public on the Taiwan Stock Exchange in 1994 and listed ADRs on the NYSE in 1997, the first Taiwanese company to do so. Technological milestones included 0.5-micron in 1994, 0.35-micron copper interconnects, and overseas ventures like WaferTech in the U.S. (1996). Despite challenges like the 1997 Asian financial crisis and 1999 earthquake, revenue soared, reaching over 50% foundry market share by 2000.

Entering the 2000s, TSMC advanced to 0.13-micron (2002) and 90nm (2004), powering the PC and mobile booms. The Open Innovation Platform (OIP) launched in 2008 fostered ecosystem partnerships. Leadership saw Chang retire briefly (2005-2009) before returning amid the global financial crisis. By 2010, revenue hit $13.9 billion, with nodes like 28nm ramping.

The 2010s marked dominance in advanced nodes. Co-CEOs Mark Liu and C.C. Wei took over in 2013, with Chang as chairman until 2018. Breakthroughs included 16nm FinFET (2015), 10nm (2017), 7nm with EUV (2019), and capturing Apple’s A-series chips from Samsung. Revenue reached $45 billion by 2020, market share ~55%. Geopolitical tensions emerged, including U.S. sanctions halting Huawei shipments.

The 2020s accelerated amid COVID shortages and AI surge. 5nm (2020), 4nm (2021), and 3nm (2022) debuted, powering Apple’s M-series and Nvidia’s GPUs. In 2025, 2nm (N2) entered mass production late in the year, offering 10-15% speed gains or 25-30% power savings over 3nm, using gate-all-around transistors. A16 (1.6nm) is slated for 2026/2027 with backside power delivery.

Global expansion diversified risks. Arizona’s Fab 21 began N4 production in Q4 2024, with yields matching Taiwan. By 2025, investment swelled to $165 billion for six fabs, two packaging sites, and R&D—third fab groundbreaking in April for N2/A16. Japan’s JASM (Kumamoto) started mature nodes in 2024, expanding to advanced. Germany’s ESMC (Dresden) progresses for automotive/specialty.

Financially, TSMC is thriving on AI demand. Q3 2025 revenue grew 30% YoY, with 72% foundry share. TTM revenue ~$88 billion, market cap ~$1.5 trillion. Advanced nodes (<7nm) drive ~74% wafer revenue.

Bottom Line: TSMC’s “trusted foundry” status stems from IP protection, neutrality, and innovation. From 1987’s vision to 2025’s AI linchpin, it powers global tech while navigating geopolitics. With C.C. Wei as CEO, TSMC targets net-zero by 2050 and continued leadership in the angstrom era.

Also Read:

Cerebras AI Inference Wins Demo of the Year Award at TSMC North America Technology Symposium

TSMC Kumamoto: Pioneering Japan’s Semiconductor Revival

TSMC’s Customized Technical Documentation Platform Enhances Customer Experience

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Quantum Advantage is About the Algorithm, not the Computer

Quantum Advantage is About the Algorithm, not the Computer
by Bernard Murphy on 12-22-2025 at 6:00 am
Categories: Quantum Computing
3 Comments

Conductor orchestrating waves inside a quantum computer

Of course there is a minimum requirement for the computer: enough qubits, fault-tolerant computing, support for hundreds of millions or more computations before a reset, that sort of thing. We’re still on that journey but even after we reach this goal it is important to have a sense of what delivers advantage since the computer itself simply enables quantum calculations. My research suggests a foundational principle to current algorithms, allowing for a range of high value operations though it is unclear to me how these would generalize more broadly. This is my brief attempt to summarize how quantum computing benefits are determined by algorithms, and what these algorithms must look like, at least in the near future.

What do we mean by advantage?

In the geeky world of computational complexity, there is very clear separation in performance between two main classes of algorithm: those which have polynomial complexity, running in times which grow roughly by some fixed power of the problem size, and those which have exponential complexity, running in times growing by some number raised to the power of the problem size. Algorithms which scale polynomially are practical in principle on classical computers, problems which scale exponentially are not. (I have over-simplified, but this is good enough for my argument.)

If quantum algorithms can demonstrate a polynomial advantage over classical computers that is of course good, though not necessarily unicorn-exciting for investors or customers. Grover’s algorithm, searching for some specified type of an element in an unsorted list, is of this type, showing a quadratic advantage over classical algorithms. Grover has the advantage that the limit on best performance for a classical algorithm has been formally proven, so the quantum method will always be superior. However best performance for almost all classical algorithms is merely the best we have discovered so far. As has been embarrassingly demonstrated on several occasions when claims of advantage have been upstaged by announcements of new classical algorithms with comparable performance.

(In fairness a polynomial advantage could signal a unicorn if the polynomial difference with classical alternatives is big enough.)

I’m sure there are more Grover algorithms waiting to be discovered which can demonstrate true polynomial superiority. But given the difficulty in proving upper limits for classical polynomial complexity algorithms and high expectations for quantum advantage, another way to go is to focus on beating classical algorithms with proven exponential complexity. There are already some examples in this class including Shor’s algorithm, so it’s worth digging into what makes these algorithms different and whether we can discern characteristics that might be extended to other problems.

Shout-out to the video tutorial series from Artur Ekert (professor of quantum physics at Oxford), from which I learned much of what I share here.

Going a bit deeper in Shor’s algorithm

The target problem is to find the factors of a large integer. An efficient solution will open up attacks on secure communications. Most encryption relies on the difficulty of factoring an integer N, the product of two very large (and unknown) primes, since complexity of this problem grows exponentially with N. Shor’s algorithm starts with classical compute setup to generate a seed value ‘a’, 2<a<N. The quantum stage leverages modular arithmetic (clock arithmetic), computing successive powers of a, mod N. When aR = 1 mod N for some power R, the calculation can stop and R appears as the output value of the quantum stage. Classical takes over again to reconstruct a divisor of N from R. The complexity of this algorithm is order of (logN)3, vastly faster that best-known classical methods.

The core principle behind this method is what I now see as an elaborate quantum interference experiment. Start with a list of qubits initialized to zero, run these through a QFT (Quantum Fourier Transform) to initialize for interference, then run through a phase gate which will modify phases between these qubits. Finally run through an inverse QFT to complete the interference. A function to determine phase gate operation sits outside this flow (though still within the quantum algorithm). This function computes successive aRmodN values through which it informs, in a very quantum-like way, phase gating in the interference flow.

Simon’s algorithm, a precursor to Shor, follows a similar if simpler pattern.

Quantum application to linear equation analysis

Linear equation problems come up everywhere in science, engineering, even business applications. The HHL algorithm can provide expectation values for x in the matrix equation Ax=b, under certain constraints. Such equations are classically soluble in low polynomial time in matrix size, even linear time in some cases, but the HHL method solves in polynomial of log (polylog) of the matrix size, so qualifies as an exponential speedup. It may also be significantly better than the classical method in space complexity.

The essential principle behind the method looks to me like Shor, except that interference starts with quantum phase estimation (QPE) (rather than QFT) and ends with inverse QPE. The phase gate in between these QPE gates translates matrix entries into phase values and is of course unique to this algorithm.

Whether or not HHL will prove to have commercial value I don’t know. Even Shor, while very well founded, has only been demonstrated on toy examples. Production value waits on sufficiently powerful and fault tolerant quantum computers to test production readiness.

Takeaway

There may be other possible quantum algorithm architectures, but what is more quantum than interference? The basic algorithm structure prepares superpositions/ entanglement of qubit states (through operators such as Hadamard, QFT, QPE, …), then applies phase gating which will control interference. It then realizes the interference through an inverse of the opening transform, delivering measured qubit output as an integer which may be the desired result or can be fed into further classical computation to generate the result.

This interference is the heart of any exponential advantage that can be realized by a quantum algorithm. All qubits in this path are evaluated simultaneously, a feat that a classical computer cannot hope to match. Not even massively parallel classical computers, since strong coupling between  qubits undermines any parallelism speedup.

Exploiting this advantage in other algorithms will require new kinds of ingenuity. It will be fascinating to see how these evolve!

Also Read:

Quantum Computing Technologies and Challenges

Quantum Computing Algorithms and Applications

An Insight into Building Quantum Computers

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CEO Interview with Gopi Sirineni of Axiado

CEO Interview with Gopi Sirineni of Axiado
by Daniel Nenni on 12-21-2025 at 12:00 pm
Categories: AI, CEO Interviews

Gopi Sirineni Axiado

Gopi Sirineni is a Silicon Valley veteran with four startups and over 25 years of experience in the semiconductor, software and systems industries. As a senior executive, he has demonstrated exceptional skills in building highly efficient, cost-effective organizations, managing them in rapidly changing environments, and bringing industry-changing technologies to market.

Tell us about your company?

Axiado is a semiconductor company redefining the way modern platforms are secured and managed. We develop hardware-anchored security and control solutions that are designed specifically for the demands of today’s AI-driven infrastructure. Our mission is to stop cyberattacks at their earliest point: before they impact systems. By delivering platform security that begins at the silicon level, threats are identified instantly with our technology, platform reliability is strengthened, and organizations gain a scalable, future-proof foundation for secure compute.

What problems are you solving?

For years, the industry has depended almost entirely on software-only security at the port of entry. These tools work hard to filter threats, but once malware slips through, there is nothing left to stop an attack in progress. This gap leaves high-value infrastructure dangerously exposed. Axiado closes that gap with a hardware-based security architecture. Our Trusted Control/Compute Unit (TCU) Sits alongside the system hardware as a persistent, intelligent last line of defense. It collaborates with existing software solutions while independently detecting threats they may overlook. Inside the TCU, autonomous AI agents continuously analyze behavior against known attack patterns, enabling real-time detection before damage occurs. No other company currently offers AI-driven cybersecurity integrated directly into hardware in this way.

What application areas are your strongest?

Our strength lies in combining platform management, platform security, and hardware-resident AI. Some core focus areas include platform security and management control, data-center-grade infrastructure, especially AI infrastructure, and hardware-anchored AI agents that continuously monitor system behavior. In addition, we are in the process of strengthening our Dynamic Thermal Management (DTM) and Dynamic Voltage and Frequency Scaling (DVFS), which is driven by customized AI models. Because our AI agents operate beside the hardware, they can continuously learn normal behavior patterns, identify anomalies instantly, and act autonomously. Beyond security, these same agents improve system efficiency by reducing power consumption and optimizing thermal and performance characteristics in real time.

What keeps your customers up at night?

CISOs and infrastructure leaders worry most about zero-day threats, which are attacks that slip past software defenses and act invisibly until it is too late. Today’s data centers rely heavily on software-based port-of-entry tools that are unable to see what happens once malware bypasses them. Our customers want a trusted, proactive way to predict, detect, and stop these attacks before they unfold. Axiado’s hardware-level AI learning provides exactly that: we monitor systems continuously, learn their patterns, flag deviations instantly, and identify active attacks in real time. Today, we are the only solution in the market capable of detecting attacks as they are happening at the hardware layer.

What does the competitive landscape look like and how do you differentiate?

Axiado does not have any direct competitors building a unified hardware security and platform management architecture. Legacy solutions are currently fragmented, with one piece for management, another partial add-on for boot-time security, and none built with holistic AI-driven protection in mind. Axiado’s solution is different because it is architected from the ground up with security baked in, not bolted on. We have reimagined platform control, efficiency, and end-to-end protection to work together as a single silicon-anchored system. This integration, coupled with hardware-resident AI agents, sets us apart from any legacy or discrete offerings on the market.

What new features/technology are you working on?

We are expanding our autonomous AI agent framework, enabling even more intelligent detection, efficiency tuning, and infrastructure automations. Some of these new capabilities include various advanced AI agents, enhanced Dynamic Voltage and Frequency Scaling (DVFS, next-generation Dynamic Thermal Management (DTM), and continued growth of our hardware-anchored AI compute environment. These innovations strengthen both the security posture and operational efficiency of modern compute infrastructure.

How do customers normally engage with your company?

Customers typically reach us through our website, direct outreach from our sales team, and in-person discussions at industry events. We actively participate in major conferences and trade shows, such as SC25, AI Infra Summit, and OCP Global, where we have seen strong engagement from enterprises, hyperscalers and ecosystem partners. From there, we work closely with customers to integrate our hardware, software stack, and APIs into their existing platforms.

Also Read:

CEO Interview with Masha Petrova of Nullspace

CEO Interview with Eelko Brinkhoff of PhotonDelta

CEO Interview with Pere Llimós Muntal of Skycore Semiconductors

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Google’s Road Trip to RISC-V at Warehouse Scale: Insights from Google’s Martin Dixon

Google’s Road Trip to RISC-V at Warehouse Scale: Insights from Google’s Martin Dixon
by Daniel Nenni on 12-21-2025 at 10:00 am
Categories: Events, IP, RISC-V

Google RISC V in Datacenter 2025

In an engaging presentation at a recent RISC-V summit, Martin Dixon, Google’s Director of Data Center Performance Engineering, took the audience on a metaphorical “road trip” to explore the company’s vision for integrating RISC-V into its massive warehouse-scale computing infrastructure. Drawing parallels from Google’s successful transition to ARM-based servers, Dixon outlined the opportunities, challenges, and necessary ingredients for bringing RISC-V to data center scale.

Google’s journey with heterogeneous computing began with its roots in commodity x86 platforms, celebrating its 27th birthday amid evolving needs. In the mid-2010s, the company began experimenting with ARM architectures, following the 2014 ARM server specification. This led to the 2022 launch of Tau T2A ARM instances and, more recently, the custom Axion ARM-based processors. Today, Google’s data centers already mix x86, ARM, and emerging architectures, including early RISC-V components. Dixon emphasized that heterogeneity and specialization are essential to overcoming the slowdown in Moore’s Law, enabling greater efficiency and performance at scale.

RISC-V’s openness and customization potential make it exciting, but Dixon cautioned it’s a “double-edged sword” without standards. He highlighted the need for baselines like the RVA23 profile and an upcoming RISC-V server platform specification to ensure compatibility for warehouse-scale deployment.

Using the road trip analogy, Dixon outlined key “ingredients” for success:
  • A roadmap — Standardized specifications with mandatory features like branch recording (similar to Intel’s LBR or ARM’s BRBE), side-channel-hardened crypto, and MMU support for security.
  • A cool car — High-performance server-class SoCs with at least 64 cores and support for 4GB+ memory per core, prioritizing performance, reliability, and maintainability.
  • Beyoncé — A humorous nod to Google’s internal “Beyoncé Rule” (from Beyoncé’s “Single Ladies”: “If you liked it, then you shoulda put a test on it”). Dixon stressed that critical functionality must have comprehensive tests to ease multi-architecture porting.
  • Friends — Strong community collaboration for a robust software ecosystem that “compiles and runs out of the box.”

Reflecting on lessons from porting to ARM, Dixon shared that Google’s top workloads (including YouTube, Spanner, BigQuery) represent nearly half its compute. Porting isn’t just about big services—schedulers require a mix of large and small jobs for efficient packing. Google ported over 30,000 packages via central efforts, automation, and AI-generated changes, enabling self-service for the long tail of workloads.

Developers’ fears about toolchain breakage proved unfounded; issues were mostly “boring” like config files, build paths, and flaky tests. Rare potholes included floating-point precision differences (resolved by standardizing to float128) and minimal memory ordering bugs. Overall, the transition was smoother than expected.

Looking ahead, Google is collaborating via RISC-V International on standards like QoS and RVA23, and as a founding RISE member, accelerating upstream work on Linux and LLVM. To “autopilot” the process, Google applied its Gemini AI model to 40,000 ARM porting edits, categorizing them to automate future changes. An AI agent now handles safe, gradual rollouts, often unnoticed by teams.

For RISC-V, Dixon called for ratifying server specs, delivering capable SoCs, expanding test coverage, and embracing AI. Google, with RISE and RISC-V International, is funding academics with Gemini credits to advance AI-driven porting.

Dixon closed optimistically, quoting Jack Kerouac: let’s “lean forward to the next venture” with RISC-V at warehouse scale. His talk underscores Google’s commitment to open architectures, positioning RISC-V as a key pillar in the future of hyperscale computing.

Also Read:

Bridging Embedded and Cloud Worlds: AWS Solutions for RISC-V Development

The RISC-V Revolution: Insights from the 2025 Summits and Andes Technology’s Pivotal Role

Podcast EP309: The State of RISC-V and the Upcoming RISC-V Summit with Andrea Gallo

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Bridging Embedded and Cloud Worlds: AWS Solutions for RISC-V Development

Bridging Embedded and Cloud Worlds: AWS Solutions for RISC-V Development
by Daniel Nenni on 12-21-2025 at 6:00 am
Categories: Events, IP, RISC-V

AWS RISC V Summit 2025 SemiWiki

In a compelling keynote at the RISC-V Summit North America 2025, Jeremy Dahan from AWS explored the challenges of embedded systems development and how cloud technologies can bridge the gap between local hardware tinkering and scalable, shareable environments. Drawing from his experience as an engineer, Dahan highlighted the desire for desktop-accessible hardware for rapid prototyping, contrasted with the difficulties of sharing setups across teams, suppliers, and global collaborators. The cloud’s infinite compute and easy accessibility offer a solution, and AWS is positioned to combine these worlds for RISC-V developers.

Dahan framed virtualization as a key enabler, but one requiring a balance between time, cost, and performance accuracy. Over-investing in high-fidelity models can delay projects, while insufficient accuracy hinders progress. AWS addresses this through curated tools, partner solutions, and guidance to accelerate hardware-software co-development from initial models to real ECUs.

A standout example is the “virtual engine experience,” a cloud-based portal providing unified access to development tools. Users log in with credentials tied to Git repositories, accessing a consistent environment with pre-installed, RISC-V-supported tools from partners. This eliminates “it works on my machine” issues, speeds onboarding (from weeks to one day), and ensures version uniformity across teams, suppliers, and customers.

Dahan showcased partnerships, highlighting a recent two-hour workshop with ChipInvent demonstrating cloud-based EDA tools for rapid RISC-V design creation, something impractical with traditional setups.

Delving deeper into virtualization levels (referencing Synopsys slides), Dahan explained the spectrum from abstract models (fast but low accuracy) to real hardware (accurate but hard to scale). Engineers prefer the right side for confidence, but cloud shifts this leftward without sacrificing too much fidelity. Notably, 90% of Hardware-in-the-Loop (HIL) testing can shift to Software-in-the-Loop (SIL), avoiding procurement delays, power/cooling needs, and maintenance of physical farms.

For RISC-V, where native execution isn’t directly available like on ARM Graviton instances, AWS leverages FPGA acceleration. EC2 F1/F2 instances (with AMD Xilinx UltraScale+ FPGAs) provide scalable access to FPGA-based prototypes, marrying desktop board benefits with cloud sharing.

Developers use pre-packaged tools like Vitis and OpenCL, integrate custom IP, and generate Amazon FPGA Images (AFIs) snapshottable, shareable, and marketplace-listable. IP remains protected, enabling monetization (free, paid, or BYOL). Smaller RISC-V IP providers gain broader reach without field engineers troubleshooting physical boards. A workshop used an RV35I core this way for quick starts.

For remaining real-hardware needs, AWS Outposts bring data-center servers on-premises, connectable to custom boards (e.g., Infinitrial or user-specific for IO testing). Secure remote access allows suppliers/customers to debug without travel, scaling to multiple boards.

Hybrid setups connect on-prem HIL farms to cloud via Direct Connect for low-latency, with EKS Hybrid Nodes orchestrating workloads across emulation, FPGA, and physical hardware under one control plane.

Dahan concluded that AWS reconciles embedded and cloud paradigms, letting developers focus on IP while managed services handle infrastructure. Calls to action included workshops for FPGA development, Marketplace listing guidance, and EDA scaling solutions. AWS hosts meetups in Santa Clara for hands-on tinkering and demos.

Bottom line: This talk underscores AWS’s commitment to RISC-V, making high-fidelity, collaborative development accessible and scalable—transform local prototypes into globally shareable assets.

Also Read:

The RISC-V Revolution: Insights from the 2025 Summits and Andes Technology’s Pivotal Role

Podcast EP309: The State of RISC-V and the Upcoming RISC-V Summit with Andrea Gallo

Yuning Liang’s Painstaking Push to Make the RISC-V PC a Reality

Podcast EP323: How to Address the Challenges of 3DIC Design with John Ferguson

Podcast EP323: How to Address the Challenges of 3DIC Design with John Ferguson
by Daniel Nenni on 12-19-2025 at 10:00 am

Daniel is joined by John Ferguson, senior director of product management for the Calibre products in the 3DIC space at Siemens EDA. He manages the vision and product offerings in the Calibre domain for 3DIC design solutions.

Dan explores the challenges of 3DIC and chiplet-based design with John, who describes the broad range of tools Siemens offers to address these challenges. John focuses on thermal, power and mechanical stress as three key aspects of advanced designs that must be carefully analyzed and optimized early. He explains how Calibre’s knowledge of the design forms the foundation for much of this work, with the addition of technologies such as multiphysics analysis to expand the scope.

John describes many real word scenarios for 3DIC design that require additional focus and the consequences of not getting it right. He also comments on the benefits of AI for advanced design flows.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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How vHelm Delivers an Optimized Clock Network

How vHelm Delivers an Optimized Clock Network
by Mike Gianfagna on 12-19-2025 at 6:00 am
Categories: ClockEdge, EDA

How vHelm Delivers an Optimized Clock Network

In a prior post, I discussed how the clock is no longer just another signal at advanced nodes. Indeed, it is the most critical network on the chip. An optimized clock network can be the margin of victory for your next design. But extracting these benefits is challenging. The clock network is quite sensitive, and optimization can come down to finding a few picoseconds buried deep inside the design. ClockEdge has built a pioneering suite of tools to address these challenges.

I discussed the four elements of the ClockEdge Veridian platform in the prior post mentioned above. Timing, power, aging and jitter are all part of the solution. But integrating the massive information associated with these elements of the design to find the right balance is another hurdle. This is where the command center for the Veridian platform takes over, providing the required integrated perspective. Let’s examine how vHelm delivers an optimized clock network.

Unlocking Insights with a Shift-Left Strategy

Thanks to SPICE-accurate visibility and fast virtual ECO loops, clock optimization can now be done early with a shift-left approach. Moving clock optimization from a late-stage emergency to an early-stage process that improves PPA across the entire design can produce a substantial positive impact for any design team.

The full-network SPICE accuracy delivered by Veridian reveals timing distortion, duty cycle imbalance, jitter sensitivity, and aging drift that corner-based STA approaches fail to capture. There are many positive impacts as a result. Here are a few:

    • Early visibility into dynamic timing behavior. SPICE-accurate timing analysis exposes real rail-to-rail behavior, including degraded swing, coupling-driven distortion, and asymmetric PVT effects that STA routinely smooths over.
    • Jitter understanding, when it matters most. Clock jitter at advanced nodes is dominated by power delivery network (PDN) noise. Gate switching currents, bump-level voltage droop, and multi-domain noise profiles create sub-picosecond accurate jitter that only transient simulation can reveal.
    • Early power optimization. Clock networks consume a large share of total power. With a virtual ECO, designers can tune buffers, topologies, and sizing while there is still room to make changes without impacting the schedule.
    • Lower sign-off risk. Once early optimization is in place, sign-off stops being a hunt for surprises. Design teams arrive at the final stage with fewer iterations, tighter margins, and higher confidence.

vHelm Puts it All Together

What makes vHelm different? Here are a few examples:

Sign-off grade accuracy, available early: The Veridian platform traces the full clock network, generates a SPICE netlist, and runs transient simulation fast with patented technology that can scale to millions of gates..

Virtual ECO enables rapid iteration: Change a constraint, resize a buffer, or adjust topology and see the SPICE-accurate impact across the clock network. This replaces the slow trial-and-error cycle of late-stage ECOs with a tight optimization loop that actually fits the schedule.

One interface. One flow. One source of truth.

vHelm consolidates:

  • Timing visualization
  • Jitter margins
  • Power consumption
  • Rail-to-rail behavior
  • Aging impact

No patchwork of point tools or stitched-together STA, simulators, and debug utilities.. It is a unified flow by design.

Designed for early leverage, not late rescue: The goal is not just catching issues. It is reshaping architecture, buffering strategy, and margin allocation at a time when these choices still influence PPA.

And here are some reasons why early optimization directly improves sign-off:

Fewer surprises: Teams that shift left find that sign-off paths often validate changes, not expose them.

Tighter PPA: With accurate SPICE insights, designers remove unnecessary guard-bands and reclaim performance or power margin without increasing risk. 

Higher reliability over product lifetime: Aging-aware analysis reveals long-term drift in edge behavior. Fixing these issues early prevents latent field failures and improves yield.

Measurable schedule predictability: Virtual ECO replaces uncertainty with controlled iteration.

I have just touched on a few of the many capabilities vHelm offers design teams for early clock network optimization. Below is a screen shot of the interface, illustrating the many parameters on the left that vHelm is tracking and some of the analysis that can be applied to these parameters on the right to find the right path to an optimal clock network.

To Learn More

What is becoming clear is this: advanced-node clocks cannot be modeled accurately enough with abstractions alone. Teams can either continue treating accuracy as something addressed at the end or use it as an opportunity at the start of the design.

vHelm exists for teams who choose the second path. If you are responsible for clocking in an advanced SoC, vHelm can help to answer one question: how much margin am I leaving on the table? You can learn more about the ClockEdge Veridian platform and the impact of vHelm here.  And that’s how vHelm delivers an optimized clock network.

Also Read:

ClockEdge Delivers Precision, Visibility and Control for Advanced Node Clock Networks

CISCO ASIC Success with Synopsys SLM IPs

RISC-V: Powering the Era of Intelligent General Computing

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CEO Interview with Masha Petrova of Nullspace

CEO Interview with Masha Petrova of Nullspace
by Daniel Nenni on 12-18-2025 at 2:00 pm
Categories: CEO Interviews

Masha Headshot

Dr. Masha Petrova is CEO and co-founder of Nullspace Inc., a venture-backed company developing next-generation electromagnetic simulation software for RF and quantum computing applications. She brings 25 years of engineering software experience from executive roles at MSC Software, Altium, and Ansys, and several computational software start-ups. Dr. Petrova holds a Ph.D. in Aerospace Engineering from UC San Diego and a B.S. in Mechanical Engineering from the University of Delaware.

What is Nullspace?

Nullspace is rebuilding electromagnetic simulation from the ground up to handle the scale and complexity of modern RF systems. Nullspace makes software that helps engineers design and validate these systems, from satellite constellations and advanced platforms to 5G infrastructure and quantum computing hardware.

The core challenge Nullspace is addressing is that the simulation tools engineers have relied on for decades are 40+ years old and were created before parallel computing architecture even existed. These legacy tools were not built for modern computing.

As RF systems have grown exponentially more complex with dozens of antennas, phased array systems, or massive MIMO configurations, these legacy tools often crash or take weeks, or even months, to run when used on real-world applications that require highly-accurate physics simulations.

Nullspace has built a solver architecture to take full advantage of parallel computing, along with both CPU and GPU acceleration combined with a proprietary compression algorithm, delivering up to 25x faster performance for simulations that typically overwhelm traditional tools.

Nullspace was incubated inside a U.S. defense contractor for over a decade, where the technology was validated on mission-critical DoD products. The company spun out three years ago to bring this defense-grade reliability to commercial markets. The Python API architecture also uniquely positions Nullspace for AI-driven optimization workflows, not AI replacing physics, but AI automating the iterative design process.

What problems is Nullspace solving?

The fundamental problem is that legacy electromagnetic solvers can’t handle the scale and complexity of modern RF systems. Engineers consistently tell Nullspace their simulations run for two weeks, then crash before delivering results. When facing a satellite launch deadline or program milestone, these failures create significant bottlenecks that put entire projects at risk.

Legacy tools force engineers to oversimplify their designs just to get something that runs. For example, simulating entire RF systems like a complex network of antennas on a spacecraft, or a phased array installed on a platform, is beyond the capability of these tools. Engineers have to break up these problems into pieces, simulate each separately, and then integrate the results, which creates loss of accuracy and increases design risk.

Nullspace solves this by enabling engineers to simulate full RF system designs accurately and significantly faster. Nullspace employs a full-fidelity 3D physics solver based on the Method of Moments that combines CPU and GPU acceleration with a proprietary compression algorithm to deliver fast results without loss of accuracy. This means faster iteration, fewer prototype spins, and the ability to validate designs that were previously impossible to simulate.

Where does Nullspace excel?

Nullspace excels in three key areas that share a common thread: complex electromagnetic and electrostatic challenges in advanced, next-generation systems that push the boundaries of traditional simulation.

Defense, aerospace, and communications industries: This is Nullspace’s area of expertise, including antenna placement and co-site analysis, radar cross-section analysis, and complex phased-array design. Nullspace software can handle electrically large problems that overwhelm legacy tools, simulating entire RF systems of a spacecraft or aircraft with all antennas interacting, a capability that sets the company apart.

Wireless infrastructure: 5G systems, phased array antennas, and next-generation communication networks. As companies pack more antennas into smaller spaces with more frequency bands, electromagnetic interference becomes critical. While legacy tools take weeks for these simulations, Nullspace can deliver results in hours or days.

Quantum computing hardware: Nullspace also develops the world’s only commercial electrostatic solver for extremely large-scale, rapid, and accurate design and analysis of structures that support modern quantum computers and particle accelerators. Leading quantum computing companies rely on Nullspace because it’s the only commercial solver capable of handling large-scale ion traps. Nullspace technology has powered multiple quantum computing world records.

What challenges were engineers facing before Nullspace?

Three challenges consistently come up in conversations with customers.

First is simulation reliability on tight deadlines. When tools fail after extended runtime with a critical deliverable approaching, teams face serious project risks and need dependable, fast solutions they can count on.

Second is the growing complexity of modern RF systems. Today’s satellites carry dozens of antennas, creating electromagnetic challenges that legacy tools simply cannot model effectively, if at all. The problems are scaling faster than the tools, and RF engineering talent is scarce enough that valuable engineers shouldn’t spend weeks waiting for simulations to complete. When design iterations take days or weeks, innovation slows dramatically.

Third is the productivity constraint this creates. Engineers need tools that can keep pace with the complexity of the systems they’re designing, not tools that force them to compromise or wait.

What makes Nullspace unique?

Nullspace’s differentiation is architectural. While others modify decades-old code, Nullspace rebuilt from scratch for modern parallel computing, representing a fundamental advancement in electromagnetic simulation capability.

Performance leads the differentiation: over 25x faster, Nullspace software can solve problems that crash competitor tools entirely. Beyond speed, the Python API foundation enables AI-guided optimization and automation, allowing engineers to set up iterative design loops that run automatically, a capability that’s difficult or impossible with legacy tools.

Nullspace runs efficiently on both CPUs and GPUs, while many other solutions require one or the other, or force costly per GPU or CPU pricing on customers.

Finally, Nullspace’s decade-plus validation on real products that were designed and delivered to DoD provides proven reliability. When organizations need mission-critical accuracy, that track record speaks volumes.

How do customers normally engage with Nullspace?

Engagement typically starts when traditional tools fail. An engineering team hits a wall, whether it’s a simulation that won’t converge, a model too large to run, or deadlines that current tools can’t meet. They reach out, often through word-of-mouth in the RF engineering community.

Nullspace runs a technology transfer process where the team takes the customer’s actual problem, sets it up in Nullspace, and demonstrates the performance gain. When they see their two-week simulation complete in ten hours with equal or better accuracy, the value becomes clear.

For defense and aerospace customers, security and compliance are critical. Nullspace’s defense background means the company understands ITAR requirements, can operate in air-gapped environments, and has experience with the procurement process. Nullspace provides extensive hands-on support during onboarding, working closely with customers to ensure they can tackle problems no other tool can handle.

Also Read:

CEO Interview with Eelko Brinkhoff of PhotonDelta

CEO Interview with Haber Ma of ADCERAX

CEO Interview with Pere Llimós Muntal of Skycore Semiconductors

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Cost, Cycle Time, and Carbon aware TCAD Development of new Technologies

Cost, Cycle Time, and Carbon aware TCAD Development of new Technologies
by Daniel Nenni on 12-18-2025 at 10:00 am
Categories: Semiconductor Services, Synopsys, TechInsights

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Our good friend Scotten Jones wrote a paper on a product that has been in joint development with Synopsys and is now available. Scott is currently President Semiconductor Manufacturing Economics and Senior Fellow at TechInsights. Scott and I have discussed this product many times and I feel it is ground breaking technology for semiconductor design. Scott briefed me on it at IEDM and sent me the white paper. Here is my take on it:

The semiconductor industry is shifting from traditional Power, Performance, and Area (PPA) metrics to a broader PPACtE framework, incorporating Cost (C), Cycle Time (t), and Environmental impact via Carbon Equivalents (E). Synopsys’ DTCO suite has long facilitated TCAD-based PPA optimization. TechInsights’ Cost Explorer plug-in integrates into Synopsys Sentaurus Process Explorer, enabling full PPACtE analysis. This tool has been demonstrated by Tokyo Electron to assess CFET architectures, revealing a 15.3% cost premium for sequential over monolithic designs. With node development costs exceeding billions, Cost Explorer promises substantial savings in R&D and manufacturing by simulating CtE alongside PPA before physical prototyping.

Introduction

For decades, semiconductor advancements focused on PPA improvements, as seen in TSMC’s 3nm node offering 25-30% power reduction, 10-15% performance boost, and 70% density gain over 5nm. However, escalating costs, extended cycle times, and environmental concerns—highlighted by industry leaders like TSMC and Applied Materials—demand inclusion of CtE. With 3nm/2nm R&D nearing $10 billion per node, early simulation is crucial. DTCO co-optimizes design and process, but traditional tools like Synopsys’ suite lack CtE modeling. TechInsights’ Cost Explorer addresses this, enhancing Synopsys’ ecosystem for comprehensive PPACtE optimization, as proven in CFET studies.

New Technology Development

Semiconductor node development spans two phases: initial simulation-driven optimization of devices, models, and flows to meet PPA, followed by test chip fabrication and PDK refinement. TCAD minimizes costly wafers by iterating assumptions virtually. Synopsys DTCO excels here but omits CtE, limiting holistic optimization.

Synopsys DTCO Solution

Synopsys’ DTCO flow integrates tools like Proteus for patterning, QuantumATK for materials, Sentaurus TCAD for architectures, and Fusion Technology for design evaluation. Benefits include accurate pre-wafer simulations, realistic context feedback, and variation-aware modeling for reliable PPA. Collaboration with TechInsights adds CtE metrics, expanding design evaluation.

Synopsys Sentaurus Process Explorer

This tool enables interactive 3D visualization, process debugging, and metrology for advanced nodes like FinFETs and GAA. Features support yield analysis, anomaly detection, and TCAD integration, reducing cycle time and enhancing collaboration. It accelerates DTCO by identifying issues early, maximizing simulation ROI.

CtE Modeling Requirements

CtE estimation demands detailed fab and process modeling. Cost varies by fab capacity, location, and steps, calculated via equipment, labor, materials, and facilities. Cycle time uses ideal estimates (step-by-step processing) multiplied by an  Xideal factor for realism. Carbon footprint tracks material usage, emissions, and abatement. Cost Explorer computes these from process flows.

How Cost Explorer Works

Users define fab parameters (country, capacity, node) and build flows by selecting from 93 equipment types, parameterizing steps (e.g., film thickness). Pre-populated tables handle configurations, throughputs, costs, and materials. Algorithms compute equipment needs, costs (wafers, labor, depreciation), ideal cycle time, and carbon via GWP factors. Outputs include per-step breakdowns, as in Samsung 3nm GAA analysis.

Integration with Sentaurus Process Explorer

In Process Explorer, users assign equipment to steps, triggering Cost Explorer to auto-populate and calculate CtE. Results display per step and total, enabling iterative PPACtE refinement within the DTCO flow.

Use Cases

Tokyo Electron’s 2023 VLSI study used an early Cost Explorer to compare CFETs: monolithic (better performance, area) vs. sequential (3% lower performance, 6% higher power, 15.3% higher cost). Future work includes 2nm nanosheet evaluations with/without backside power, incorporating tE.

Bottom line: Cost Explorer’s integration into Synopsys DTCO empowers pre-wafer PPACtE optimization, slashing development costs and yielding efficient, sustainable processes. In a billion-dollar R&D landscape, this yields significant long-term savings in manufacturing, time, and emissions.

Download Paper Here

Also Read:

How PCIe Multistream Architecture Enables AI Connectivity at 64 GT/s and 128 GT/s

WEBINAR: How PCIe Multistream Architecture is Enabling AI Connectivity

Lessons from the DeepChip Wars: What a Decade-old Debate Teaches Us About Tech Evolution