SemiWiki – Page 140 – The Open Forum for Semiconductor Professionals

February 14, 2023April 10, 2023

Interconnect Choices for 2.5D and 3D IC Designs

A quick Google search for “2.5D 3D IC” returns 669,000 results, so it’s a popular topic for the semiconductor industry, and there are plenty of decisions to make, like whether to use an organic substrate or silicon interposer for interconnect of heterogenous semiconductor die. Design teams using 2.5D and 3D techniques soon realize that there are many data formats to consider:

GDS – chiplet layout
LEF/DEF – Library Exchange Format, Design Exchange Format
Excel – ball map
Verilog – logic design
ODB++ – BGA package
CSV – Comma Separated Value

A recent e-book from Siemens provides some much-needed guidance on the challenges of managing the connectivity across the multiple data formats. Source data gets imported into their connectivity management tool, and then each implementation tool receives the right data for analyzing thermal, SI (Signal Integrity), PI (Power Integrity), IR drop, system-level LVS, and assembly checking.

For consistency your design team should use a single source of truth, so that when a design change is made then the full system is updated, and each implementation tool has the newest input data. The Siemen’s workflow stays in sync through the system-level LVS approach.

There’s no standard file format between package, interposer and board teams, yet by using ODB++ you can take in package and PCB data to the planning tool, allowing your team to communicate and optimize using any EDA tool. A package designer can move bumps around, and then the silicon team can review the changes using DEF files to accept them.

The largest system in package designs can have one million total pins, so your tools need to handle that capacity. Yield on a substrate depends on the accurate placement of via, via arrays and metal areas. Your substrate or interposer layout tool has to manage the interfaces properly, and make sure to get the foundry or OSAT assembly design kit for optimal results.

From the Siemens tool you have a planning cockpit to graphically and quickly create a virtual prototype of the complete 2.5/3D package assembly, aka – digital twin. This methodology makes possible System Technology Co-Optimization (STCO). Making early trade-offs between architecture and technology produce the best results for a new system, by using predictive analysis to sort through all the different design scenarios. Predictive analysis validates that the net names are consistent between the die, interposer and package, thus avoiding shorts and opens.

System Technology Co-Optimization

System LVS ensures that all design domains are DRC and LVS clean, validating connections at the package bumps, interposer and die.

Physical verification is required during many steps:

Die level DRC and LVS
Interposer
Package
All levels together

The Siemens planning tool does all of this, while keeping the system design correct from start to finish, eliminating late surprises. An equivalence check also needs to be run between the planning tool and the final design.

Using a digital twin methodology your team can now verify that the package system is correct. Early mistakes are quickly caught through verification, like “pins up, pins down”, through an overlaps check between the package, silicon and interposer. Bump locations will also be checked for consistency between package and IC teams. Checks can be run after every change or update, just to ensure that there are no surprises.

Summary

The inter-related teams of IC, package and board can now work together by using a digital twin approach, as offered by Siemens. Not many EDA vendors have the years of experience in tool flows for all three of these areas, plus you can add many of your favorite point EDA tools. Collaboration and optimization are possible for the challenges of 2.5D/3D interconnects.

Read the full 14 page e-book from Siemens.

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February 14, 2023May 5, 2023

PCIe 6.0: Challenges of Achieving 64GT/s with PAM4 in Lossy, HVM Channels

PCIe 6.0: Challenges of Achieving 64GT/s with PAM4 in Lossy, HVM Channels
by Kalar Rajendiran on 02-14-2023 at 6:00 am
Categories: EDA, IP, Synopsys

As the premier high-speed communications and system design conference, DesignCon 2023 offered deep insights from various experts on a number of technical topics. In the area of high-speed communications, PCIe has a played a crucial role over the years in supporting increasingly higher communications speed with every new revision. Revision 6.0, the latest revision of this communications interface standard enables system designers to achieve advances in the deployment of AI inference engines and co-processors in data centers. Consequently, PCIe 6.0 was a hot topic at the conference, not just for the 64GT/s speed but also for understanding the engineering challenges to reliably deliver that speed.

PCIe 6.0 poses a demanding set of chip and system design challenges on engineers. To reliably deliver the full benefits of PCIe 6.0, collaboration and cooperation are needed to standardize specifications in the areas of PCIe card, cable, connector assembly, test method, measurement and tools and PCIe PHY and controller IP. An experts panel to discuss these very topics included David Bouse from Tektronix, Rick Eads from Keysight Technologies, Steve Krooswyk from Samtec, Madhumita Sanyal from Synopsys and Timothy Wig from Intel. The panel session was moderated by Pegah Alavi from Keysight Technologies.

Pegah opened the session by highlighting the challenges introduced by multi-level signaling (MLS) when the switch was made from NRZ to PAM4 signaling to support 64GT/s. The adoption of MLS has opened up the path to continue increasing data communications speeds. By mapping more than 1 bit into a transmitted symbol, the required bandwidth/bit is reduced. But MLS introduces a lot of challenges too, which need to be overcome to achieve the speed benefit in a reliably manner.

Under MLS, the signal to noise ratio worsens, negatively impacting the performance of the channel. Consequentially, all aspects of the channel need to be paid close attention to. With that introduction, Pegah set the stage for the panelists to update the audience on their respective areas of focus to deliver a reliable PCIe 6.0 end-user solution. The following is a synthesis of the salient points from the session.

PCIe Card and Cable Form Factor Updates

Rev 6.0 of the PCIe Card Electromechanical (CEM) form factor specification is being finalized in 2023. The Rev 6.0 mechanical updates are completely redefining chassis retention on the North and East vias.

The CEM card physical form factor introduces two new power connectors at 48V to deliver 600W.

A shielded plane/south via approach has been introduced to shield the send signals from the receive signals. Without the shielding plane/south via approach, PCIe 6.0 channels would be completely broken, given known examples of inattentive card layout sabotaging even PCIe 5.0 channels.

Two PCIe cable form factors are being defined. Both these new form factors are distinct from previous PCIe cable solutions. An internal cable form factor is being defined based on the EDSFF-TA-1016 cable system targeting PCIe 5.0 and PCIe 6.0 speeds. An external cable form factor is being defined based on the industry standard CDFP. The Internal PCIe cable form factor has been characterized for a range of connectors and cables from multiple vendors, mounting styles and lengths.

Test Methods and Tools

The PCIe ecosystem is keeping PCIe 7.0 in mind as they define and develop tools and test methods for PCIe 6.0. After all, PCIe 7.0 spec (128 GT/s) is just around the corner as it is expected to arrive in the 2024-2025 time frame. The Tx, Rx and channel compliance requirements are kept in mind as the simulation, test and measurement methods are being developed to validate connectors and cables-connector assemblies. Forward Error Correction (FEC) has been introduced in PCIe 6.0, a first for the PCIe interface standard to accommodate the impact of channel loss.

PCIe v6.0 Retimer

All of the things presented above ensure that the cards, cables, connectors and assemblies are validated to support PCIe 6.0. Depending on the end market and application, a PCIe-based system will be deploying different channel topologies, leveraging the hardware listed above. Consequentially, each channel topology will bring with it, its own characteristic that would impact the channel performance.

The following chart shows four different channel topologies that are commonly found in PCIe-based systems.

From the PCIe PHY perspective, it needs to be able to optimize for all possible channel topologies. Given the Reduced Insertion Loss budget imposed by the PCIe 6.0 specification, how to ensure that the signal from the Root port will reach the destination port without losing fidelity.

The solution is the introduction of a PCIe 6.0 Retimer circuit. PCIe Retimers enable the expansion of PCIe over system boards, backplanes, cables, risers and add-in cards, irrespective of the channel topology that is deployed. A Retimer is a physical layer and protocol-aware device but software-transparent, and can reside in any place in the channel between PCIe Root-port and End-point. It fully recovers the data over any channel from the Host PCIe Root-port, extracts clock and re-transmits the clean data over another channel to the PCIe End-point device. The Retimer solution is implemented in the form of customized PHY and light controller logic for the MAC.

Summary

The panelists offered a number of tips and tricks and best practices throughout the session. When DesignCon makes the panelists’ presentation materials available on their website, it would be a good idea to download as reference materials. You may want to reach out to the panelists for more specific detailed information.

Also Read:

Optimization Tradeoffs in Power and Latency for PCIe/CXL in Datacenters

Synopsys Design Space Optimization Hits a Milestone

Webinar: Achieving Consistent RTL Power Accuracy

February 13, 2023May 5, 2023

Optimization Tradeoffs in Power and Latency for PCIe/CXL in Datacenters

Optimization Tradeoffs in Power and Latency for PCIe/CXL in Datacenters
by Daniel Nenni on 02-13-2023 at 10:00 am
Categories: Events, IP, Synopsys

PCI Express Power Bottleneck

Madhumita Sanyal, Sr. Technical Product Manager, and Gary Ruggles, Sr. Product Manager, discussed the tradeoffs between power and latency in PCIe/CXL data centers during a live SemiWiki webinar on January 26, 2023. The demands on PCIe continue to grow with the integration of multiple components and the challenge of balancing power and latency. The increasing number of lanes, multicore processors, SSD storage, GPUs, accelerators, and network switches have contributed to this growth in demand for PCIe in compute, servers, and datacenter interconnects. Gary and Madhumita provided expert insights on PCIe power states and power/latency optimization. I will cherry pick a few things that interested me.

Watch the full webinar for a more comprehensive understanding on Power, Latency for PCIe/CXL in Datacenters from Synopsys experts.

Figure 1. Compute, Server, and Data Center Interconnect Devices with Multiple Lanes Hit the Power Ceiling

Reducing Power with L1 & L2 PCIe Power States

In the early days of PCIe, the standard was primarily focused on PCs and servers, for example achieving high throughput. This early standard lacked considerations for what we would now consider green or mobile friendly. However, since the introduction of PCIe 3.0, PCI-SIG has placed a strong emphasis on supporting aggressive power savings while continuing to advance performance goals. These power savings are achieved through the implementation of a standard defined as link states. Link states range from L0 (everything on) to L3 (everything off) with intermediate states contributing various levels of power savings. Possible link states continue to be refined as the standard advances.

Madhumita explained that PCIe PHYs are the big power hogs, accounting for as much as 80% to power consumption in a fully-on (L0) state! The lower power, L1 state, now includes various sub-states, enabling the deactivation of transceivers, PLLs, and analog circuitry in the PHY. The L2 power state reflects a power-off state with only auxiliary power to support circuitry such as retention logic. L1 (and its sub-states) and L2 are the workhorses for fine-tuning power savings. PCIe 6.0 introduces the option of L0p, which allows for dynamic power down on a subset of lanes in a link while keeping the remainder fully active. This feature results in both a reduction of the number of active lanes via L0p, which lowers the bandwidth, with a simultaneous reduction in the power consumption.

With PCIe power states defined, the Synopsys experts delved deeper into the process for the host and device to determine the appropriate link state. A link in any form of sleep state will incur a latency penalty upon waking – known as exit latency – such as when transitioning to an L0 state to support communication with an SSD. To reduce the system impact of this penalty, the standard specifies a latency tolerance reporting (LTR) mechanism which informs the host of the latency tolerance of the device towards an interrupt request, ultimately guiding the negotiation process.

Using Clock-Gating to Reduce Activity

The range of power saving options in digital logic is well known. I was particularly interested in the usage of clock gating techniques to optimize energy consumption by eliminating wasted clock toggling on individual flops or banks of flops, even globally for entire blocks. Dynamic voltage and frequency scaling (DVFS) decreases power by reducing operating voltage and clock frequency on functions which can afford to run slower at times. Although DVFS can result in significant power savings, it also adds complexity to the logic. Finally, power gating allows for the shutting off both dynamic and leakage power at a block level, except perhaps for auxiliary power to support retention logic.

In addition to these options, there are other techniques such as the use of mixed VT libraries. Madhumita also expanded on board and backplane considerations in balancing performance vs. power in PCIe 6.0. Low power can be achieved with lower channel reaches. For a more comprehensive discussion on these topics, I encourage you watch the webinar.

Latency in PCIe/CXL: Waiting is the Hardest Part!

Gary Ruggles recommends utilizing optimized embedded endpoints to reduce latency. These endpoints avoid the need for the full PCIe protocol from the host, through a physical connection and again through the full PCIe protocol on the device side. For example, a NIC interface could be embedded directly in the same SoC as the host, connecting to the PCIe switch directly through a low latency interface.

Gary also expanded on using a faster clock to decrease latency, while acknowledging the obvious challenges. A faster clock may require higher voltage levels, leading to increased dynamic power consumption, and higher speed libraries increase leakage power. However, the tradeoff between clock speed and pipelining is not always a total clearcut. Despite the potential increase in power consumption, a faster clock may still result in a performance advantage if the added pipelining latency is outweighed by the reduction in functional latency. Latency considerations factor in how you plan power states in PCIe. Fine-grained power state management can reduce power usage, but it also results in increased exit latencies, which can become more consequential when managing power aggressively.

Gary’s final point in managing latency is considering the use of CXL. This protocol is built based PCIe, while also supporting the standard protocol through CXL.io. CXL’s claim to fame is support for cache coherent communication through CXL.cache and CXL.mem. These interfaces offer much lower latency than PCIe. If you have need for coherent cache/memory access, CXL could be a good option.

Takeaways

Power consumption is a major concern in datacenters. The PCIe standard makes allowance for multiple power states to take advantage of opportunities to reduce power in the PHY and in the digital logic. Taking full advantage of the possibilities requires careful tradeoffs between optimization for latency, power, and throughput, all the way from software down to the PCIe physical layer. When suitable, CXL proves to be a promising solution, offering much lower latency compared to conventional PCIe.

Naturally ,Synopsys has production IP for PCIe (all the way up to Gen 6) and for CXL (all the way to CXL 3.0).

You can watch the webinar HERE.

Also Read:

PCIe 6.0: Challenges of Achieving 64GT/s with PAM4 in Lossy, HVM Channels

How to Efficiently and Effectively Secure SoC Interfaces for Data Protection

ARC Processor Summit 2022 Your embedded edge starts here!

February 13, 2023October 6, 2023

Big plans for state-of-the-art RF and microwave EDA

Big plans for state-of-the-art RF and microwave EDA
by Don Dingee on 02-13-2023 at 6:00 am
Categories: 5G, EDA, Keysight EDA

RF front-end components are driving demand for state-of-the-art RF and microwave EDA

RF and microwave design is no longer confined to a few defense and aerospace EEs huddled in dark cubicles working with spreadsheets and primitive circuit simulators. Now, areas like 5G and automotive demand complex RF systems. Advanced RF and microwave EDA tools are taking on electromagnetic (EM), thermal, and power simulation, and everyone from systems engineering to foundry partners touch the workflow.

Quantitatively, the opportunity is drawing interest rapidly. Market analyst Yole Développement pegs CAGR for RF front-end components at 8.3% through 2026. Digital EDA companies are scrambling to incorporate RF-aware technology into their EDA mix – and finding they need many different pieces, not just point products, for a complete RF design workflow.

As a long-time leader in the RF and microwave design and test business, Keysight has proven tools and experience customers have counted on for decades. Its state-of-the-art RF/microwave EDA solutions will drive integration, openness, and scalability for anyone looking to innovate – even designers and systems engineers from digital-first backgrounds with less RF knowledge. Nilesh Kamdar, Senior Director and Portfolio Manager for RF/Microwave, Power Electronics & Device Modeling products, sat down to give us a sense of what’s coming in 2023.

On a journey together with customers to first-pass success

Kamdar sees his business and its mission with customers hinging on collaboration and trust, going back to its HP EEsof origin story four decades ago. “We’ve been #1 in RF/microwave EDA for decades because our customers trust us,” he says. “Now, it’s time to expand that trust and offer solutions that take existing customers – and new ones – into the future.” Keysight portfolio teams meet regularly with Tier 1 customers, and their list of pain points is weighty.

Time-to-market is shrinking, especially where consumer life cycles dominate,
Complexity is also growing exponentially, with more integration, advanced packaging and foundry processes, and higher expectations for user experience
Packing more into less space is causing multi-domain interactions, detuning RF performance, and putting pressure on managing heat and power consumption
Scale is now immense, with billions of devices produced from a single design
Open environments and platforms are redefining boundaries in ecosystems and workflows

Maybe it’s stating the obvious, but Kamdar says another theme for Keysight is design to verification to manufacturing. “We help people simulate it. We help people build it. We help people measure it. No other RF/microwave EDA company really offers all three phases,” he observes. The link between advanced measurement science in virtual and physical space, giving the same results any way a user chooses to work, is unique in the industry. In RF and microwave design, the destination counts, and Keysight gives customers the best chance of first-pass success with fewer schedule-killing hardware re-spins.

Doing more with automation, interoperability, and simulation

There’s also a few unknowns lurking beneath the surface. One is the “talent shortage.” It’s a case of not having the right talent with the right RF EDA tools at the right moment in the workflow. It could show up on teams spread in different departments, across facilities, across continents, or across organizations working together.

If a digital design is needed, many people and mature EDA tools can handle even complex designs on advanced processes with smooth handoffs. But introduce mixed-signal technology – CPU, memory, and RF in the same chipsets – and it’s a different game. “Designs can cross technology domains, with roundtrip loops between tools and people for changes and approvals,” notes Daren McClearnon, RF and Microwave Product Marketing Lead at Keysight. “Co-design with less RF-centric people requires another level of interoperability, or else it can degenerate to ‘trick-or-treating’ manually around an organization, trying to close design issues.”

To Kamdar’s earlier point, this looks different to an RF EDA install base versus a prospect who hasn’t embraced the right tools for one of several reasons. “We like it when our customers surface their challenges, and Keysight usually has more to offer them,” Kamdar says. Fundamental changes like using industry-standard file formats, or incremental changes like scripting a frequently-used procedure, can have a big payoff for customers.

RF design prospects face what they think are tougher decisions. Changing a workflow can be painful, and learning curve costs exist. Kamdar boils it down to one question: are your existing solutions achieving your goals? He suggests it’s not always about switching tools per se but more about bringing in a tool that integrates with the mix of tools in service and delivers value without disrupting workflows and adding extra steps.

Kamdar says people know Keysight for RF and 5G design and electromagnetic simulation technology but not so much for other solutions in the portfolio, like thermal simulation, packaging design, and multi-physics analysis. Trust is vital, and Kamdar wants more prospects to experience what customers already see with real-world simulation accuracy. But the emphasis on automating processes and making everything interoperable to help the talent shortfall is equally important in the Keysight 2023 strategy.

Three areas where new Keysight RF and microwave EDA innovation is coming

Kamdar walked us through three focused areas for RF EDA innovation his R&D teams are aggressively pursuing, with rollouts expected throughout 2023.

Multi-technology and Open Platforms. Streamlining physical co-design and verification in an all-Keysight environment or in workflows paired with Cadence, Synopsys, and other EDA tools is a top priority. There are also ongoing improvements in foundry PDK offerings, with developments coming from several new or enhanced foundry and semiconductor partnerships.
6G and mmWave Technology Leadership. Keysight is deeply committed to active participation in specification development for 5G-Advanced and 6G and supporting early-stage research working with customers. Improvements to the core EM simulation engine in several product lines target densification challenges, pushing state-of-the-art forward.
Enterprise Scale and Transformation. Cloud and high-performance computing platforms are having enterprise-wide productivity impacts. Keysight is bringing them to bear on RF and microwave engineering, scaling up for peak demands at critical moments in the development life cycle. The “all Python, all the time” message drives enhancements for scripted automation of repetitive tasks.

Looking further ahead, Kamdar also sees a more prominent role for AI/ML in modeling and simulation. A decade of Keysight AI/ML research is starting to weave its way into its RF EDA solutions. One exciting application for artificial neural network (ANN) technology is the datasheet curve-to-model work from Alex Petr’s team.

Kamdar concludes that with in-person tradeshows restarting, he and his team are excited to get out and see customers face-to-face again. Keysight’s RF and microwave EDA vision and latest announcements will be on full display this year at several major industry events, including IEEE’s IMS 2023 in San Diego in June and the 60^th DAC in San Francisco in July. On the virtual event front, Keysight will speak on February 15^th in an online panel moderated by Microwave Journal, pairing with Analog Devices, featured in a new Keysight case study on reference designs for RF front ends.

Microwave Journal Online Panel:
What is the Best Beamsteering Antenna Array and Repeater Technologies for 5G mmWave?

Also Read:

Higher-order QAM and smarter workflows in VSA 2023

Advanced EM simulations target conducted EMI and transients

Seeing 1/f noise more accurately

Podcast EP143: FPGAs, eFPGAs and the Emerging Chiplet Market

Podcast EP143: FPGAs, eFPGAs and the Emerging Chiplet Market
by Daniel Nenni on 02-10-2023 at 10:00 am
3 Comments

Dan is joined by Nick Ilyadis, Senior Director of Product Planning at Achronix. With over 35 years of data and semiconductor engineering and manufacturing experience and 72 issued patents under his name, Nick is a recognized expert on software and hardware development and quality control.

Dan explores the emerging chiplet market with Nick. The impact of standards, advanced packaging challenges and how and why to assemble a multi-die chiplet-based system are discussed. The application of chiplets in FPGA and eFPGA applications is also explored.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

Achronix Semiconductor Corporation is a fabless semiconductor corporation based in Santa Clara, California, offering high-end FPGA-based data acceleration solutions, designed to address high-performance, compute-intensive and real-time processing applications. Achronix is the only supplier to have both high-performance and high-density standalone FPGAs and licensed eFPGA IP solutions. Achronix Speedster®7t FPGA and Speedcore™ eFPGA IP offerings are further enhanced by ready-to-use VectorPath™ accelerator cards targeting AI, machine learning, networking and data center applications. All Achronix products are fully supported by the Achronix Tool Suite which enables customers to quickly develop their own custom applications.

February 10, 2023September 22, 2023

Dr. Anirudh Devgan Elected to The National Academy of Engineering (NAE)

Dr. Anirudh Devgan Elected to The National Academy of Engineering (NAE)
by Daniel Nenni on 02-10-2023 at 6:00 am
Categories: Cadence, EDA
1 Comment

Having known many of the top EDA CEOs during my semiconductor tenure the common traits I have found are brilliance, humility, endurance, and a sharp sense of humor. EDA solves so many problems, complex problem after complex problem, that it takes teams of incredibly smart people to solve them. Even more difficult is leading these teams. Falling into the footsteps of great Cadence CEOs Joe Costello and Lip-Bu Tan, Dr. Anirudh Devgan has already made his place in EDA history, absolutely.

Founded in 1964, the U.S. National Academy of Engineering is a private, independent, nonprofit institution that provides engineering leadership in service to the nation. Its mission is to advance the welfare and prosperity of the nation by providing independent advice on matters involving engineering and technology, and by promoting a vibrant engineering profession and public appreciation of engineering.

National Academy of Engineering Elects 106 Members and 18 International Members

FOR IMMEDIATE RELEASE

TUE, FEBRUARY 07, 2023

Washington, D.C., February 07, 2023 —

The National Academy of Engineering (NAE) has elected 106 new members and 18 international members, announced NAE President John L. Anderson today. This brings the total U.S. membership to 2,420 and the number of international members to 319.

Election to the National Academy of Engineering is among the highest professional distinctions accorded to an engineer. Academy membership honors those who have made outstanding contributions to “engineering research, practice, or education, including, where appropriate, significant contributions to the engineering literature” and to “the pioneering of new and developing fields of technology, making major advancements in traditional fields of engineering, or developing/implementing innovative approaches to engineering education.” Election of new NAE members is the culmination of a yearlong process. The ballot is set in December and the final vote for membership occurs during January.

Individuals in the newly elected class will be formally inducted during the NAE’s annual meeting on Oct. 1, 2023. A list of the new members and international members follows, with their primary affiliations at the time of election and a brief statement of their principal engineering accomplishments.

New Members:

…

Devgan, Anirudh, president and CEO, Cadence Design Systems, San Jose, Calif. For technical and business leadership in the electronic design automation industry.

…

As we all know Anirudh is not only President and CEO of Cadence Design Systems, Inc., he is a member of the Board of Directors. Prior to becoming CEO in 2021, he was President of Cadence, Executive Vice President and General Manager of the Digital & Signoff and System Verification groups. Prior to joining Cadence in 2012, Anirudh was with Magma Design Automation, and earlier held management and technical roles at the IBM Thomas J. Watson Research Center, IBM Microelectronics Division, and IBM Austin Research Lab.

What you may not know is that Anirudh successfully pioneered the application of massively parallel and distributed architectures to create several industry firsts and most impactful products in the areas of SPICE simulation, library characterization, place and route, static timing, power and electromagnetics, among several others. He also drove the first common compiler architecture for emulation and prototyping platforms.

As with other notable EDA CEOs, Anirudh has a collection of notable associations and awards including: IEEE Fellow, holds 27 US patents, Phil Kaufman Award for his extensive contributions to EDA as well as the IBM Corporate Award and IEEE McCalla Award. He serves on the boards of the Global Semiconductor Alliance and the Electronic System Design Alliance.

So, congratulations Anirudh, it is a pleasure working with you and thank you very much for your contributions to EDA!

Also Read:

2022 Retrospective. Innovation in Verification

Validating NoC Security. Innovation in Verification

Functional Safety for Automotive IP

February 9, 2023April 10, 2023

The State of IC and ASIC Functional Verification

The State of IC and ASIC Functional Verification
by Daniel Payne on 02-09-2023 at 10:00 am
Categories: EDA, Siemens EDA

Way back in 2002 there was a study from Collett International Research on functional verification, and since 2010 the Wilson Research Group has continued that same kind of study with a new report every two years. What attracts me to this report is that it doesn’t just look at the installed base of one EDA vendor, instead it looks across the world asking questions of design and verification engineers, so that the rest of us in the semiconductor industry can understand what the trends are for functional verification.

Our global semiconductor market had a total value of $547 billion in 2021, dipping to $545 billion in 2023, then forecasted to grow to $635 billion in 2025, according to IBS, where the IC and ASIC segment would reach $330.9 billion in 2025. Systems designers using IC and ASIC components expect that functional verification has been thorough and correct, ensuring that their products operate properly and reliably.

980 engineers responded to the 2022 survey across the implementation spectrum of FPGA, IC, ASIC, full custom, structured custom, structured ASIC, to even include embedded array and gate array design styles. This blog focuses just on the IC and ASIC segments.

The very first metric in the report showed a sad result that first silicon success was moving downwards at only 24%, which means an expensive re-spin plus lost time to market for even more lost revenues.

# of IC and ASIC spins

The top five causes for these silicon re-spins in ranked order are:

Logic, functional
Analog
Power Consumption
Clocking
Yield

So functional flaws are the number one cause for failure, then this category is expanded to show us how design errors, changes in the specification and incorrect specification are the low-level culprits. IP vendors should note that both internal and external IP blocks contribute less to functional flaws than design errors.

Functional Flaws

Here’s a common question from management, “Is the project on schedule?” Not quite is the realistic answer, as 66% of IC and ASIC projects completed behind schedule.

Project Design Completion

The percentage of total time spent in functional verification has held pretty constant since 2008 at about 70%, while the mean peak number of both design and verification engineers has grown to about 12. Even design engineers are spending 49% of their time doing verification. Verification engineers spread their time doing five activities:

47% – Test planning
21% – Creating Test and Running Simulation
15% – Testbench Development
13% – Debug
5% – Other

IC and ASIC trends show that the number of embedded processor cores is increasing, as 74% have one or more cores, 52% include two or more cores, and 15% have eight or more cores. RISC-V processors were found n 30% of designs in 2022, up 23% from two years prior. AI accelerators were seen in 32% of designs. To manage power on SoC designs we see an increase in the number of clock domains, with 3-4 being the average number.

Asynchronous clock domains are predominant at 93% of designs, creating a need for more gate-level simulation and CDC verification tools. Security features are being added to 58% of IC/ASIC designs for things like encryption keys, DRM keys and handling sensitive data. Here’s the distribution for safety-critical standards:

Safety-critical Standards

FuSa (Functional Safety) project time was spent on four activities, taking less than 25% of project time: Safety Analysis, Safety Architecture and design, Safety requirements, Safety verification.

Verification languages and methodology are spread out across 10 categories, with SystemVerilog in top use, while Verilog use decreases, and Python is an emerging trend:

Verification Languages

Accellera UVM remains the most used verification methodology, and the Python-based cocotb was recently added this year.

Verification Methodologies

For assertion languages there is SystemVerilog Assertions still on top at 72%, with OVL at 15% and PSL at 9%. Formal property checking was used in 35% of designs, and automatic formal checking grew to 32% of designs, both categories grew quickly in the past 8 years.

There are four simulation-based techniques tracked in the survey, so no new approaches added in the past 15 years:

Simulation Techniques

Software-based verification is limited by speed and capacity issues, so hardware-based emulation and FPGA prototyping have arrived just in time to help verify the largest SoC devices by running actual software and operating systems. The top six reasons to use emulation or FPGA prototyping are listed with HW/SW co-design and verification as the most important factor.

Emulation and Prototyping

Emulation and prototyping have recently improved in capacity to exceed 1 billion gates, not counting memories.

Summary

Functional verification is essential to knowing that a new electronic design meets the specification, functions reliably and works properly on first silicon. Both design and verification engineers spend their time in functional verification using multiple languages, methodologies and even hardware-assisted platforms to reach their goals of on-time project delivery. This bi-annual report is rich with information to help our industry see the functional trends for IC and ASIC designers, then respond with best practices and keep engineers updated and trained on how to work smarter, not harder.

Read the complete 17 page report by requesting it online.

Stay tuned for a separate blog on FPGA functional verification trends.

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February 9, 2023May 5, 2023

Synopsys Design Space Optimization Hits a Milestone

Synopsys Design Space Optimization Hits a Milestone
by Bernard Murphy on 02-09-2023 at 6:00 am
Categories: AI, EDA, Synopsys

I talked recently with Stelios Diamantidis (Distinguished Architect, Head of Strategy, Autonomous Design Solutions) about Synopsys’ announcement on the 100^th customer tapeout using their DSO.ai solution. My concern on AI-related articles is in avoiding the hype that surrounds AI in general, and conversely the skepticism in reaction to that hype prompting some to dismiss all AI claims as snake oil. I was happy to hear Stelios laugh and agree whole-heartedly. We had a very grounded discussion on what DSO.ai can do today, what their reference customers see in the solution (based on what it can do today) and what he could tell me about the technology.

What DSO.ai does

DSO.ai couples with Fusion Compiler and IC Compiler II, which as Stelios was careful to emphasize means this is a block-level optimization solution; Full SoCs are not a target yet. This fits current design practices as Stelios said an important goal is fit easily into existing flows. The purpose of the technology is to enable implementation engineers, often a single engineer, to improve their productivity while also exploring a larger design space for a better PPA than might have been discoverable otherwise.

Synopsys announced the first tapeout in the summer of 2021 and have now announced 100 tapeouts. That speaks well for the demand for and effectiveness of a solution like this. Stelios added that the value becomes even more obvious for applications which must instantiate a block many times. Think of a many-core server, a GPU, or a network switch. Optimize a block once, instantiate many times – that can add up to a significant PPA improvement.

I asked if customers doing this are all working at 7nm and below. Surprisingly, there is active use all the way up to 40nm. One interesting example is a flash controller, a design which is not very performance sensitive but can run to tens to hundred of million units. Reducing size even by 5% here can have a big impact on margins.

What’s under the hood

DSO.ai is based on reinforcement learning, a hot topic these days but I promised no hype in this article. I asked Stelios to drill down a bit more though wasn’t surprised when he said he couldn’t reveal too much. What he could tell me was interesting enough. He made the point that in more general applications, one cycle through a training set (an epoch) assumes a fast (seconds to minutes) method to assess next possible steps, through gradient comparisons for example.

But serious block design can’t be optimized with quick estimates. Each trial must run through the full production flow, mapping to real manufacturing processes. Flows which can take hours to run. Part of the strategy for effective reinforcement learning given this constraint is parallelism. The rest is DSO.ai secret sauce. Certainly you can imagine that if that secret sauce can come up with effective refinements based on a given epoch, then parallelism will accelerate progress through the next epoch.

To that end, this capability really must run in a cloud to support parallelism. Private on-premises cloud is one option. Microsoft has announced that they are hosting DSO.ai on Azure, and ST report in the DSO.ai press release that they used this capability to optimize implementation of an Arm core. I imagine there could be some interesting debates around the pros and cons of running an optimization in a public cloud across say 1000 servers if the area reduction is worth it.

Customer feedback

Synopsys claims customers (including ST and SK Hynix in this announcement) are reporting 3x+ productivity increases, up to 25% lower total power and significant reduction in die size, all with reduced use of overall resources. Given what Stelios described, this sounds reasonable to me. The tool allows exploration of more points in the design state space within a given schedule than would be possible if that exploration were manual. As long as the search algorithm (the secret sauce) is effective, of

course that would find a better optimum than a manual search.

In short, neither AI hype nor snake oil. DSO.ai suggests AI is entering the mainstream as an credible engineering extension to existing flows. You can learn more from the press release and from this blog.

Also Read:

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Synopsys Crosses $5 Billion Milestone!

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February 8, 2023February 8, 2023

Cliosoft’s Smart Storage Strategy for Better Workspace Management

Cliosoft’s Smart Storage Strategy for Better Workspace Management
by Kalar Rajendiran on 02-08-2023 at 10:00 am
Categories: Cliosoft, EDA

Over the years storage has gotten very cheap, or has it? As a typical consumer, we take data storage for granted because access to it has gotten very cheap. Long gone are the days of being limited to 1.44MB floppy disks to store data. The smart devices we carry around with us can store 100’s of GB of data. That is a lot of data. But what about when we have to deal with data management when designing these very smart devices? The demand for data storage and management goes up orders of magnitude. Specifically, within the semiconductor realm, chip design data management is about terabytes and terabytes of data. It does not matter whether a company is using on-prem storage or cloud storage, the total cost of ownership (TCO) becomes an expensive proposition.

With teams of engineers accessing, adding, modifying and deleting data, the strategy for workspace management takes paramount importance. A smarter storage strategy is needed to enable efficient and cost-effective workspace management.

Pedro Pires from Cliosoft delivered an excellent webinar recently to address this very topic. Pedro is an application engineer and used Cliosoft’s SOS solution as the backdrop. His talk focused on minimizing design data storage consumption, fast workspace creation, and lightweight resource consumption.

Drawbacks of Traditional Approach to Workspace Storage Management

Many traditional solutions for data management simply make copies of the project data for as many users who are working on that project. While this may give the feeling of complete data control to every user, it is obviously a very storage inefficient approach. For example, if the project data size is 100GB and there are 10 users on the project, 1.1TB of storage is needed for starters. The bigger the project team, the more inefficient the storage solution becomes.

A better data management solution is preferable. And if that better solution can offer additional benefits on top of the storage efficiency, all the better.

Cliosoft SOS Solution for Workspace Storage Management

The Cliosoft SOS solution uses a three-pronged approach for very efficient project workspace storage management.

Links to Cache Feature

When the various users of a project create their workspace under the SOS solution, no physical copies of the project data are made. Instead, symbolic links are made to the actual physical copy that exists in the main repository. This automatically reduces the workspace footprint compared to the traditional data management solution discussed earlier.

When users want to work on particular views/files, they would checkout those files and SOS would automatically replace the relevant symbolic links with an actual copy of the views/files. Once the users work on these files and make necessary modifications, they can check those files back in. SOS will commit those changes to the physical copy in the main repository and replace the users’ physical copy with symbolic links again.

The cache repository keeps just a few revisions of all the data held in the main repository. This is a configurable aspect of the solution and the customer can select the number of revisions for the cache repository. But when it comes to the metadata contained in the main repository, the cache repository holds an exact copy of it. SOS keeps the metadata synchronized in real-time across all project sites, thus enabling all users to be looking at the same state of the project at any point in time.

Reference and Reuse Feature

Reuse of proven IP is very commonly practiced. That in itself is not a new concept. But how the proven IP is used from a data management perspective is what is new with the Cliosoft SOS solution. Instead of copying the various proven IP blocks for use in the project on hand, SOS makes references to these IP blocks. On top of storage space savings, the Reference and Reuse approach delivers IP trackability and traceability benefits as well. IP traceability is not only important but is a requirement when designing products in certain industries.

“Sparse Populate” Feature

The Sparse Populate feature takes the Links to Cache functionality of the SOS solution to the next level by further reducing the user workspace requirements. Invariably, in most projects, there are blocks of data, such as a library or PDK data that are only needed on a read-only basis. Instead of making symbolic links to each and every file within the library or PDK folder, the SOS solution creates a symbolic link to just the top-level of the directory structure.

When and as needed, SOS provides the ability for a user to switch from Sparse Populate setup to a fully-populated copy. When this switch is made, SOS replaces the top-level symbolic link with symbolic links to all the individual files within that directory structure. The user is able to make any changes to the required files and check back the updated files to the repository. Once done, the user can revert back to the Sparse Populate setup.

Summary

Cliosoft’s SOS solution allows customers to mix and match the functionality discussed above on a workspace by workspace basis. This offers flexibility for one user to use the Links to Cache functionality when another user may decide to use the physical copy approach. But for the conscious choice made, a user wouldn’t know the difference in terms of data access and performance as SOS automatically handles the operations. With the IP tracking and traceability functionality built into SOS, users can generate “who uses me” reports for various IP blocks to meet certain compliance requirements.

The entire webinar could be accessed here on-demand.

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February 8, 2023March 15, 2023

ASIL B Certification on an Industry-Class Root of Trust IP

ASIL B Certification on an Industry-Class Root of Trust IP
by Bernard Murphy on 02-08-2023 at 6:00 am
Categories: Automotive, EDA, Security, Siemens EDA
1 Comment

I have always been curious about how Austemper-based safety methodologies (from Siemens EDA) compares with conventional safety flows. Siemens EDA together with Rambus recently released a white paper on getting a root of trust IP to ASIL B certification. This provides a revealing insight beyond the basics of fault simulation into a detailed campaign on an industrial scale IP. Siemens EDA and Rambus describe using the Austemper toolset on the on Rambus RT-640 root of trust IP, and the steps they went through to achieve functional safety metrics required for ASIL B certification.

The Austemper toolkit

In a typical FMEDA flow you would first use spreadsheets and engineering judgment to decide where you should insert safety mitigation techniques in an RTL design. Then you would run a fault campaign using fault simulation to determine how effectively your mitigation techniques have worked, as measured by the appropriate ASIL requirements. This could lead to lengthy loops to reach targets such as those for ASIL B.

In the Austemper flow, SafetyScope will estimate FIT rates and FMEDA metrics, and suggest a preliminary fault list before safety insertion. It can then be run again after fault simulation to provide a summary report with final metrics and detection coverage. Kaleidoscope runs fault simulation, categorizing faults as detected, not detected, not triggered, or not observed (at an observable point).

Faults modeled in the analysis

Following the standard, the Austemper flow models three types of faults:

Transient. These are as the name suggests temporary faults and may result from cosmic rays, electromagnetic interference, or other transitory stimuli. The flow runs a quick pseudo-synthesis to find state elements, putting these into the fault list. During analysis such a fault will be enabled at the outset then removed after some time window, remaining active until that point. The length of the window is configurable.

Permanent. These are durable faults and may result from design errors, configuration errors, deadlocks or other influences which can create a stuck state. Candidates include state and non-state elements and are modeled using stuck-at-1 or 0 values, just as in DFT analyses. These errors persist throughout a fault simulation.

Latent. These faults are very tricky to find and to mitigate because they result from a failure depending on two or more faults in the system, especially when one of them occurs in safety mitigation logic. Austemper models latent faults with one stuck-at in the functional logic and one in the corresponding safety system. (Latent faults depending on 3+ simultaneous failures have very low probability.)

Practical considerations in the fault campaign

Fault simulation of many faults over a large circuit could consume a huge amount of time without careful planning. The Siemens and Rambus guys suggested several techniques they used to keep this manageable.

First, they don’t always work with the full fault list. They strategically evaluate subsets of faults at different stages to slim down the set, before working on the hardest cases. For example, they analyze first around known safety-critical areas. Then they (temporarily) reduce the fault-tolerant time interval (FTTI) to determine faults which can be detected quickly. With similar intent, they temporarily treat sequential elements as observable points, allowing them to filter out any faults which reach a primary output without triggering an alarm.

This ultimately leaves them with a subset of undetected faults which must be analyzed for the full FTTI to determine if any escape to an output without raising an alarm. These are the most expensive to evaluate since they can fanout through multiple cycles, creating multiple simultaneously active faulty traces before ultimately registering as detected or otherwise.

Fault simulation depends on stimulus vector which may not trigger a fault, or may trigger it but not lead to it raising an alarm or being observed at a primary output. These faults they consider unclassified. Improving the stimulus may help but there are limits to that option for a software based and heavily parallelized software fault simulation. They suggest a couple of options to reduce the number of unclassified faults. In bus simplification, they assert that if a fault in one bit is detected, then all bits get the same classification. They make a similar assertion for duplicated instances of a module. If all faults within one instance are successfully classified, then all instances in other instances are also deemed classified. Finally they set an empirical threshold for the number of stimuli against which they test. A level at which they feel they tried “hard enough”. Arbitrary yes, but I don’t know how I would do any better.

Nice paper. You can read it HERE.

Also Read:

The State of IC and ASIC Functional Verification

ASIL B Certification on an Industry-Class Root of Trust IP

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