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December 10, 2023December 10, 2023

IEDM Buzz – Intel Previews New Vertical Transistor Scaling Innovation

IEDM Buzz – Intel Previews New Vertical Transistor Scaling Innovation
by Mike Gianfagna on 12-10-2023 at 2:00 pm
Categories: Events, Foundries, Intel Foundry
3 Comments

For more than 65 years, the IEEE International Electron Devices Meeting (IEDM) has been the world’s pre-eminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. As I post this, the conference is underway in San Francisco and Intel is presenting a series of first-of-a-kind advances to extend Moore’s Law. The palette of innovations being presented at the conference creates a new path to vertical device scaling, opening the opportunity for a trillion transistors on a package by 2030. This is a story with several parts. Here are the details of how Intel previews new vertical transistor scaling innovation at IEDM.

The Impact

Everyone knows about the incredible exponential scaling delivered by Moore’s Law over the past 50 years or so. We’ve also seen the monolithic effects of Moore’s Law slowing of late. Multi-die design is now adding to the exponential density increases the industry has come to rely on. But that’s not the whole story. It turns out on-chip transistor density scaling is alive and well and is a key contributor to semiconductor industry health.

And Intel, the birthplace of Moore’s Law, is leading the way with innovation that fuels both monolithic and multi-die trends. In the area of advanced packaging to fuel multi-die design, you can read about Intel’s innovation with glass substrates here. The subject of this post is what Intel is doing to fuel the other trend – monolithic transistor scaling. This is a story of innovation in the Z-axis; how to stack devices on top of each other to deliver more in the same area.

It turns out there are two fundamental barriers to overcome here. First, how to stack CMOS devices to deliver reliable, high-performance characteristics. And second, how to get power to those devices without reducing reliability and performance. There are a series of presentations at IEDM this week that present several innovations that address these problems. Here are some details…

A Preview of Intel’s Announcements

I was fortunate to attend a pre-IEDM briefing where some of Intel’s advanced researchers previewed what was being presented at IEDM. What follows is a summary of their comments.

Paul Fisher

First to speak was Paul Fisher, Director of Chip Mesoscale Processing Components Research at Intel. Paul began with an introduction to the Components Research Group. He explained this organization is responsible for delivering revolutionary process and packaging technology options that advance Moore’s Law and enable Intel products and services. Some of the research that came from this group and found its way into commercial Intel products includes strained silicon, high-K metal gate, the FinFET transistor, Power Via technology and the RibbonFET. The list is much longer – quite impressive.

Another remarkable characteristic of this organization is the breadth of its worldwide collaboration. Beyond US government agencies, Paul explained the group also collaborates with consortia around the world such as Imec, Leti, Fraunhofer, and others in Asia. The group also directly sponsors university work and mentors other programs through organizations such as the Semiconductor Research Corporation (SRC). The group also works with the semiconductor ecosystem to ensure the equipment and processes needed for new developments are available.

Paul then set the stage for the three briefings that followed. The first discussed innovations in backside power delivery. The second discussed three-dimensional transistor scaling and interconnect. And the third presented advances for on-chip power delivery using Gallium-Nitride (GaN). These three areas are summarized in the top graphic for this post.

Mauro J. Kobrinsky

Next to speak was Mauro J. Kobrinsky, Intel Fellow, Technology Development Director of Novel Interconnect Structures and Architectures. Mauro began by explaining that large, low resistance power routing competes with fine, low capacitance signal routing. The result is a compromise in density and performance. A significant advance that reduces this problem is back-side power delivery. Using this approach, power delivery routing can be done on the backside of the device, freeing critical front-side real estate for more optimal signal routing.

Mauro explained that Intel’s Power Via technology will move to production is 2024 and this will begin to open new options for back-side power delivery. Additional research will also be presented that takes back-side power delivery to a new level. This includes the development of back-side contacts to allow power to be delivered through the backside while signals are delivered through the front-side of the device.

Mauro also discussed critical enhancements for stacked device routing that are underway. Stacked devices present a unique set of challenges for both power and signal routing. In the signal area, new approaches for epi-epi and gate-gate connection must be developed and this is part of the research Mauro discussed.

Marko Radosavljevic

After Mauro, Marko Radosavljevic, Principal Engineer at Intel discussed three-dimensional transistor scaling and interconnect. Essentially what comes after RibbonFET. Marko explained that initial device stacking results were presented by Intel at IEDM in 2021.

What will be presented at IEDM this year is the implementation of a vertically stacked NMOS and PMOS RibbonFET device configuration with Power Via and direct back-side device contacts with a poly pitch of 60nm. The resultant compact inverter exhibits excellent performance characteristics, paving the way for more widespread use of vertical device stacking.

The final speaker was Han Wui, Principal Engineer, Components Research at Intel. Han discussed new approaches to on-chip power delivery. He explained that Intel proposed the first MOS power driver in 2004. This device, often called DrMOS is now used in a wide variety of products.

Han Wui

Han went on to explain that Gallium Nitride, or GaN devices are popular today for high-voltage applications like the 200-volt devices in many laptop charging “bricks”. It turns out GaN exhibits far superior performance at lower voltages (48-volt and below) when compared to CMOS power devices.

At this year’s IEDM, Han explained that Intel will show the first implementation of a process that integrates CMOS devices with GaN power devices on a 300mm wafer. Dubbed DrGaN, Han explained that this technology will open new levels of performance and density for future designs by integrating CMOS drivers with highly efficient GaN power devices on the same wafer.

To Learn More

You can get a broader view of Intel’s device and process innovation here. And that’s how Intel previews new vertical transistor scaling innovation at IEDM.

Also Read:

Intel Ushers a New Era of Advanced Packaging with Glass Substrates

How Intel, Samsung and TSMC are Changing the World

Intel Enables the Multi-Die Revolution with Packaging Innovation

Podcast EP197: A Tour of the RISC-V Movement and SiFive’s Contributions with Jack Kang

Podcast EP197: A Tour of the RISC-V Movement and SiFive’s Contributions with Jack Kang
by Daniel Nenni on 12-08-2023 at 10:00 am

Dan is joined by Jack Kang of SiFive. As a member of the founding team at SiFive, Jack oversees the Business Development, Customer Experience, and Corporate Marketing groups. He is responsible for strategic business initiatives and partnerships, technical pre-sales activities and post-sales support, and corporate messaging and campaigns. Prior to SiFive, Jack held a variety of senior business development, product management, and product marketing roles at NVIDIA and Marvell with a long track record of successful, large-scale design wins. He also has over 20 U.S. patents from his time as a CPU design engineer.

Dan explores the growth of the RISC-V movement and SiFive’s contributions with Jack. The growth from embedded to end application is discussed, along with the attributes of the RISC-V architecture and ecosystem that are helping this growth. Many aspects of RISC-V are touched on in this far-reaching discussion, from China’s involvement to aerospace applications and ARM’s influence on the overall market.

Jack also discusses SiFive’s contributions and plans as the largest company. focused on RISC-V development.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

December 8, 2023December 9, 2023

CEO Interview: Suresh Sugumar of Mastiska AI

CEO Interview: Suresh Sugumar of Mastiska AI
by Daniel Nenni on 12-08-2023 at 6:00 am
Categories: AI, CEO Interviews, RISC-V

Suresh is a technology executive with deep technical expertise in semiconductors, artificial intelligence, cybersecurity, internet-of-things, hardware, software, etc. He spent 20 years in the industry, most recently serving as an Executive Director for open-source zero-trust chip development at Technology Innovation Institute, Abu Dhabi, and in other Fortune 500 semiconductor companies such as Intel, Qualcomm, and MediaTek in various leadership roles, where he researched and developed high-performant, energy-efficient, post-quantum secure, safe microchips/ system-on-chips (SoCs)/ accelerators for the Datacenter, Client, Smartphone, Networking, IoT, and AI/ML markets. He holds 15+ US Patents and has published/presented at more than 20+ conferences.

Suresh is also actively serving in a leadership position at RISC-V International where he chairs the Trusted Computing Group to develop RISC-V confidential computing capability and chairs the AI/ML Group to develop RISC-V hardware acceleration for AI/ML workloads such as Transformer Large Language Models used in ChatGPT kind of applications. He also advises startups and venture capital firms on investment decision support, product strategy, technology due diligence, etc.

He earned an MBA from INSEAD, an MS from Birla Institute of Technology & Science Pilani, a Systems Engineering certificate from MIT, an AI certificate from Stanford, and an automotive functional safety certificate from TÜV SÜD.

Tell us about your company
“Mastiṣka AI” (Mastiṣka means Brain in Sanskrit) is an AI company focused on building brain-like computers to run foundation models more efficiently for Generative AI use cases of tomorrow.

What problems are you solving?
Given the benefits of AI/ GenAI, its demand is only bound to go up, and so will its side effects on our planet. How can we reduce or neutralize the side effects of AI on our planet? Carbon capture and nuclear power are in the right direction. But we need to fundamentally rethink the way we do AI, is it the wrong way to do tonnes of matrix multiplications?

Our brain can learn and do many tasks in parallel, in and under 10W, but why do these AI systems consume 10s of megawatts to train models?

Perhaps the future holds energy-efficient architectures such as neuromorphic architectures and spiking neural network-based transformers that are closest to the human brain, which might consume 100-1000x lower energy, hence reducing the cost of using AI, thereby democratizing it and saving our planet.

The current challenges we face with AI namely a) availability, b) accessibility, c) affordability, and d) environmental safety along with some recommendations to tackle them.

If we foresee in the future, some useful AGI concepts are demonstrated in the movie “HER”, where the character ‘Samantha’ – a conversational agent who is natural, understands emotions, shows empathy, is an amazing copilot at work — and runs on handheld devices the entire day, then we may have to address the below challenges right now.

Issue 1: Training an LLM can cost anywhere from 150K to 10+ million dollars, and it allows only those with deeper pockets to develop AI. On top, inferencing costs are huge too (costs 10x more than a web search)
—> We need to improve the energy efficiency of models/ hardware to democratize AI for the benefit of humanity.

Issue 2: Running ginormous AI models for conversational agents or recommendation systems, puts a toll on the environment in terms of electricity consumption and cooling.
—> We need to improve the energy efficiency of models/ hardware to save our planet for our kids.

Issue 3: The human brain is capable and can multitask, but consumes only 10 Watts instead of Megawatts.
—> Perhaps we should build machines like our brains and not the regular matrix multipliers faster.

Humanity can only thrive with sustainable innovations, and not by cutting down all forests and boiling the oceans in the name of innovation. We must protect our planet for the welfare of our children and future generations to come…

What application areas are your strongest?
Training and Inferencing of Transformer (and future neural architecture) based foundation models, at 50-100x more energy efficiently compared to today’s GPU-based solutions.

What keeps your customers up at night?
Issues for customers who currently use other products:

Electricity consumption for training humungous language models is beyond the roof, for example, training a 13B parameter LLM on 390B text tokens on 200 GPUs for 7 days costs $151,744 (Source: HuggingFace new training cluster service page – https://lnkd.in/g6Vc5cz3). And even larger models with 100+B parameters cost $10+M just to train. Then pay for inferencing every time a new prompt request arrives.

Water consumption for cooling, researchers at the University of California, Riverside estimated the environmental impact of ChatGPT-like service, and say it gulps up 500 milliliters of water (close to what’s in a 16-ounce water bottle) every time you ask it a series of between 5 to 50 prompts or questions. The range varies depending on where its servers are located and the season. The estimate includes indirect water usage that the companies don’t measure — such as to cool power plants that supply the data centers with electricity. (Source: https://lnkd.in/gybcxX8C)

Issues for non-customers of current products:

Can’t afford CAPEX to buy hardware
Can’t afford to use cloud services
Can’t innovate or leverage AI — stuck with services model that eliminates any competitive advantage

What does the competitive landscape look like and how do you differentiate?

GPUs dominiate training space, even though specialized ASICs also compete in this segment
Cloud & Edge inference has too many options available

Digital, Analog, Photonic — you name it people are trying to tackle the same problem.

Can you share your thoughts on the current state of chip architecture for AI/ML, meaning, what do you see as the most significant trends and opportunities right now?

Following trends:
Trend 1: 10 years ago, hardware-enabled deep learning flourished, and now the same hardware is inhibiting progress. Due to the huge cost of hardware and electricity costs to run models, it has become a challenge to access the hardware. Only companies with deep pockets are able to afford these and are becoming monopolies.

Trend 2: Now that these models are there, we need to use them for practical purposes so that the inferencing load will increase, allowing CPUs with AI accelerators to come to the limelight again.

Trend 3: Startups are trying to come up with alternative floating point number representations that the traditional IEEE format – such as logarithmic and posit-based — are good but not enough. PPA$ design space optimization explodes when we try to optimize one and another goes for a toss.

Trend 4: The industry is moving away from the service-based model of AI to hosting its own private models on its own premises — but access to hardware is a challenge due to supply shortages, sanctions, etc

Current state of affairs:
Availability of hardware and data fueled the growth of AI 10 years ago, now the same hardware is sort of inhibiting it — let me explain

Ever since CPUs were doing miserable and GPUs were repurposed to do AI, many things happened

Companies have been addressing 4 segments of AI/ML namely – 1) cloud training, 2) cloud inferencing, 3) edge inferencing, and 4) edge training (federated learning for privacy-sensitive applications).
Digital & Analog

Training side – a plethora of companies doing GPUs, customer accelerators based on RISC-V, wafer-scale chips (850K cores), and so on where traditional CPUs lack (their general purpose). Inference side – NN accelerators are available from every manufacturer, in smartphones, laptops, and other edge devices.

Analog memristor-based architectures also showed up some time ago.

We believe CPUs can be very good at inferencing if we enhance it with acceleration such as matrix extensions

RISC-V side of things:
On the RISC-V side of things, we are developing accelerators for matrix operations and other non-linear operations to eliminate possible bottlenecks for transformer workloads. Von Neumann bottlenecks are also being addressed by architecting memories closer to computing, eventually making CPUs with AI acceleration the right choice for inferencing.

Opportunities:
Unique opportunities exist to fill in the market of foundation models. Example – OpenAI have been mentioning they were not able to secure enough AI compute (GPUs) to continue to push their ChatGPT services… and the news reports about electricity costs of 10x of that of regular internet search and 500ml of water to cool down the systems for every query. There is a market to fill in here — its not niche, but its the entire market that will democratize AI tackling all the challenges mentioned above – a) availability, b) accessibility, c) affordability, and d) environmental safet

What new features/technology are you working on?
We are building brain like computer leveraging neuromodrphic technuques and tailoring models to take advantage of the energy efficient hardware, reusing may of open frameworks available

How do you envision the AI/ML sector growing or changing in the next 12-18 months?
As the demand for GPUs have soured (costing like $30K) plus some parts of the world are facing sanctions to buy these GPUs, some parts of the world are feeling they are frozen in AI research and development without access to GPUs. Alternate hardware platforms are going to capture the market.
Models perhaps will start shrinking — custom models or even fundamentally the information density would grow

Same question but how about the growth and change in the next 3-5 years?
a) CPUs with AI extensions would capture the AI inference market
b) Models would become nimble, and parameters will drop out as information density improves from 16% to 90%
c) Energy efficiency improves, CO2 foot print reduces
d) New architectures come up
e) hardware costs and energy costs go down so the barrier to entry for smaller companies to create and train models becomes affordable
f) people talk about pre-AGI moment, but my benchmark would be the characted Samantha (conversational AI) in movie “her”.. that maybe unlikely given the high cost of scaling up

What are some of the challenges that could impact or limit the growth in AI/ML sector?
a) Access to hardware
b) Energy costs and cooling costs and environmental harm

Also Read:

CEO Interview: David Moore of Pragmatic

CEO Interview: Dr. Meghali Chopra of Sandbox Semiconductor

CEO Interview: Dr. J Provine of Aligned Carbon

December 7, 2023March 7, 2024

Analysis and Verification of Single Event Upset Mitigation

Analysis and Verification of Single Event Upset Mitigation
by Jacob Wiltgen on 12-07-2023 at 10:00 am
Categories: EDA, Siemens EDA

The evolution of space-based applications continues to drive innovation across government and private entities. The new demands for advanced capabilities and feature sets have a direct impact on the underlying hardware, driving companies to migrate to smaller geometries to deliver the required performance, area, and power benefits.

Simultaneously, the application space is evolving, and mission parameters for these new applications are causing companies to evaluate non-traditional approaches. Commercial high-reliability processes (i.e., those developed for automotive designs) are being considered for aerospace as they meet both the survivability requirements of certain scenarios and provide reduced development timelines and cost.

Unfortunately, the advantages delivered in lower geometries come at a cost, and one of those drawbacks is that the underlying hardware is more susceptible to soft errors, commonly referred to as single event upsets (SEU). Traditional approaches of redundancy or triplication on salient (if not all) functions within the chip are quickly becoming cost prohibitive.

Fortunately, new flows and automation provide project teams insights into SEU mitigation and offer the ability to optimize the SEU mitigation architecture, also referred to as selective hardening.

Figure 1. Driving trends to selective radiation mitigation

First, let’s review the challenges.

Selective Hardening Challenges

Feedback from the aerospace industry suggests that the traditional approach to SEU mitigation has many pitfalls and leaves two important questions unanswered.

For the design elements known to be mission critical, how effective is the implemented mitigation?
How can I identify the potential of failure due to faults in design elements not protected?

The traditional approach to SEU mitigation is best summarized in a three-step workflow.

Step 1: Identify failure points through expert driven analysis
Step 2: Design engineers insert the mitigation (HW and/or SW)
Step 3: Verify the effectiveness of the mitigation
- Simulation leveraging functional regressions and force commands to inject SEUs
- Post-silicon functional testing under heavy ion exposure

Figure 2: The traditional approach to SEU mitigation

Unfortunately, the traditional approach has multiple drawbacks, including:

No common measurement (metric) which determines the effectiveness of SEU mitigation.
Expert driven analysis is not repeatable or scalable as complexity rises.
Manually forcing faults in functional simulation requires substantial engineering effort.
An inability to analyze the complete fault state space using functional simulation and force statements.
Late cycle identification of failures when testing in a beam environment alongside limited debug visibility when they occur.

Automation and Workflows Supporting Selective Hardening

The overarching objective of selective hardening is to protect design functions which are critical to mission function and save on cost (power and area) by leaving non-critical functions unprotected. Boiling that down a level, the methodology has three aims:

Provide confidence early in the design cycle that the mitigation is optimal.
Provide empirical evidence that what is left unprotected cannot result in abnormal behavior.
Deliver a quantitative assessment detailing the effectiveness of the implemented mitigation.

Siemens has developed a methodology and integrated workflow to deliver a systematic approach in measuring the effectiveness of existing mitigation as well as determining the criticality of unprotected logic. The workflow is broken up into four phases.

Figure 3. The Siemens SEU mitigation workflow

Structural Partitioning: The first step in the flow leverages structural analysis engines to evaluate design functions in combination with the implemented hardware mitigation protecting the function. The output of structural partitioning is a report indicating the effectiveness of the existing hardware mitigation as well as insights into the gaps which exist.

Fault Injection Analysis: Mitigation which could not be verified structurally are candidates for fault injection. In this phase, SEUs are injected, propagated, and the impact evaluated. The output of fault injection analysis is a fault classification report listing which faults were detected by hardware or software mitigation and which faults were not detected.

Propagation Analysis: The SEU sites left unprotected are evaluated structurally under expected workload stimulus to determine per site criticality and its probability to result in functional failure. The output of propagation analysis is a list of currently unprotected faults which were identified to impact functional behavior.

Metrics Computation: Data from structural, injection, and propagation analysis feed the metrics computation engine and visualization cockpit. The cockpit provides visual insights into failure rate, the effectiveness of the mitigation, and any gaps that exist.

Every semiconductor development program has unique characteristics. The methodology described above is flexible and highly configurable, allowing project teams to adjust as needed.

Conclusion

Mitigation of single event upsets continues to challenge even the most veteran project teams, and this challenge is exacerbated as design complexity rises and technology nodes shrink. New methodologies exist to provide quantitative results detailing the effectiveness of SEU mitigation.

For a more detailed view of the Siemens SEU methodology and the challenges it will help you overcome, please refer to the white paper, Selective radiation mitigation for integrated circuits, which can also be accessed at Verification Academy: Selective Radiation Mitigation.

Jacob Wiltgen is the Functional Safety Solutions Manager for Siemens EDA. Jacob is responsible for defining and aligning functional safety technologies across the portfolio of IC Verification Solutions. He holds a Bachelor of Science degree in Electrical and Computer Engineering from the University of Colorado Boulder. Prior to Mentor, Jacob has held various design, verification, and leadership roles performing IC and SoC development at Xilinx, Micron, and Broadcom.

Also Read:

Siemens Digital Industries Software Collaborates with AWS and Arm To Deliver an Automotive Digital Twin

Handling metastability during Clock Domain Crossing (CDC)

Uniquely Understanding Challenges of Chip Design and Verification

December 7, 2023December 27, 2023

5G Aim at LEO Satellites Will Stimulate Growth and Competition

5G Aim at LEO Satellites Will Stimulate Growth and Competition
by Bernard Murphy on 12-07-2023 at 6:00 am
Categories: 5G, Ceva, IP

Low earth orbit (LEO) satellites as an intermediary for communication became hot when Elon Musk announced Starlink (yeah, other options were available, but Elon Musk). This capability extends internet availability to remote areas and notably (for a while) to Ukraine in support of the war with Russia. Satellites can in principle provide line-of sight access anywhere, especially in areas lacking base stations (low population, mountainous, remote rural, etc). They even help in high latitude areas where access to geostationary satellites can be hampered by low-angle availability. 3GPP, the group of committees responsible for mobile communications standards, are now working on extending 5G to allow for communication through satellites, especially LEO and MEO (medium earth orbit) satellites. Thanks Elon, but we need competition to drive cost down and availability and service options up. The opportunity is significant, as are the challenges since this option isn’t just a simple extension to 5G.

Opportunity

While 75% or more of the US population lives in urban areas, only 55% of the worldwide population is urban. Nearly half the world likely does not live near a cellular base station, significantly limiting access to the internet and ability to make mobile phone calls. Even within the US or other western countries, our food production, cross-country shipping and at least 25% of the population have restricted access to those services. As any city dweller on a road trip quickly realizes.

In addition to Starlink, Amazon through their Kuiper project and T-mobile have active programs to support satellite-based communication. Market analysts estimate nearly a $30B market by 2030, with a CAGR of nearly 30%. That’s very tempting growth for operators, for infrastructure equipment makers and for handset makers if protocols can be standardized to drive growth and lower cost. Getting there will require not only extensions to 5G but also new hardware and software, as we’ll see next.

Challenges

Connecting through a satellite isn’t an incremental extension to terrestrial options. One problem is latency. Not simple there-and-back latency which for a LEO satellite runs maybe a few tens of milliseconds, not much worse than a ground-based cable link. One issue is handovers. LEO satellites orbit much closer to earth than say a geostationary satellite, which makes the coverage area much smaller for any given satellite at any given time. To maintain those orbits, LEO satellites must travel at high speed, requiring links be handed over quite frequently between satellites to maintain coverage with a ground-based device. Managing these handovers adds to latency.

Another challenge arises in managing Doppler shift in the link signal. LEO satellites travel at around 8km per second, fast enough to alter link frequencies noticeably and variably during the lifetime of a link to any given satellite. This problem isn’t a concern for terrestrial base stations traveling at 0km per second 😊

A third challenge is that the standard is not yet finalized. The 3GPP plan is aiming at support for up to tens to hundreds of Mbps bandwidth in the downlink and roundtrip delays down to a few tens of milliseconds. Those goals will require innovation in software for efficient handover management and in modems to manage the Doppler problem.

Who are you going to call?

The standard isn’t released, and production wireless solutions aren’t yet available, but that doesn’t mean you can’t start planning. This will be a competitive market demanding aggressive pricing for user equipment and for infrastructure. As usual, all components in the network must be very low power and these systems must remain compliant with baseline expectations for 5G and Open RAN. The days of dedicated phones for satellite access and proprietary solutions for large chunks of the network are far behind us.

Which makes CEVA an interesting company to talk to when planning your LEO satellite strategy. These guys have a track record for releasing solutions shortly after a standard is ratified. They already have well-proven cellular (and other wireless) IP solutions up to and including 5G, targeted to all aspects of mobile networks and UEs. Take a look at their Open RAN platform, and their 5G Modems platform for more details.

December 6, 2023December 6, 2023

Do you have Time to Pull in your Tapeout Schedule?

Do you have Time to Pull in your Tapeout Schedule?
by Ronen Laviv on 12-06-2023 at 10:00 am
Categories: AI, EDA
2 Comments

So… , we’re 4 months before tapeout. You were assigned to close place & route on three complex key blocks. You have 15 machines for the job, 5 per block.

You send your first batch, 5 runs per block. You’re not very surprised that your first batch fails. You modify the scripts, and run another batch. And… (Surprise 🙂 the runs do not converge. You have lots of ideas to improve the scripts, you make some changes and, …another run… and another…. and another…. and here we are, two months before tapeout. Still negative slacks.

What do you do?
Compromise on PPA (Power, Performance, Area)?
Delay the tapeout?

Similar questions are also relevant for verification. Think about the RTL freeze and your coverage. Think about formal verification and the properties you have proved so far.

Same with Analog, Characterizations, …

In one of the EDA vendor’s events, there was a presentation about AI for backend, how it saved few weeks of work and resulted better PPA for the tested blocks. It required 900+ CPUs. One of the engineers in the audience said… hmm… 900 CPUs!? I don’t have that compute capacity, all I have is 32CPUs or 96CPUs if I’m lucky.

Well…

Nowadays it has become easy to get as many CPUs as needed for a specific run utilizing AWS cloud.

You may rightfully say… “but I don’t have 150 (or 900) licenses just for my job”

There are two things you could do about your licenses:

Run faster and make sure you never wait in queue for machines (I’ll talk about it in one of the next articles). This will allow better utilization of the licenses you already have.
The 2nd thing you may want to do is go talk to your EDA vendors as they each have ways to address cloud flexibility licenses.

If the process of verification, place & route or any other run happens to be on your project’s critical path to tapeout, wouldn’t it make sense to pull in the schedule by utilizing resources you can use when needed most?

Back to the backend example (or verification regression), Assuming each run/regression takes ~5 days, and you happen to have only 5 machines at your disposal on premise. You could take 25 machines or more and finish your runs in 5 days instead of 25.

We should be seeing more and more usage of AI tools as Cerebrus and DSO-AI. Those tools usually require more compute than you might have available on-premise. Whoever utilize those, may cut his time to tapeout / time to market as well as improve PPA compared to manual runs.

The more adoption of AI tools, the more competitive the market would become.

With compute and AI same engineering teams could do more projects, faster, with better PPA.

Here are some public references.

Disclaimer: My name is Ronen, and I’ve been working in the semiconductor industry for the past ~25 years. In the early days of my career I was a chip designer, then moved to the vendor side (Cadence) and now spending my days in the cloud with AWS. Looking at our industry along the years, examining the pain points of our industry as a customer and a service provider I am planning to write a few articles to shed some light on how chip design could benefit from the cloud revolution that is taking place these days.

In the coming articles I’ll cover more aspects of performance & cost for chip design in the cloud.

C U soon.

Also Read:

Generative AI for Silicon Design – Article 4 (Hunt for Bugs)

SystemVerilog Has Some Changes Coming Up

ML-Guided Model Abstraction. Innovation in Verification

December 6, 2023February 12, 2024

Webinar: “Navigating our AI Wonderland” … with humans-in-the-Loop?

Webinar: “Navigating our AI Wonderland” … with humans-in-the-Loop?
by Richard Curtin on 12-06-2023 at 8:00 am
Categories: AI, Events, Semiconductor Services, Silicon Catalyst

AI is here, there, and absolutely everywhere – now and forever.

The electronics industry, and the world at-large, have experienced an overwhelming amount of AI coverage this year, with no letup in store for 2024. Both EE Times and Silicon Catalyst have recently staged events around artificial intelligence:

“AI Everywhere” delivered via a series of web sessions

Video Replay

“Welcome to our AI Wonderland” – The 6^th Annual Semiconductor Industry Forum:

(l to r) David French, Moshe Gavrielov, Dierdre Hanford, Ivo Bolsens

Video Replay

Article write-up:

https://spectrum.ieee.org/how-will-ai-change-semiconductors

Although these events covered the fundamental technical and business aspects of AI, the critical societal impacts of AI were only briefly mentioned. As a result, EE Times and Silicon Catalyst decided to team up and host a follow-on event that was held last week, to delve into the “bigger picture” aspects of how AI will shape our lives. Or as Geoffrey Hinton, cited as the godfather of AI stated, “Humanity is at a turning point with AI”.

You can appreciate that today’s coverage of the AI segment is an interesting and rapidly changing storyline and balancing act:

Looking at the safety aspects of AI, and all the issues that come up in terms of the AI-angst generated. Clearly the recent AI-related events are extremely relevant, starting with the pedestrian incident associated with Cruise, the autonomous vehicle company, and also the palace intrigue that took place at OpenAI. What impact will regulatory oversight have on innovation?
On the other side of the scale, one needs to understand the financial impact of AI, in both the private and public markets, for electronics industry investment opportunities. Needless to say, I don’t have to remind everyone about the envy that a lot of organizations and investors (private and institutional) now have about Nvidia’s position in the market; with their tremendous YoY sales growth, > 80% AI processor market share and almost 250% YTD stock price increase.

We encourage you to view the joint EE Times and Silicon Catalyst webinar, to get a sense of our rapidly evolving AI landscape, to understand the current state of our industry and how regulatory oversight and investment decisions need to take into account the impact on humanity. The webinar panel was moderated by Nitin Dahad of EE Times, joined by:

Jama Adams, COO, Responsible Innovation Labs rilabs.org
Navin Chaddha, Managing Partner, Mayfield mayfield.com
Rohit Israni, Chair AI Standards, US (INCITS/ANSI) incits.org

Quoting Navin Chaddha from Mayfield, in his closing webinar remarks:

“I think it’s great time to start a company and do it in a balanced way.

So that you do well financially, but also do good for the world.”

Video Replay

About Silicon Catalyst

Silicon Catalyst is the world’s only incubator focused exclusively on accelerating semiconductor solutions, built on a comprehensive coalition of in-kind and strategic partners to dramatically reduce the cost and complexity of development. More than 1000 startup companies worldwide have engaged with Silicon Catalyst and the company has admitted 100 exciting companies. With a world-class network of mentors to advise startups, Silicon Catalyst is helping new semiconductor companies address the challenges in moving from idea to realization. The incubator + accelerator supplies startups with access to design tools, silicon devices, networking, and a path to funding, banking and marketing acumen to successfully launch and grow their companies’ novel technology solutions.

Also Read:

Silicon Catalyst Welcomes You to Our “AI Wonderland”

McKinsey & Company Shines a Light on Domain Specific Architectures

A Look at the Winners of the Silicon Catalyst/Arm Silicon Startups Contest

December 6, 2023December 6, 2023

BEOL Mask Reduction Using Spacer-Defined Vias and Cuts

BEOL Mask Reduction Using Spacer-Defined Vias and Cuts
by Fred Chen on 12-06-2023 at 6:00 am
Categories: Lithography
2 Comments

In recent advanced nodes, via and cut patterning have constituted a larger and larger portion of the overall BEOL mask count. The advent of SALELE [1,2] caused mask count to increase for EUV as well, resulting in costs no longer being competitive with DUV down to 3nm [3]. Further development by TEL [4] has shown the possibility for further mask reduction, which will be considered in this article.

With the BEOL metal pitch approaching 20 nm, several patterning scenarios can be envisaged. The first case would be EUV SALELE (Figure 1, left). This would entail the use of 2 masks for trenches, 2 masks for blocks (cuts), and 2 masks for vias. The factor of two comes from the two etch “colors” (mutual selectivity) needed to help relax overlay requirements. If this were done by DUV (Figure 1, right), the number of block and via masks would have to double to achieve the same pitch per line or track [3]. Two masks can still be used to define (through an LELE (Litho-Etch-Litho-Etch) sequence) a core pattern upon which spacer-based SADP (self-aligned double patterning) is executed [5]. This leads to 10 masks being used for DUV vs. 6 for EUV, to pattern one metal and one via layer. While there are more steps, the cost still favors DUV [3]. Still, we can check if there is any opportunity to reduce the masking steps.

Figure 1. (Left) EUV SALELE. (Right) DUV LELE + SADP, followed by 2x LELE blocks and 2x LELE vias.

The number of DUV masks for blocking/cutting can be halved by applying SADP instead of LELE. Figure 2 is an abbreviated sketch of the expected flow.

Figure 2. Replacing LELE block with SADP halves the number of required block masks.

The number of DUV masks for the trench layer (line + block/cut) is now the same as for the EUV case. While we now have extra SADP process sequences that need to be designed, the benefit is that energy consumption for DUV SADP is still ~30% less than that for an EUV single exposure [6], while not being expected to be more expensive [7].

Focusing now on via mask reduction, we can apply the SADP replacement of LELE there as well. With SADP being applied to the trench, via, and block layers successively, the etch selectivity of the materials being processed must be considered very carefully. The resulting process step sequence (Figure 3) becomes much more complicated of course, but the end result would be a halving of the via masks (Figure 4).

Figure 3. Example of a process step sequence expected for full replacement of via and block LELE with SADP [8-17].

Figure 4. Replacing LELE via with SADP halves the number of required via masks.

Thus, the mask reduction is carried to its extreme, by greatly increasing the etch complexity. Yet, even without going so far, having extra DUV masks should not be prohibitive in any way.

References

[1] R. Venkatesan et al., Proc. SPIE 12292, 1229202 (2022).

[2] Y. Drissi et al., Proc. SPIE 10962, 109620V (2019).

[3] F. Chen, https://www.linkedin.com/pulse/extension-duv-multipatterning-toward-3nm-frederick-chen

[4] A. J. deVilliers, US9240329; H. Kang, A. J. deVilliers, US10115726.

[5] S. Sakhare et al., Proc. SPIE 9427, 94270O (2015).

[6] L-A. Ragnarsson et al., “The Environmental Impact of CMOS Logic Technologies,” 2022 EDTM.

[7] L. Liebmann et al., Proc. SPIE 9427, 942702 (2015).

[8] Y. Zhang et al., JVST A14, 2127 (1996).

[9] A. Sankaran and M. Kushner, JAP 97, 023307 (2005).

[10] S. A. Vitale et al., JVST B 27, 2472 (2009).

[11] B. S. Kwon et al., J. Electrochem. Soc. 157, D135 (2010).

[12] J. S. Kim et al., JVST A28, 65 (2010).

[13] F. Weilnboeck et al., JVST B 30, 041811 (2012).

[14] S. Dhungana et al., JVST A34, 061302 (2016).

[15] D. Radisic et al., Proc. SPIE 10963, 109630P (2019).

[16] K-C. Chien and C-H. Chang, JVST B 40, 062802 (2022).

[17] N. Miyoshi et al., JVST A 40, 032601 (2022).

This article first appeared in LinkedIn Pulse: BEOL Mask Reduction Using Spacer-Defined Vias and Cuts

Also Read:

Predicting Stochastic Defectivity from Intel’s EUV Resist Electron Scattering Model

The Significance of Point Spread Functions with Stochastic Behavior in Electron-Beam Lithography

Extension of DUV Multipatterning Toward 3nm

December 5, 2023December 5, 2023

Prototyping Chiplets from the Desktop!

Prototyping Chiplets from the Desktop!
by Daniel Nenni on 12-05-2023 at 10:00 am
Categories: Chiplet, EDA, FPGA, Prototyping, S2C EDA

S2C has been successfully delivering rapid SoC prototyping solutions since 2003 with over 600 customers, including 6 of the world’s top 10 semiconductor companies. I personally have been involved with the prototyping market for a good part of my career and know S2C intimately.

S2C is the leading independent global supplier of FPGA prototyping solutions for today’s innovative SoC and ASIC designs, now with the second largest share of the global prototyping market. We all know the benefits of working with an independent company that can focus on the specific needs of prototyping customers so I will skip forward to the technology part of this article.

For prototyping we all read about the scalability of the systems and how many gates are supported. Today hyperscale designs that are in the billions of gates can be prototyped using the latest FPGAs from Xilinx. These high-end prototyping systems are generally housed in a dedicated facility or a cloud.

Not all designs are in the billions of gates however and now that we are entering the chiplet era smaller designs are a focus and that brings us to the new S2C Prodigy Logic Matrix LX2 Mini, an enterprise-class FPGA prototyping solution designed for lab or desktop use.

S2C LX2-M2 Mini and the LX2-P4

Prodigy Logic Matrix Configuration Table

Despite its smaller form factor relative to LX2, LX2 Mini also delivers the same high bandwidth and scalability. Both LX2 and LX2 Mini can leverage S2C Chiplink AXI IP, enhancing partition interconnectivity at up to 100MHz.

Here is a quick video on the S2C Prodigy Logic Matrix LX2 Mini:

Brining the full power of S2C Prodigy Logic Matrix Prototyping to the desktop with the mini series of enterprise-class prototyping will further enable the chiplet market.

Chiplets are like the building blocks of a computer chip. Instead of creating a single, monolithic integrated circuit, chiplets are smaller, individual semiconductor components that can be designed and manufactured separately. These chiplets can then be combined or stacked together to form a more complex and powerful integrated circuit.

The idea is to take advantage of specialized manufacturing processes for different components of a chip. For example, one chiplet might be optimized for high-performance computing, while another might be designed for energy efficiency. By combining these chiplets, you can create a more flexible and efficient overall system.

Think of it like assembling a puzzle where each piece is a specialized chiplet, and when they come together, they create a powerful and cohesive unit.

Verification is a crucial step in the design and manufacturing process of chips, especially in the context of chiplets. Since chiplets are separate components that come together to form a single integrated circuit, verifying their functionality individually and as a collective unit is essential.

Clearly FPGA prototyping chiplets will dramatically speed the verification process and if you are delivering a chiplet to a customer the new S2C Prodigy Logic Matrix LX2 Mini can be sent to your customer’s desktop for close collaboration, absolutely.

Also Read:

S2C’s FPGA Prototyping Accelerates the Iteration of XiangShan RISC-V Processor

ViShare’s Rapid Market Entry with FPGA-Based Prototyping Solution from S2C

Systematic RISC-V architecture analysis and optimization

December 5, 2023December 19, 2023

Building Reliability into Advanced Automotive Electronics

Building Reliability into Advanced Automotive Electronics
by Bernard Murphy on 12-05-2023 at 6:00 am
Categories: AI, Analytics, Automotive, proteanTecs

Those of you who have been in the industry for a little while will remember that the recipe for reliable electronics in cars (and other vehicles) used to be simple. Stick to old (like 10 years old) and well-proven processes and tweak rather than tear up and restart well-proven designs to the greatest extent possible. Because incrementing from a well-characterized base should ensure that reliability and other KPIs will not drift too far from expectations.

That recipe went out the window when we demanded that our vehicles turn into phones on wheels, offering ADAS, autonomy, advanced infotainment, requiring state of the art processes and architectures. Throwing out the rulebook gets us all the functionality; however, we don’t expect our phones to be ultra-safe or work reliably for 20 years or more. How do we bridge the gap between all the technology goodies we want and our safety and durability expectations?

proteanTecs recently hosted a webinar I rate a must-watch on this and related topics. Packed with information and informed opinion, it measurably increased my understanding of challenges and directions towards bringing high reliability to advanced technologies. More generally it helps build greater understanding of the need for electronics lifetime monitoring and adaptation. Participants were Heinz Wagensonner (Senior SoC designer at Cariad, the automotive software branch of Volkswagen), Jens Rosenbusch (Senior Principal Engineer, SoC safety architecture at Infineon), Robert Jin (Automotive safety architect at NXP), Gal Carmel (Senior VP/GM for automotive at proteanTecs), and moderator Ellen Carey (Chief External Affairs Officer at Circulor).

What Auto Reliability Means Today

One aspect of enhanced reliability is in fail-safe or fail-degraded systems. Real systems can and will fail. Acknowledging this reality, when a system is failing or expected to fail, a redundant system can take over or the system can fall back to reduced functionality, still safe enough to allow the car to limp home or perhaps to the side of the freeway. This reasoning is already well understood, though is expected to be applied more widely in future designs.

Another aspect – the subject of this webinar – recognizes that high reliability cannot be assured in a system which fails to evolve over time. Devices age, use-cases change, the environment changes, and feature capabilities will be upgraded. Few of these changes can be accounted for in the t=0 (product release) system. Systems must become intelligently self-monitoring, responding in part through locally determined adaptation but also through a feedback loop to a central resource which can synthesize broader learning for dissemination back to vehicles.

In short, for continued high reliability in these advanced systems, closing the spec for t=0 is only the start. You move to Arizona (hot) and your daily commute doubles. You are now pulling a trailer and have downloaded a software upgrade to your vehicle (now 10 years old) which promises to improve your range (ICE or EV). The “spec” keeps changing yet reliability plus safety must continue to measure up to the highest standards. This demands in-system and in-circuit monitoring through embedded sensors for workload, temperature, voltage, interconnect, and delay monitoring (for example) together with on-board ML-driven intelligence to interpret that data. This should capture not only immediate problems but also anomalous signatures which might indicate the beginning of a future problem. Allowing us to supplement now routine safety mitigations with the beginnings of predictive maintenance.

What constitutes a problem or a suspicious signature depends on mission profiles. One size does not fit all, for example a robotaxi, a city business vehicle, a personal car in the city or in rural use, will have different profiles. An important aspect of profiles will be factors affecting power: voltages and frequencies for example. Lowering power improves thermal reliability of course but will also extend range in an EV, also a positive for reliability.

Profiles can’t be programmed into a product at release, not least because we have no idea (yet) what those profiles should be. The t=0 spec must somehow accommodate the full range of possibilities, which designers accomplish through margins, margins everywhere which is expensive. In use, it will become clear for a certain profile that some margins can be tightened, whereas others perhaps should be loosened. Intelligent systems can learn their way to profile optimization, even better if they can share data with other cars.

From Theory to Practice

Naturally proteanTecs plays an important part in this solution. During chip design, they build and insert low impact agents, guided by detailed analysis, into the design to assure high coverage data in use. Working in partnership with proteanTecs, NXP have written a paper which became a driver for the ISO/TR:9839 standard on predictive maintenance. This is expected to fold into or alongside the next rev of the ISO 26262 standard.

This method for capturing and utilizing in-use behaviors is a starting point, however all participants agree that the next interesting/challenging step to derive full value is to collaboratively share this data, certainly within a brand, even across brands for common subsystems, say for engine and braking. Complementary value could be found in considering reliability of total system (the car) rather just individual component or subsystems. In both cases there is rich potential for AI to detect signature patterns in this collective data, patterns which perhaps appear only in multi-factor correlations that we would find hard to detect ourselves.

Sharing data is always a tricky topic these days. Since the types of data discussed here is relatively low-level, I would think so privacy concerns may not be as big an issue as brand competitive concerns. All panelists agreed on the need to build an ecosystem together with regulatory bodies to develop and support standards in this area.

There were several other interesting points raised. Will Tier1s disappear as OEMs build their own silicon? (no). How will this approach simplify analysis for field failures? (massively). Can chiplets help with reliability? (Maybe in the next decade after multi-die system reliability has been proven to automotive expectations for temperature, vibration and humidity).

Watch the replay for more detail on all points.