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EDA Company Selected as One of the Fastest Growing Companies in North America by Deloitte’s 2011 Technology Fast 500™!?!?!?!

EDA Company Selected as One of the Fastest Growing Companies in North America by Deloitte’s 2011 Technology Fast 500™!?!?!?!
by Daniel Nenni on 10-31-2011 at 11:07 am
Categories: EDA

Wow! We always hear semiconductor companies complain about the lack of innovation amongst the EDA leaders. Placing high on the Deloitte 500 list shows that innovation is alive and well in EDA and it IS possible to have a meaningful impact regardless of your overall size. It is worth noting that there are very few EDA companies that have ever won this award.

The Deloitte’s 2011 Technology Fast 500™ is a ranking of the 500 fastest growing technology, media, telecommunications, life sciences and clean technology companies in North America. The winners are selected based on percentage fiscal year revenue growth from 2006 to 2010. During this period, Berkeley Design Automation’s revenue grew 787%, while its customer base grew to over 110 semiconductor companies worldwide.

There are more and more pain points cropping up as our customers try to close the gap between circuit design and actual silicon performance at ever-shrinking process nodes. Physics and statistics are becoming critical to understand electronics. The focus at BDA is on those problems that arise when analog, mixed-signal, RF, and custom digital circuit content grows rapidly. Technology that is directly targeted to solve these pain points, together with knowledgeable application expertise, timely responsiveness to customer issues, and the right business models are the key ingredients behind the company’s rapid revenue growth.

It is an incredible honor for BDA to win this prestigious award. It validates their mission, strategy, and execution in solving some of the newest and most difficult problems for semiconductor design teams. BDA is widely recognized for its technology leadership via its Analog FastSPICE™ Platform and its growing market share in the electronic design automation industry. Berkeley Design Automation is the only EDA company selected for this year’s ranking.

Ravi Subramanian, Berkeley Design Automation’s chief executive officer, credits the company’s incredible revenue growth on the combination of the:

  • Industry’s rapid move to nanometer mixed-signal design starts
  • Company’s breakthrough verification technology
  • Collaboration with key customers and partners
  • Widespread customer success with this new technology

“This is a prestigious honor for Berkeley Design Automation, and we would like to share this honor with our customers. Our stellar team, strong technology base, innovative products, outstanding customer focus, and execution discipline have helped ensure our strong and consistent year-on-year revenue growth, even as we faced challenging economic times. I would like to thank our customers for fueling this growth via the strong demand for our products.”

Berkeley Design Automation, Inc. is the recognized leader in nanometer circuit verification. The company combines the world’s fastest nanometer circuit verification platform, Analog FastSPICE, with exceptional application expertise to uniquely address nanometer circuit design challenges. More than 100 companies rely on Berkeley Design Automation to verify their nanometer-scale circuits. Berkeley Design Automation has received numerous industry awards and is widely recognized for its technology leadership and contributions to the electronics industry. The company is privately held and backed by Woodside Fund, Bessemer Venture Partners, Panasonic Corp., NTT Corp., IT-Farm, and MUFJ Capital.

For more information, visit the BDA landing page on SemiWiki:

http://www.semiwiki.com/forum/content/section/256-berkeley-design.html

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TSMC ASIC versus IBM ASIC!

TSMC ASIC versus IBM ASIC!
by Daniel Nenni on 10-30-2011 at 3:00 pm
Categories: Uncategorized
6 Comments

Lunch with Jim Lai, President of Global Unichip(GUC), was the highlight of my week, I had a very nice crab cake salad. As you may have read, GUC announced itself as the “Flexible ASIC Leader” taking direct aim at the traditional ASIC market led by the likes of IBM, ST Micro, TI, Renesas, and Samsung. This will be like “shooting fish in a barrel” for two very simple reasons: 28nm/20nm design challenges and the incredibly complex IP and packaging that goes with it!

  • Established in 1998
  • Headquartered in Hsin-chu Science Park
  • IPO on TSE (symbol: 3443), 2006
  • Largest shareholder is TSMC, current share 36%
  • Worldwide presence: US, China, Europe, Japan and Korea

After my time as Director of Strategic Foundry Relationships for Virage Logic, I spent two years with the eSilicon and Virage sales teams in Silicon Valley. My theory was that IP was key to competing in the ASIC market so combining the two would be a perfect fit. My vision was for eSilicon and Virage and to merge and create an ultra competitive ASIC company which of course did NOT happen but I digress……

The New GUC provides superior domain-specific design flows and a comprehensive IP portfolio, melded through an unparalleled bond with the manufacturing leader, to forge our uncompromising ASIC capabilities.

During this time I identified 200+ fabless semiconductor companies in Northern California and profiled them based on product application, EDA methodology, IP, foundry, process node, etc…. I also attended weekly eSilicon and Virage Logic sales meetings to document why business was won and lost. Bottom line, IP absolutely was a key differentiator in why eSilicon lost to the ASIC guys, including GUC.

GUC provides an unmatched combination of advanced technology, low power and embedded CPU design capabilities and production knowhow through close partnership with TSMC and major 3D IC packaging and testing companies that are ideal for advanced communications, computing and consumer electronics ASIC applications.

Process technology is also now a differentiator since the ASIC guys have all but given up their fabs. TSMC has the only yielding 28nm processes, so which ASIC company has the inside track at TSMC? Well that would be GUC. The eSilicon guys often complained about the unfair advantage GUC had being the child of TSMC. When I relayed this story to Jim Lai he responded, “Yes, of course that is true!” GUC HQ in Taiwan is right across the street from TSMC Fab 12. TSMC executives are in Fab 12, including Dr. Cliff Hou, Vice President, Design and Technology Platform at TSMC, who is on the GUC board of directors.

GUC is the Flexible ASIC Leader that communications, computing and consumer electronics companies turn to when low power AND high performance ASICs are “a must have.” The company provides superior domain-specific designflows and a comprehensive, proven IP portfolio, melded through an unparalleled bond with the manufacturing leader, to forge our uncompromising ASIC capabilities.

GUC may live in the shadow of TSMC but with 500+ employees worldwide, 100+ customers, and 2010 revenue of $327M, they are casting a much larger shadow on the traditional ASIC industry. It will start at 28nm and finish in 20nm, Global Unichip Corporation will be the number one ASIC company worldwide, believe it! I have been invited to GUC HQ during my trip to Taiwan later this month and I’m really looking forward to it!


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What’s New with Semiconductor Test and Failure Analysis at Mentor?

What’s New with Semiconductor Test and Failure Analysis at Mentor?
by Daniel Payne on 10-28-2011 at 6:03 pm
Categories: EDA, Siemens EDA

ISTFA
Silicon Valley is a great location for trade shows and technical conferences, so if you have an interest in test and failure analysis then don’t miss out on the 37th annual International Symposium for Testing and Failure Analysis. This year ISTFA will be held from Sunday, November 13th thru Thursday, November 17th in San Jose at the McEnery Convention Center.

I’ll never forget the first DRAM design that I worked on because we had a few percent yield issue caused by electromigration. I could look at my DRAM chip under the microscope and vary the VDD supply until an aluminum wire would start to bubble, melt and evaporate before my very eyes.

You can visit all of the exhibitors on Tuesday and Wednesday, November 15-16.

  • New Tutorials including: Construction Analysis and Reverse Engineering, Package FA, Chip Access and Repackaging,
    Delayering Techniques, Photovoltaic FA

  • Technical Sessions including Counterfeit Electronics and Renewable Energy
  • Technology-Specific User Groups include: Package and Assembly FA, 3D and Finding the Invisible Defect
  • Panel Discussion “…But How Does One Find an ‘Invisible’ Defect?”
  • Pre- and Post-Conference Education Short Courses
  • North America’s Largest FA-Related Industry Show
  • Exhibitor AfterHours Demonstrations
  • Unlimited Networking Opportunities
  • Significant Early-Bird and Housing Discounts

Mentor Graphics
New in 2011 is a cell-aware flow where you can have user-defined fault models (UDFM) to generate test patterns for cell internals.

Dave Macemon has written a White Paper on this topic of UDFM.

Another new area for Mentor in 2011 is DFM + Yield analysis. For ramp-up of a new design you need to quickly identify the fundamental cause for low yield. The Tessent YieldInsight® tool gives you statistical analysis and data mining that work along with Tessent Diagnosis. With these tools you can identify the likely source of systematic defects prior to physical failure analysis.

These approaches could save you days or weeks of effort.

To register for after hours demos (by invitation only) Tuesday, Nov 15 from 5:45 pm – 7:15 pm, send email to: silicon_test@mentor.com

Also, to get your free expo pass for the conferencesimply enter MEN102as your promo code here.

More Details
Here’s where to get more information about the ISTFA 2011 Conference and Exposition.

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Xilinx and Altera’s Summer At The Beach

Xilinx and Altera’s Summer At The Beach
by Ed McKernan on 10-28-2011 at 11:01 am
Categories: FPGA, Xilinx

The “old saw” is “To Sell in May and Go Away.” It’s a Maxim that particularly applies to semiconductor stocks as they typically drop from a post April earnings peak through the summer doldrums to a late September nadir only to be revived in the prelude of October earnings. It has happened again this year, although the path taken by the various big semiconductor players was quite different. In particular, the highly profitable, seemingly unstoppable Altera and Xilinx were coasting along until mid July when their fait was sealed by the Financial shenanigans of the US and Europe Governments. More than other semiconductors, their revenue faucet appears to turn hard off when sovereigns play chicken and the bank dominoes tip over. No bank financing, economy stalls.

August means the Hamptons and Martha’s Vinyard for the stressed out Wall St wizards and the White House Family. Instructions are usually left at the office to never disturb the sun tanners, unless it’s absolutely the end of the world. If the US government had just spent a $100 billion less these past 3 years – which works out to less than 1% of the overall budget, Obama wouldn’t have had to pick a budget fight with Boehner until the Fall and the S&P wouldn’t have downgraded the US Debt in early August. And if the Greeks would just raise the retirement age a couple years, the Europeans would have been able to kick the can down the road until the cold of winter reminds the Germans why they desperately need Greece after all is said and done.

No with great synchronicity that one could swear was a conspiracy, the financial geniuses decided that the first weekend in August was to be the line in the sand. It worked to perfection, the banks swooned and so the big communications equipment vendors like Ericsson and Alcatel Lucent broke the “In case of Fire” Glass to implement the plans they should have had ready back in September 2008. Back then, nobody thought the experts would actually take the financial system over the cliff. Sitting on FPGA silicon inventory that rots while sales stalls out is not a plan that companies like Ericsson and Alcatel Lucent and Huawei etc can live with for long. The everyday cash flow paying salaries, rent and the electric bill quickly consume what remains in the bank. And so purchasing gets a call from the CFO to cancel all open orders and return to distributors what is not soldered on a PCB until all is clear.

Altera and Xilinx reported stunning drop-offs in revenue for Q3 of 5-10% sequentially. In addition, they forecast Q4 2011 will see another sequential drop of as much as 8-11%. In terms of drop-offs this is as bad as it gets without being 2008. And yet the morning after the earnings call, all was forgiven as analyst cheered seeing lights at the end of the tunnel. Altera and Xilin’s stocks have been on an absolute tear, because no one on Wall St. wants to be late to the party when the whisper goes out “Customers have come back, Book-to-Bill is much greater than 1.”

It has been such a treat to observe the comedy of errors of Wall St. analysts writing opinion pieces quarter after quarter of the great FPGA inventory bubble about to burst while Altera’s stock tripled and Xilinx’s more than doubled. This months earnings season was about Xilinx and Altera finally confessing that they had hit a wall, albeit one not of their own doing. No matter, sins were confessed, absolution delivered and the stocks have been anointed. For now the Wall St. analysts can go back to their bosses and claim “See, I was right, the FPGA guys were overbuilding and they just entered an inventory correction.” My sense is that the big traders have stopped listening to Wall St. analysts.

What does the new economic environment of stop and go sovereign debt crises mean for Altera and Xilinx. It means we will probably see more oscillation in their revenue, however margins will still be strong, they didn’t budge this last quarter. Xilinx and Altera, unlike other semiconductor companies have very long revenue tails so inventory doesn’t go to waste. Secondly, both players have discovered that lost revenue in the short term is eventually made up in the long term with revived orders and with new products. Every new process node they seem to ratchet up prototype ASPs, which boosts margins as well. No need to cry for Altera and Xilinx, but I will remind myself that every debt crises presents an opportunity.

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Think differentiation

Think differentiation
by Paul McLellan on 10-27-2011 at 5:01 pm
Categories: EDA, Siemens EDA

Wally Rhines’s keynote at the ARM TechCon was about differentiation and how to use it to create measurable value. We all know what differentiation means in some intuitive sense, but how do you make it measurable? Wally’s answer was that differentiation is a measure of the difficulty of switching suppliers and is best measured by the gross profit margin (GPM). It doesn’t really work for pure software products because of the accounting rules we are forced to use, but it is fine if the software is embedded in something (think a smartphone).

The alternative to differentiation is commoditization, where the products are interchangeable and compete only on price. Sometimes this is quite deliberate (think DRAM) and sometimes it happens despite the companies involved trying to unsuccessfully to differentiate (think PCs).

Sustainable differentiation depends on the three-legged-stool of product, infrastructure and ecosystem, each more difficult for a competitor to create. ARM is actually a good example. They don’t have a monopoly on good processor design but they have done a good job of creating the infrastructure of compilers etc that are required to make a processor usable. But where they excel is in the number of partners that they have built into an ecosystem around the ARM processor families, ranging from cell-phone manufacturers, to semiconductor partners, RTOS suppliers and many other categories.

So once something is commoditized is it possible to escape from the pit. Wally’s example was bottled water. It sells for 30,000 times the price of a glass of tapwater, although it is basically the same product. And how big is that market. Embarrassingly, it is 13X the size of the EDA market at $65B. However, I’m not sure that this is really a good example of a product where differentiation is measured by the difficulty of changing suppliers. To switch from Evian to Calistoga doesn’t have a lot of switching cost.

So what about semiconductors? Where is the differentiation? The most differentiated (based on GPM) is FPGA, followed by analog. Memories and discretes bring up the rear.


FPGAs fit the three-legged-stool model where there is product (FPGA itself), infrastructure (tools) and an ecosystem. Once you have a piece of IP working on, say, Xilinx then it is pretty certain that the next product in that family will be on Xilinx too. Why requalify it on Altera when the underlying product (the FPGA itself) isn’t that much different. And at the other end of the scale, memories are pin compatible and switching is easy. Indeed many manufacturers use multiple sources anyway (for example, the teardowns of the latest iPhone seems to have Samsung memory chips in the A5 SoC in the US, but Elpida in Europe).

Foundry looked at as a group has low GPM too. But that hides what is really happening which is that TSMC has margins in the 50% range (and increasing) whereas the other foundries struggle around 20%. Again this partially reflects the strong ecosystem that TSMC has built up around its processes with IP and reference design flows.

Wally had an interesting chart listing the semiconductor companies not by their revenue but by their gross margin. Linear Technology leads the pack with 77%, followed by Altera, PMC-Sierra, Nationa, Qualcom, Silicon Labs, Intel, ADI, Xilinx and Conexant. Analog, FPGA and microprocessors.

Going forward Wally reckons that there will be less differentiation by process, the traditional edge for a semiconductor company, and more for design. The infrastructure will be build around proprietary IP. For everyone except Intel I think I’d agree but Intel being a process generation or two ahead of everyone else gives them differentiation even where their design is not the best.

But how to build an ecosystem?

First, luck with good followup. Both ARM and Intel have done this, riding the cell-phone and the PC industries when they took off. They were in the right place at the right time but then executed very well.

Another approach is to sacrifice a key capability as Adobe did with Acrobat. Give up the revenue from Acrobat Reader. Or IBM did with the PC by their extreme openness (although they rather screwed that one up: a company with the best semiconductor technology, a great RISC processor, world-leading operating system developers gave all the money to Intel and Microsoft).

TSMC in the early days had a problem. They were second sourcing designs that were made to run in different fabs and different processes so constantly had to tweak their fab to get good yield. So they took their design rules, traditionally the biggest secret in any semiconductor company, and published them. At VLSI/Compass we created libraries and sold them so suddenly people were doing designs directly in TSMC’s process and all that design tweaking went away.

So there you have it. GPM is the best measure of differentiation, also driven by the difficult of switching. And the hardest thing to reproduce for a competitor is an ecosystem.

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AMS Design using Dongbu HiTek foundry and Tanner EDA Tools

AMS Design using Dongbu HiTek foundry and Tanner EDA Tools
by Daniel Payne on 10-27-2011 at 12:00 pm
Categories: EDA, Tanner EDA

Every analog designer needs a foundry PDK (Process Design Kits) and EDA tools to design, layout and verify their AMS chip or IP. This week I had a chance to conduct an email interview with Taek-Soo Kim, VP of Technical Engineering at Dongbu HiTek in Korea. This specialty foundry supplies analog silicon worldwide.

Interview
Q: Tell me about your background and how long have you been at Dongbu HiTek?

A: I have been in the Semiconductor industry for 26years. My main experience is in EDA, developing tools, setting up design methodology during first 15 years. Then I was responsible for design services operation in ASIC biz. Now I have been with Dongbu HiTek for 4 years and main responsibility is all design infrastructure.

Q: How long have Dongbu HiTek and Tanner EDA been working together on PDKs?

A: We have been working with TannerEDA for 2 years now. We started with 0.35um BCD process PDK and then worked on 0.18um BCD node.

Q: What was the deciding factor to make the PDK for the BD180LV process (instead of the Medium-High Voltage, Ultra-High Voltage or Analog CMOS)?
A: Main reason is that this process happened to be the one our customer selected to use.

Q: Can you mention your first Tanner EDA customers that are using this PDK?

A: Unfortunately, we cannot disclose the name of this customer.

Q: Can you mention the end-product or industry that the first customers are using this PDK for?

A: DC-DC converter

Q: What other PDKs do you create ?

A: Cadence, Mentor, Synopsys, SpringSoft, iPDK

Q: How would you compare the effort of creating the PDK for Tanner EDA versus other PDKs?

A: For the first project that was done on 0.35um node, Tanner EDA engineer needed to get used to Dongbu HiTek technology. So, there was many communication going back and forth, but as things progress, thing got better.

Q: What would be the next PDK project that you will work with Tanner EDA on?

A: Plan to work on 60V extension of 0.18um BCD process.

Q: What do you like most about working with Tanner EDA?

A: Since Tanner EDA is not a big company, they are very active and shows very quick response.

Q: At the 180nm node about how long do most customer designs take to go from concept to tape-out?

A: within 6 month

Q: How many silicon re-spins does it take on average for your customers to get silicon designs ready for volume production?

A: Different on case by case but, on the average approximately 1 year.

Q: What is your Analog technology roadmap?
A:

Q: What is new between Dongbu HiTek and Tanner EDA?
A: We just announced a foundry-certified 0.18 micron Analog CMOS PDK.

Q: When did Dongbu HiTek first offer the 0.18 micron node for analog designers?
A: Back in June 2008.

Q: What is unique with the BD180LV process node?
A: It has many analog components to choose from and can operate above 5V. This process has bipolar transistors as well for high performance power devices.

Q: In my PDK for Tanner EDA tools what do I get?
A: You get schematic symbols, simulation models, layout rules and verification structures.

Summary
Users of Tanner EDA tools are all set to design and fab with Dongbu HiTek for their analog and mixed-signal IC designs. PDKs for the 0.18 micron node and 0.35 micron node are ready now and more nodes are planned.

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Interview with Eric Esteve IPNest made by Synopsys

Interview with Eric Esteve IPNest made by Synopsys
by Eric Esteve on 10-27-2011 at 11:15 am
Categories: IP, Synopsys

Introduction from Hezi Saar: Eric’s latest viewpoints and reports are host onIPnestas well as on Semiwikiand you can find information related to various Interface IP: USB 3.0, PCIe, SATA, DDRn, MIPI, HDMI and more.

Q: Eric, give us a quick introduction about your background as it relates to interface IP
A: I have spent 20 years working as a designer, then FAE, then Marketing for TI and Atmel, before working as a WW Marketing Director for PLDA, where I have launched their PCIe Controller IP.
Working day to day in marketing for Interface IP, I was missing key information about the market size and trends, the vendors, and so on. Thus, when I have started IPnest, three years ago, I have decided to focus on the Interface IP market, and to provide comprehensive market surveys dedicated to IP for USB 3.0, PCIe, SATA, MIPI, DDRn etc… Now, I can say that IPnest is the leader analyst in this niche segment. IPnest has customers all over the world, the list includes: Sony, Inventure, KSIA, Cadence, Cast, Evatronix, PLDA, Rambus,Mentor Graphics, Arasan, Denali, Snowbush, MoSys, Mixel, Intel, Fujitsu, LSI Logic, nSYS, HDL DH… and Synopsys!
Q: What are your high level thoughts about the semiconductor industry in general and mobile segment in particular?
A: The semiconductor industry is still growing, with an 8% CAGR for the last 20 years or so, but it is a matter of fact that there is a consolidation, and the ASIC or ASSP design starts are slightly declining. Along with this decline, we can see two major trends: the production level per ASIC are growing, and even more important, the chip complexity (gate count, number of functions) is increasing. If you look at the mobile segment, taking for example the latest platform from TI, OMAP5 (see: blog) you realize that this device is extremely complex.

The chip architecture is based on no less than FIVE CPU cores, related Cache Memory, and several dozens of IP functions, including a “shopping list” for the major Interface IP (several USB 2.0, USB 3.0 OTG, SATA 2.0, HDMI 1.4, LPDDR2 by 2, almost all MIPI specification: CSI-2, CSI-3, DSI, LLI, HSI…). Such a design start is probably equivalent, in terms of design power, to a dozen of ASIC design starts in the 2000. So, yes there are less design starts, but these are in general more complex designs, especially for applications like Wireless Smartphone or Set-Top-Box. In fact these are so complex than the only way to comply with the time to market requirements is to massively rely on design reuse, or IP.

Q: What do you believe are the challenges facing the mobile electronics industry?
A: Eventhough I have worked for TI for 7 years, I am not necessarily an expert of the mobile electronic industry. I think some of the challenges the mobile electronic industry is facing are almost the same than for the other electronic segments: at first, close the “design gap”, which means design chips larger and larger, but with almost the same headcount and design resources and do it when always using the most advanced technology nodes (today 28nm and tomorrow 22nm). These needs push to use the latest techniques, like Design For Manufacturability keeping in mind the huge production volumes expected with a single device, ASIC or ASSP. The requirements which are unique to the Wireless industry are: how to design always more complex application (like 3D Video) keeping the system battery life long enough and try to meet the incredible Time To Market for handset applications, which is probably the more stringent of the industry: on the end user market, the typical delay between two product launch from the same OEM is about 6 months, which is not the delay from concept to engineering samples which is much larger, but obviously push for a design cycle as small as possible, for product being incredibly more complex!

Q: You raise a very interesting point, what is a typical design cycle for SoC targeting mobile electronics (From concept to tape-out and to engineering samples)?
A:see above

Q: Since you (and Synopsys) are focused on interface IP what do you see as the overarching trends for interface IP?
A: Being strongly focused on Interface IP, since 2005, I have seen the massive adoption of the differential, high speed, serial communication techniques inside and outside the box (whichever is “the box”). This has been true for PCI Express replacing PCI, initially at 2.5 Gbps now up to 8 Gbps, for SATA replacing ATA at a speed moving from 1.5 up to 6 Gbps. Outside the box, HDMI is now a standard used in PC, Consumer and Wireless handset and USB is –finally- closing the gap and moving to 5 Gbps with USB 3.0. Amazingly the Memory Controller Interface and memory devices is still based on parallel communication, even if this physical interface is at the edge in terms of feasibility with 3200 Mhz for the DDR4. I don’t know when this interface will move to the same type (high speed, differential, serial) like the other, but I don’t see how it could stay the exception in the future! This will probably be the next “hot topic” for the Interface IP market.

I am also watching closely the different MIPI Interface specifications, as using a standardized communication technique in the mobile industry certainly makes sense, not only from a technical point of view but also as this is a more rational approach.

Q: Which are the most promising interfaces for used semiconductor SoCs targeting mobile market segments and why?
A: Lets take TI’s OMAP5 an an example, we have pretty much the list of most promising interfaces for Application Processor SoC targeting mobile market segments:
· LPDDRn to access external DRAM
· USB 2.0 and USB 3.0 if you want to exchange data with your system, as well as for battery charging.
· HDMI when you want to display video with the system being the source.
· SATA has been freshly introduced, that you will use when you want to store data coming through the system on an external SSD
· MIPI functions, the list of supported specifications is long:
· LLI/uniport to interface with a companion device or/and with a Modem in order to share the same external memory and save a couple of $ on each handset
· CSI: to interface with one or more cameras, one or more CSI-3 and CSI-2 function
· DSI or Display serial interface
· SlimBus, a low performance, serial, low power interface with Audio chips
· UFS: MIPI Interface for mass storage devices

There are also other Interfaces (UART, SDIO and a lot more) which are used in Mobile, as well as in other segments, that I would qualify of being part of a second type, which can be reused internally or acquired through an IP vendor, for a fraction of the price of the above listed interfaces. If we look at the market for the “first type” Interfaces IP listed above, we can see that it is expected to grow up to almost $500M by 2015.

This is the end of Part 1… not the end of the interview. More to come later!

Eric ESTEVE from IPNEST

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Parasitic Extraction—My Head Hurts!

Parasitic Extraction—My Head Hurts!
by glforte on 10-27-2011 at 10:08 am
Categories: EDA, Siemens EDA

By Carey Robertson, Director of Product Marketing, Mentor Graphics

IC physical verification requires a number of different types of checking, the most familiar being design rule checking (DRC), layout vs. schematic (LVS) checking, and parasitic extraction combined with circuit simulation. Fundamentally, it does not matter whether you are designing an analog, digital or memory circuit, and it does not matter if you are at the cell, block or full-chip level, you still have to meet the manufacturing requirements for that particular process, and you still need to verify that your logical representation matches your physical design. While EDA vendors have been successful in providing DRC and LVS platforms that can address all these different design styles and flows, parasitic extraction, on the other hand, does not fit well into a “one size fits all” solution.

Because extraction is a “means to an end,” you first need to consider what “end” you are trying to address, which means understanding what circuit simulation task would you like to perform. That simulation goal may be timing, noise analysis, signal integrity, IR drop, clock tree analysis, or some other static or dynamic simulation. Next, you need to factor in the design style (memory, analog, RF, digital ASIC, custom digital, SoC, cell libraries, etc.) and the abstraction level (transistor-level, cell-level, block-level, full-chip). One additional point to consider is that extraction models also vary substantially by process node, because as critical dimensions drop below 65 nm, the underlying electrical characteristics are increasingly sensitive to the interactions among adjacent devices. Once all of those criteria are defined, then you are ready to set up the parasitic extraction tool.

But wait, there’s more! As with any engineering problem, there is the standard tradeoff between performance and accuracy. How accurate do your results need to be, and how long are you willing to wait to attain that level of accuracy? What CPU resources are you able to utilize? What frequency are you running at, and do you need to consider all RCLK parasitics or a subset? This accuracy/performance tradeoff applies to downstream simulation as well. A very accurate simulation may require a very detailed netlist. As the detail and complexity of the netlist increases, so will turnaround time (TAT) of the subsequent simulation. Therefore, understanding netlist size and what level of parasitic reduction to apply is critical.

Does your head hurt yet? Does this decision matrix seem a bit daunting?

As you can imagine, the industry has evolved to the point where we have different extraction tools, engines, flows, and sub-flows to address the specialized solutions for both extraction and simulation. The problem is that having so many specialized tools incurs designer overhead (aka headache): higher learning curve costs, more effort to set up tools for multiple scenarios, and various data and use model mismatches.

What extraction users need is a very flexible and intelligent extraction environment that can adapt to all of their requirements with minimum effort. While there may be different models, engines, and data formats “under the covers,” users would prefer to access these capabilities and options through a uniform, parameterized interface, with the ability to easily adjust tradeoffs (such as speed and accuracy) to give them the best overall solution for their immediate needs. Such an environment should not require users to duplicate setup work, such as creating multiple rule decks when switching from one design style or from one node to another. For example, designers might want to do a “quick and dirty” extraction run to check block interconnects, then later refine accuracy on specific critical nets. . Ideally, this would be accomplished without extra setup time or redefining inputs and outputs.

Imagine a set of golf clubs—that’s how extraction should perform. Good golfers tell me they swing each club the same way and let the club do the work (this doesn’t work for me, but that’s what I’m told). In golf, the golfer considers several variables, such as desired height, desired distance, ball position, etc. From there, a club selection is made to meet those requirements. Every club has the same user interface, so the golfer does not have to learn new techniques for each club, but simply employs the same tried and true methods to be successful (If you don’t believe me, it does work well on TV). That’s the use model we should strive for in parasitic extraction, where the user considers the desired outcome first, then selects the best engine or mode of extraction to match that outcome. It should not require learning several new tools.

Click here for more on parasitic extraction.

About the Author
Carey Robertson does a hit a golf ball from time to time. When he is not out losing golf balls, he is the Director of Product Marketing for Calibre’s Circuit Verification product line (LVS, PERC, and Parasitic Extraction products). He has been with Mentor Graphics for eleven years in various product and technical marketing roles. Prior to Mentor Graphics, Carey was a design engineer at Digital Equipment Corp., working on microprocessor development. Carey holds a BS from Stanford University and an MS from UC Berkeley.

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ARM TechCon 2011 Trip Report and Sailing Semiconductors!

ARM TechCon 2011 Trip Report and Sailing Semiconductors!
by Daniel Nenni on 10-26-2011 at 9:37 pm
Categories: Arm, Cadence, IP, Siemens EDA, TSMC

This was my first ARM TechCon, they cordially invited me as media, but it certainly was not what I expected. Making matters worse, I had literally just flown in from a very long weekend sailing in Mexico which was much more interesting and certainly made me much less tolerant of sales and marketing nonsense. My Uncle Jim lives on a sailboat which is currently in Mexico for the Winter. I’ve sailed on the Esmeralda before but she has just been sold so this was a momentous occasion. Uncle Jim has some health issues so he will be a land locked for the rest of his days. Sailing up and down the Coast is very hard work, believe it!

On the semiconductor side, sailing has come a long way since Esmeralda was first launched. The marine electronics available today are amazing and the ability to run those low-power semiconductor devices via the wind and sun is simply incredible. There should be an ARM Inside sticker on every sailboat! Even the shower is 100% solar and let me tell you that water gets hot! Esmeralda can also desalinate saltwater faster than we could drink it! As the picture suggests we were 3G enabled so, yes, I sailed the internet! Uncle Jim did his best to keep Esmeralda up to date but now technology moves much faster than he can.

I chose Tuesday for ARM TechCon to see the keynotes by TSMC’s Dr. Shang-Yi Chiang, my favorite EDA CEO Dr. Wally Rhines, and Cadence Sr VP Dr. Chi-Ping Hsu. Somebody from the conference called me tonight (Wednesday) and asked why I didn’t attend. Well, you gave me a one-day pass that’s why! But seriously, why the strong ARM tactic? The place was jam PACKED with semiconductor professionals. Having 99.99% market share must be nice!

Shang-Yi’s presentation was similar to the one at OIP last week which I blogged about HERE. According to Shang-Yi, the biggest problems to face the semiconductor industry in the years to come will be more economic than technical, citing the increasing costs of wafers as geometry decreases and density increases. He also stated that FinFets will keep semiconductors scaling through the 14nm and 7nm nodes. I certainly hope he is right. I have 4 kids to put through college.

Wally’s presentation was again by far the best. I expected a rehashed version of his OIP speech, “Accelerating Innovation Through Collaboration” which I blogged about HERE, but no, he pulled out another excellent presentation, “Creating Measurable Value Through Differentiation”. Every CEO in the semiconductor ecosystem should memorize this one! Why have I not seen any press on this? SemiWiki blogger Dr. Paul McLellanwill did a more thorough blog on it HERE.

Chi-Ping’s presentation was the biggest disappointment, I actually walked out. I know Chi-Ping from the Avanti days and can tell you that material did not come from him. Cadence marketing people clearly possessed him with infomercials and all! He even mentioned EDA360!?!?!? Richard Goering’s blog on it, “ARM TechCon Address: High Stakes at Low Process Nodes” was much better than the presentation itself.

ARM did not feed the media but thankfully Jim Lai, President of Global Unichip, invited me to lunch so I did not starve. I will blog about our lunch conversation this weekend but let me tell you this, the semiconductor design ecosystem is about to change once again!

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Synopsys Journal, now on Itunes

Synopsys Journal, now on Itunes
by Paul McLellan on 10-24-2011 at 9:42 am
Categories: EDA, Synopsys

Synopsys Journal is a quarterly publication for management dedicated to covering the latest issues facing designers today. It has been published now for two and a half years. Of course, you can go here and, once registered, get a copy of the journal.

But people don’t have a lot of time to read a journal like this so it has been available since the start of last year in an audio form too. And you can now subscribe to it on iTunes so it will just simply appear in the podcast section of your iTunes, and (if you have things set up right) get synced to your iPod, iPhone and/or iPad so you can listen to it in the gym or in your car during time when there aren’t too many other things that you can be doing other than listening to something.

To subscribe to the Synopsys journal on iTunes click here.

The current issue covers Intellectual property (IP). IP is no longer a “nice to have” for chip design. You cannot hope to design a complex chip, and be competitive, without using IP. In this issue, Synopsys takes a look at how the IP market has matured, how design teams are deploying IP today, and put down some markers for the future. Rich Wawrzyniak, Analyst with Semico Research Corporation, sees a future where design teams integrate complete SoCs as subsystems in much the same way as they use IP blocks today. Dr. Seh-Woong Jeong, Executive Vice President for Systems LSI at Samsung Electronics Co., explains how his teams balance the tensions between time-to-market and quality with the knowledge that it now takes almost as long to develop a complex IP blocks as it does the chip itself. And Joachim Kunkel, Senior Vice President and General Manager of Synopsys Solutions Groups, puts forward a case for IP as an enabling technology for businesses that want to innovate through SoC design. In iTunes, each of these interviews is a separate track (or “tune” in iTunes parlance, although in this context that is quite amusing).