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48th Annual Design Automation Conference

48th Annual Design Automation Conference
by Daniel Nenni on 05-23-2011 at 8:08 am
Categories: EDA, Events

The 48[SUP]th[/SUP] Design Automation Conference (DAC) is now upon us. DAC is billed as “the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions” for which I would have to agree with 100%.

The first DAC I attended was in 1984, Albuquerque New Mexico, which was one of the first to allow exhibitors. It was an exciting time in semiconductor design, so much innovation, new technology everywhere, the Design Automation Conference is and has always been the cornerstone of EDA. This will be my 28[SUP]th[/SUP] DAC and certainly not my last since the Rapture didn’t get me, unless of course the world ends on October 21st.

SemiWiki will be at DAC giving away iPad2s in booth #1432.Register for SemiWiki on an iPad2 at the booth and you qualify to win. Current SemiWiki members just check in and qualify to win.


This year I was part of the DAC planning process and organized two pavilion panels which is what this blog is really about:

The first panel is Hogan’s Heroes: The Reaggregation of Ecosystem Value

Topic Area: Business
Tuesday, June 7, 2011
Time:11:00 AM—12:00 PM
Location:Booth #3421

Summary:The semiconductor ecosystem shifts its value aggregation on somewhat predictable cycles. These are followed by longer periods of stability during which new companies are created. The latest cycle is being driven by system houses. What impact will these new trends in system design have on EDA and IP business models and enterprise value?

Organizer:Daniel Nenni – SemiWiki, Danville, CA
Moderator:Jim Hogan – Tela Innovation, Inc.,Campbell,CA
Speakers:Ajoy K. Bose – Atrenta, Inc., San Jose, CA Jack Harding – eSilicon Corp., Sunnyvale, CA Grant A. Pierce – Sonics, Inc., Milpitas, CA

The second panel isWhy the Delay in Analog PDK?

Topic Area: Analog/Mixed-Signal/RF Design
Wednesday, June 8, 2011
Time:10:30 AM — 11:15 AM
Location:Booth #3421

Organizer: Daniel Nenni – SemiWiki, Danville, CA
Moderator:Steven Klass – SMSC,Phoenix,AZ
Speakers:Mass Sivilotti – Tanner EDA, Monrovia, CA, Tom Quan – Taiwan Semiconductor Manufacturing Co., Ltd., San Jose, CA Ofer Tamir – TowerJazz, Newport Beach, CA

Summary:Why does it take so long for foundries to release analog/mixed-signal process design kits (PDKs)? The amount of AMS content in your designs is growing, and the pressure to move to smaller process nodes is increasing. This is your chance to talk to the people who develop your PDKs and reference flows!

Tom is a natural in front of the camera, he did it in one take! This is must see TV!

As for me, if we haven’t met please introduce yourself and feel free to buy me a drink. If we already know each other just buy me a drink. This DAC I will be blogging for beverages! Don’t forget to click the LinkedIn share button below in support of the 48th Design Automation Conference. See you in San Diego!


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FPGA Prototypes Made Easy

FPGA Prototypes Made Easy
by Paul McLellan on 05-23-2011 at 5:00 am
Categories: Uncategorized
2 Comments

FPGA-based prototype boards are a fast, cost-effective platform for SoC system validation but they are notoriously difficult to set up and to debug. There is a big upside, however, allowing early software integration and testing and thus finding bugs in both the software and the SoC earlier. This approach is much cheaper than commercial emulators. However, problems of debug visibility and the need for repeated slow FPGA compiles limits their use to late in the design cycle.

The basic problem is that you need to decide in advance which signals to monitor, and add code to the RTL to bring those signals out. Of course, they always turn out to be the wrong set of signals, but to make a change requires adding the new signals and recompiling the whole FPGA. The number of pins available also restricts how many signals can be probed.

What you would really like is to be able to have thousands of signals probed, and be able to change your mind to add new probes without requiring a complete recompile of the FPGA which can take hours.


Protolink proble visualizer is a mixture of hardware and some clever software that gives just this capability. The way it works is that the RTL for the design is augmented with a bit of code before compilation (there is an overhead of a few percent for this). After compilation, the detailed routing of the FPGA is analyzed, the dummy module is replaced with the actual gates required for Protolink and then the verification can be run with the ProtoLink interface card attached to the prototype board. If an additional signal needs to be probed then small adjustments to the FPGA are all that are required.

The traditional approach gives the capability to monitor tens of signals for a limited number of cycles, and with the time required to add a new signal measured in hours or even days. With Prove Visuallizer it is possible to monitor thousands of signals for millions of cycles, and adding a new signal to probe is a matter of minutes.

The whole system is interfaced through Verdi, giving a common user-interface for simulation, FPGA prototyping and conventional in-circuit emulation. Verdi’s advanced visualization, tracing and analysis all operate to produce an extremely productive test and debug environment.

Probe Visuallizer backgrounder

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Analyzing and Planning Electro-static Discharge (ESD) Protection

Analyzing and Planning Electro-static Discharge (ESD) Protection
by Paul McLellan on 05-23-2011 at 5:00 am
Categories: Ansys, Inc., EDA

ESD has historically been a big problem analyzed with ad-hoc approaches. As explained earlier, this is no longer an adequate way to plan nor signoff ESD protection.

Pathfinder is the first full-chip comprehensive ESD planning and verification solution. It is targeted to address limitations in today’s methodologies. Using a full-chip modeling approach, it can verify that a design meets ESD guidelines and identify vulnerable areas of the design. It can report if current density exceeds limits for wires and vias. It works for both digital and analog circuits.

There are three different types of analysis.

[LIST=1]

  • First, human body model (HBM) and machine model (MM) checks. These are the ESD problems that can result from either humans touching the pins or during manufacturing test and assembly. Pathfinder will check to ensure than if ESD voltage occurs between any two pins (or bumps) then it will traverse one or more clamp cells placed between those pins. First the loop resistance through each clamp cell is estimated. If the resistance is too high then that clamp cell is ignored and only any remaining cells (if any) for that path are considered. Checks are performed to ensure that the ESD protection is sufficient between each pair of pins.
  • Charged device model (CDM) checks. This is check for build up in logic, package capacitors and other circuits such as memories that need to have low resistance discharge paths.
  • Current density checks. This involve estimating the current density in wires following the injection of current into any pin pair. It calculates the current through the wires and vias and highlights any which fail the current density limits (as defined by the process guidelines).

    Following this analysis, extensive information can be created to enable debugging: reports, histograms and graphical displays overlaid onto the layout. This makes it easy to perform what-if experiments without leaving the tool. Once any changes are confirmed, an ECO report is created to allow for implementation of those changes in the final layout of the chip.

    Pathfinder is used in two different ways. Early in the design it can be used for ESD planning, especially on bumped chips which need to contain extensive ESD protection circuitry in the core and not just in an IO ring. If this is not done, and ESD protection circuitry is only added very late in the design process, it risks causing unexpected area (and perhaps timing) problems and thus potentially major schedule impact. The second way is to analyze the final design to signoff on the ESD protection prior to tapeout.

    Pathfinder white paper

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    Right-source your electronic designs

    Right-source your electronic designs
    by nitindeo on 05-19-2011 at 5:42 pm
    Categories: Uncategorized

    Concept2Silicon Systems (C2SiS) is focused on providing complete solutions for complex SoC and System designs with best in class engineering capabilities and most cost-efficient business model. Our highly capable engineering team has experience in delivering 200+ silicon and system design solutions to its customers in the most advanced semiconductor process technology nodes up to 28nm.


    We have delivered extremely tough design criteria for embedded ARM with low-power and high-performance on a tight timeline. Our customers include ARM, TI, Cypress and the large communications company in Southern California. Please go to www.concept2silicon.com for more information.



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    Cadence Virtuoso 6.1.5 and ClioSoft Hardware Configuration Management – Webinar Review

    Cadence Virtuoso 6.1.5 and ClioSoft Hardware Configuration Management – Webinar Review
    by Daniel Payne on 05-19-2011 at 5:33 pm
    Categories: Cadence, Cliosoft, EDA

    Introduction
    Cadence and ClioSoft made a webinar recently and I’ll summarize what I learned from it.

    What’s New from Cadence in Virtuoso 6.1.5

    • Back2Basics (28nm rule integration, Skill improved with object-oriented, OASIS support, HTML Publisher, Waveform re-written for better Analog support, smaller Waveform db files, generate layout from schematic source improved )
    • Connectivity Design (smarter wire to via automation, better auto routing for bus and diff pair, one router simplifies setup time, low power using Common Power Format with visual spreadsheet)
    • Design Constraints (in schematic add layout constraints for Encounter, constraint checking simplified, constraints are bi-direction schematic-layout)
    • Selective Automation (reliability analysis integrated, fluid guard rings without tweaking Pcell code )
    • Parasitic Aware Design (how does physical layout affect performance, schematic-> constraints-> tests and sims -> pre-layout parasitic estimates -> circuit optimization -> MODGEN creation -> device placement -> net routing -> in-design verification -> extraction -> parasitic comparison)

    Do Not

    • Use 6.1 like you did 5.1, there’s no benefit

    Do

    • Take advantage of new features to get benefits

    ClioSoft
    Karim Khalfan talked about the SOS tool used by IC designers:

    • Hardware Configuration Management – should be easy to use
    • Design Management is for the entire IC team
    • Manage everything: Spec, RTL, Verification, P&R, Analog, Custom Layout
      • Large teams, multiple sites, data explosion, binary files, complex flows, IP and re-use, design variants
    • Features
      • Version control – text and binary files, folders, tags and labels
      • Release management – take snapshots
      • Issue tracking – connect to your favorite tools
      • Design reuse – reference previous projects
      • Global Collaboration – client/server architecture, cache, synched
      • Authentication – users identified, groups (schematics, layout, etc.)
      • Design Aware Integration – integrated into Virtuoso
    • Hardware Design
      • Easy to checkin and checkout, use design objects
      • Disk use is optimized, not sending terabytes across network
      • Isolated and shared work spaces, you decide
      • Design hierarchy can be managed
      • Visual differences – compare schematics or layouts, click on each change
      • Integration directly into Virtuoso
    • DDM is built just for IC designs, no 3rd party SW needed

    Then Karim did a live demo of Virtuoso 6.1.5 with ClioSoft menus (Design Manager) and commands explained as he went through the process of checking in cells and checking out cells for an IC project. Used both the Library Manager and Schematic tools in Virtuoso. Visual Difference shown between two versions of a schematic or layout, flat or hierarchical.

     

    Summary
    Cadence and ClioSoft have really created a powerful and flexible IC design environment for team-based design. Both the designers of schematics and the layout people will benefit from using hardware configuration management by keeping track of their complex projects all within the familiar Virtuoso tools.

    Also Read

    How Avnera uses Hardware Configuration Management with Virtuoso IC Tools

    Hardware Configuration Management and why it’s different than Software Configuration Management

    Webinar: Beyond the Basics of IP-based Digital Design Management

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    A New Hierarchical 3D Field Solver

    A New Hierarchical 3D Field Solver
    by Daniel Payne on 05-19-2011 at 2:04 pm
    Categories: EDA

    Introduction
    3D field solvers produce the most accurate netlists of RC values of your IC layout that can then be used in SPICE circuit simulators however most of these solvers produce a flat netlist which tends to simulate rather slowly. Thankfully several years ago the first hierarchical SPICE tools were offered by Nassda (HSIM) and Cadence (UltraSim) but they require a hierarchical netlist to simulate large designs quickly and efficiently.

    What’s New?
    This week I spoke with Dermott Lynch of Silicon Frontline about their latest Hierarchical 3D Field Solver named H3D.

    Q: What is hierarchical extraction a big deal?
    A: Most SOCs have many memory and other repeated structures in their layout, so exploiting layout hierarchy provides a big benefit to users.

    Q: What kind of approach did you use with H3D to create a hierarchical netlist?
    A: We have a patented approach based on the Random Walk Algorithm, interested readers can see the patent here.

    Q: How are the CPU run times with your hierarchical approach to extraction?
    A: This new tool shows a sub-linear increase based on the number of nets.

    Q: Does H3D fit into my existing IC tool flow?
    A: Yes, it reads a standard layout and produces a netlist that can be: distributed, lumped, C, R, RC and RCCc.

    Q: How about using distributed CPUs?
    A: We support both distributed and multi-core CPUs to help speed up the results.

    Q: Compared to a flat extractor, what kind of speed improvements should I expect with this hierarchical extractor?
    A: From 10X to 100X speed improvements, based upon how much hierarchy there is in your layout. Designs with the most hierarchy are: FPGA, Image Sensors and memory rich SOCs.

    Q: Should I expect the RC numbers extracted from your flat tool to match the hierarchical tool?
    A: Yes, they are statistically equivalent values.

    Q: How does H3D help my post-layout simulation run times?
    A: We’re seeing speed improvements between 2X and 7X faster using the H3D netlist in a Fast SPICE simulator.

    Q: How popular are your field solver tools?
    A: Over 350 designs have been verified at over 30 customers, and they’ve been adopted by 12 of the top 30 semiconductor vendors.

    Q: What is pricing like for H3D?
    A: Pricing starts at $99K annually and there are several configurations to choose from.

    Summary
    If your IC design requires the highest accuracy for parasitic RC values and the layout has hierarchy then you should start to consider the tool flow of H3D for hierarchical extraction followed by a Fast SPICE tool like HSIM or UltraSim.

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    Electro-static Discharge (ESD)

    Electro-static Discharge (ESD)
    by Paul McLellan on 05-18-2011 at 4:26 pm
    Categories: Ansys, Inc., EDA

    Electro-static discharge (ESD) has been a problem since the beginning of IC production. Chips function on power supplies of up to a few volts (depending on the era) whereas ESD voltages are measured in the thousands of volts. When you reach out for your car door handle and a spark jumps across, that is ESD. If you were touching a chip instead of your car (and cars contain plenty of chips these days) then the chip has to be able to absorb those thousands of volts and harmlessly dump them without letting voltages or currents on the chip go beyond what can be handled. ESD doesn’t just cause a potential problem when it happens, it can physically destroy the chip. Estimates are that as many as 35% of all in-field chip failures are due to ESD.

    For example, if ESD is incorrectly handled and very high voltages end up on the gate of the chip, the discharge can destroy the thin oxide underneath the gate and make that transistor, and probably thus the whole chip, inoperable. Since the thin oxide is getting thinner with each process node it is not surprising that ESD is a problem that is only going to continue to get worse. Metal geometries are also getting smaller, and so have a reduced capacity to handle a current surcharge.

    There are other reasons that it is getting worse, not just shrinking geometries. The higher levels of integration on mixed signal chips man that there are many isolated independent power/ground networks, which aggravates the problem. Also, there are more and more hand-held devices (cell-phones etc) which means that there is more direct access to the ICs. You are not very likely to have n ESD problem with the engine-controller in your car since you don’t touch it. The base of your iPhone has a socket with lots of connectors that go straight to the chips inside the phone.

    ESD events can also occur during packaging, assembly and test of the IC. And, in fact, charge buildup inside the chip can also cause ESD failures, especially from in-package capacitors and from on-chip memories.

    ESD protection has typically been implemented by placing clamp circuits at appropriate locations on the chip that do two things. First, provide a low impedance discharge path for the ESD and second, clamp the signal voltage at a level that avoids dielectric breakdown. Historically these clamp circuits have been placed in the I/O and power/ground pads. Input pads are especially vulnerable since the input pin has to be connected to the gate of the input driver. The clamp circuits are quite large but since the pads and their drivers are already large this doesn’t have a huge impact.

    However, modern designs often have c4 bumps all across the chip, and with the coming of 3D (and 2.5D) designs this will only increase. This means that clamp circuits, which are large, are needed in the core of chip too and thus compete for area with circuitry in the core such as standard cells.

    Historically, analysis of ESD has been done in a fairly ad hoc manner, with design guidelines and manual verification. But as the complexity of the design and the number of power/ground nets increases this is no longer adequate. A full-chip ESD verification solution for ESD signoff is required. Indeed, as more ESD protection is needed in the core, it is no longer enough to analyze after the design is complete, ESD protection needs to be planned since it has potentially large impact on the area available in the core for actual implementation of the design.

    Whitepaper on Pathfinder

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    Adjusting Custom IP to Process Changes

    Adjusting Custom IP to Process Changes
    by Daniel Nenni on 05-16-2011 at 1:57 pm
    Categories: Uncategorized
    12 Comments

    A High-Definition Multimedia Interface (HDMI) IP core was being implemented in an advanced process technology. This fairly large and complex analog mixed-signal (AMS) IP comprising over 130K devices was close to being finalized and shipped to the customer. But many design rules at the foundry were unexpectedly changed from recommended to compulsory, creating hundreds of thousands of violations. It would have taken months to fix all the problems. An automated migration was really the only possible solution.

    The main changes: New PDKs were received from the foundry incorporating modified PCells, changed rules for DRC (design rule check) and DFM (design for manufacturing). Some of the most significant were:

    • Larger poly gate end-cap. Simple to fix when there is room for the extra poly but very hard to fix when there are other nearby transistors, poly etc
    • Larger metal on via enclosure. Simple to fix if the via is isolated but very hard to fix in the typical case where the via is surrounded by minimum spacing routing
    • Small notches prohibited

    The main non-changes: Obviously the migration needed to be performed with minimal possible changes to the design, especially for an AMS block. In particular, design hierarchy needed to be maintained with no changes, and LVS must continue to pass. Corrections should have minimum affect on the design, especially in areas where no violations needed fixing. Virtuoso database integrity should be maintained, in particular structure, connectivity, Pcells etc.

    The schedule: The runtime should only be a few hours to allow rapid iteration. At least 90% of the design rule and DFM violations should be fixed automatically. The entire project, including any manual fixup, and technology file creation, should be completed in 3 weeks.

    How the above challenges were addressed:

    Metal enclosure of vias bigger in target:meta1 enclosure around via needs to be enlarged without creating DRC errors due to the introduced extra metal. A similar change is required on all metal levels. The migration engine not only enlarges the metal enclosure, but will move adjacent wires where needed to maintain a correct spacing.

    Replacing some Pcells introduced jogs: replacing some pcells and via cells with target PDK cells resulted in small metal jog DRC errors which needed to be removed automatically.

    The poly to diffusion spacing was too small:     at 90° gate connections the poly spacing to the source/drain diffusion needed to be enlarged automatically to be DRC correct. The migration engine will move adjacent poly wires or devices where needed to maintain correct spacing.

    Experience     : The Sagantec application engineer took about a week to set up the technology file from scratch and debug it, running a few sub-blocks to pipe-clean the flow and ensure that the results maintained LVS connectivity and Virtuoso database integrity. Mid way through the project, a still-newer PDK was received from the foundry with modified devices that required changes to the source layout database. However, due to having the automated flow in-place these changes caused only minimal delay compared to using massive layout resources to make the changes by hand.

    The Sagantec tool automatically corrected over 95% of the ~250,000 violations created by the rule changes, both the DRC and the DFM problems. The remaining violations were easily handled and were cleaned up manually in less than a week of effort.

    The final migrated design completely maintained the hierarchy of the original design and was LVS clean.

    Results : The corrected output was available before the agreed deadline. Each iteration of the design took only a few hours to run. Over 95% of the violations were fixed automatically and the remaining ones were easily fixed within a week.

    One big advantage of the flow was risk-reduction and change-management since rules, requirements and libraries were all unstable. The final Virtuoso database had exactly the same structure as the original layout and nothing in the database was lost or changed during the correction.

    IP block Adaption: Altering a complex custom physical design IP to take account of design rule changes can either be done by an experienced and highly effective layout team or using an automated flow that handles almost all of the work automatically. But when the volume of modification is high and the schedule is tight, the manual correction route is no longer a viable option. Furthermore, with any subsequent changes of design rules, the manual work needs to be repeated, resulting in additional delays and cost. That is where automatic solutions, such as Sagantec’s migration technology, provide the most significant advantage, as once the flow is setup, rule update iterations can be completed in hours rather than weeks. In this case, layout adjustment work that would have taken 20 weeks was reduced to one week, effectively a 20x effort reduction. In addition to licensing the migration software, Sagantec also offers migration as a service, performed by its experienced application engineers. Such service offering minimizes the turn-around time, ensures optimal use of the software and accomplishes high quality results in the shortest time.

    Sagantec Demo Suite Registration


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    Shakeup at Mentor Graphics

    Shakeup at Mentor Graphics
    by Daniel Payne on 05-12-2011 at 12:22 pm
    Categories: EDA, Siemens EDA

    Reading the title you guessed it right, Mentor Graphics has three new board members today from the slate offered by billionaire activist Carl Icahn:

    • José Maria Alapont, chief executive of the auto parts maker Federal-Mogul
    • Gary Meyers, a director of the chip maker Exar
    • David Schechter, an executive at Mr. Icahn’s investment firm

    After Wally Rhines made the announcement of the three new board members, the audience broke into applause and new board member David Schechter said, “Thank you again, thank you Mentor employees. I look forward to working with you.”


    The Commons at Mentor, Wilsonville

    The acrimony in the press over the past month between Mentor and Mr. Icahn has now given way to a new world order within Mentor Graphics as three board members have been replaced by outsiders.

    My hope is that Mentor continues to focus on providing innovative EDA tools to meet the challenges for IC, PCB and Systems Designers.

    The Meeting Details
    Arriving 30 minutes early at Mentor Graphics this morning I parked and approached the building for the annual share holders meeting. At the door was tight security and a check-in process to identify me as Press. I sat next to Mike Rogoway, Business Writer at the Oregonian, we’ve both been following this hostile drama with Mentor for the past year. We tried in vain to connect with Clear wireless but it simply wasn’t working, so we couldn’t tweet out the highlights.

    Ry Schwark, PR Director told me the Press rules: No photography, No video, No questions.

    The buzz in the room before the meeting is, “Will Carl Icahn show up?” Most people think that he won’t show and instead will send others in his place.

    Bryan Derrik, VP of Corporate Marketing is making the rounds and chatting with co-workers and shareholders.

    Don Nail, a Mentor shareholder for 15 years is ready for change and has voted for the Icahn change.

    It’s 9:11AM and Wally Rhines of Mentor just showed up so we are soon to get started this morning. A hush has entered the room. All the Mentor executives and board members occupy the front row.

    30th annual meeting is opened by Wally Rhines. Questions will be allowed, and cards will be handed out for attendees to use during Q and A.

    Directors are introduced to a deadly quiet audience.

    Notably executives are introduced by Wally, still a quiet audience.

    Dean Freed takes over from Wally Rhines to announce the rules for the meeting. Last call to change your mind on voting by ballot in person. Reading from a script, the minutes are skipped from last year, list of board candidates read.

    IBS Associates is the official company to count all votes today.

    Dean mentions the board members from Carl Icahn, and Mr. Schechter is in attendance today.

    Six items for vote are rattled off.

    Wally Rhines takes over from Dean and reports a summary of recent Mentor accomplishments. FY2011 Results, revenue of $915M, up 14% from FY2010 the fastest growth rate in public EDA companies. Non-GAAP EPS of $0.70, up 49%. Bookings up 30% for the year.

    Review of “What is EDA?” Software for IC, PCB and Systems design.

    EDA Product Segments show 60 distinct software categories for EDA (courtesy of Gary Smith EDA).

    Largest EDA Market Share by segments (SNPS, CDN, MENT) shows about a 40% to 66% market share to the #1 supplier across each category.

    Mentor Revenue: Integrated System Design PCB is 25%, Scalable Verification (Simulation, Emulation) is 25%, IC Design to Silicon (Calibre, IC, Olympus P&R) is 30%, New and Emerging (transportation, embedded, DFT) is 15%.

    80% of Mentor revenue is in products where they are #1 or #2 in market share.

    PCB is a #1 market for Mentor, and they have been growing market share to 40% total.

    Mentor Strategies: Extend, Detect Discontinuity (Calibre vs Dracula),

    Emulation – Functional simulation is too slow, so emulation will enable verification of the largest new designs (Veloce – about 5X faster than competitors). Market share double in FY 2011.

    New Markets – Transportation (auto and aerospace) and embedded software. Products: CHS – wire harness, System Vision – mechatronic, Volcano – network design.

    8 out of last 9 quarters Mentor has exceeded analyst expectations.

    Fiscal 2012 revenue estimates at $1B, a 9% growth.

    Dean Freed – any more ballot votes? At 9:40AM the polls are closed.

    Waiting for a final share holder to hand-write his ballot, the room starts a small murmur and whispering. Wally and Dean look on, then Wally cracks a joke, “Lot of suspense, this could be a swing vote.”

    The preliminary vote says that 5 board members stay, and that 3 new members are elected (per Icahn’s). The room erupts into applause.

    Wally pledges cooperation with Icahn’s 3 board members.

    Wally opens up for questions and answers.

    David Schecter, new board member, “Thank you again., thank you Mentor employees. I look forward to working with you.”

    The Votes being taken away by armored truck

    Shareholder Questions:

    Jim Romero – What about acquisitions to grow?

    Wally – Yes, primarily our growth is internal. Plus, we do acquisitions, typically small in size. Flomerics is an acquisition example.

    No more questions or comments.

    David Schechter (Newest Mentor board member)
    Q: Was this a surprise?
    A: David – No, we expected this result. We look forward to working with the other Mentor board members to return the greatest value to share holders.

    Q: Any other comments?
    A: David – I’ll have Mr. Icahn reply to you.

    Mentor Founder
    After the meeting I chatted with Mentor Founder Tom Bruggere (now Chairman/CEO at 13therapeutics) and Mike Bosworth (former CEO of Context, acquired by Mentor).

    Q: What did you think of the vote today?
    A: It is what it is.

    Mike Bosworth, Tom Bruggere

    I first met Mr. Bruggere in the 90’s when Mentor Graphics acquired Silicon Compiler Systems.

    All of the founders of Mentor have long since left the company, although many are still interested in the outcome of today’s vote for a change in board members.

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    How Good is Your Verification?

    How Good is Your Verification?
    by Paul McLellan on 05-11-2011 at 5:00 am
    Categories: Uncategorized

    The traditional way for analyzing the effectiveness of testing in the software world and in the RTL world is code coverage. Make sure that every line of code is executed. This is a pretty crude measure since even 100% code coverage doesn’t mean that all the condition has really been tested but it is certainly necessary–after all if a line of code is never executed then there is no way to know if it is correct or not.

    In the manufacturing test world the criterion is to look at fault coverage. Every signal is considered to be stuck at 0 and 1 and the percentage of these faults that actually propagate to the outputs is calculated. This isn’t perfect since other types of faults can exist (two signals shorted together for example) but again it is a good starting point and there is a good chance that other faults will be detected if the fault coverage is good.

    A better way to do things would be to take the design, add a bug, run the test and see if the added bug was detected by the test. Repeat for lots of bugs and you start to get a good idea of how effective your verification is. This gives you an objective metric as to what percentage of the injected bugs are found and, moreover, by looking at which bugs are missed allows the verification tests to be strengthened in the appropriate areas.


    Certitude does just this, automatically injecting bugs into the design, running the simulation and then seeing how many of the injected bugs are flagged. For example, it might change “a=b|c” in your original code into “a=b&c”.

    This helps with the closure challenge: is it safe to sign off the RTL? Since it is impossible to ever exhaustively test a design, this is always somewhat of a judgement call. But Certitude gives an objective measure of stimulus and checker completeness to support this signoff decision, along with pointers to specific holes to accelerate the closure process by directing incremental efforts to the areas requiring additional attention.

    The latest version has been further enhanced by adding new fault types that better represent typical SoC failures. Fault dropping has been expanded to remove redundancy in the results. Results can now be ranked based on the impact of the fault, directing the user to where to analyze first.

    Certitudeproduct page