I will share with you the most interesting I have heard during IP-SoC 2010, last December in Grenoble. Today, let’s summarize what I heard about the future of the IP business. The presentation was done by Gartner, in the “Auditorium” (largest room). It first started with the results for 2010, and I took some notes, as you can see the business figures are very informative:

Overall IP business growth (2010/2009) was +24.8%, for a total of $1677M

• IP licensing (50% of total) grew by 20%, royalties (42%) grew by +31% and maintenance/services (8%) by 25%.

This “forecast” is useful, as well as some trends proposed by Gartner about the IP market:

• Innovation is moving from chip level to system level was the clear message. Or, if you prefer, be prepared to provide not only a piece of H/W to be used within a chip, but a more complete solution integrating several pieces of H/W, the drivers for these, and the S/W at system level. (We will come back to this in a next post).
• In Automotive and Industrial, the IP usage will be growing from being 5 to 10% of a chip to 30 to 40% within 3-5 years.
• In Wireless, IP usage will double and pass from 20% today to 40% in 2013/14.

Good to hear, this means that the IP market, as a business, should be growing in value per license (moving from chip to system level) and in license number, as the IP usage is strongly growing in at least two segments. Then came the growth forecast for 2011 to 2014. Don’t worry, I will share it with you:+6% in 2011, then +2.3% in 2012, followed by +6.7% in 2013 and 6.9% in 2014.Here I disagree! How cans a certain market strongly grow in unit value and in unit count, and posts a mere 5.8 CAGR ? I know the number of ASIC/ASSP design starts is expected to go down, but only by 2 or 3% per year. And the FPGA design starts also generate license sales (another post will come, as I have attended to the FPGA panel, see: http://www.design-reuse.com/ipsoc2010/program/panel_fpga.htmlSo I decided to dig into these figures, here is that I found.Using the forecast for 2010-2015 I have built for the Interface IP market(see: http://www.ip-nest.com/index.php?page=wired)analyzing precisely USB, PCIe, HDMI, DDRn, SATA, MIPI and a few others protocols, I have built this table.For 2010/2015, the CAGR is: 14.3%Using Gartner’s figures above listed, I have built a similar table, including all the IP segments. .For 2010/2015, the CAGR is 5.8%Now, extracting the expected market growth for all the IP businesses: Processor, Memories, Libraries, Mixed Signal, Digital… everything at the exception of the Interface IP, becomes pretty simple (no problem, I give you the formula: when a = b + c, then b = a – c; rocket science!). So the new table: the CAGR is now 2.7% !!What do you think? Is it realistic to expect a growth rate between 2 and 3% for a certain market, when everybody says the IP usage will grow (double?) because that is the only way to guarantee the TTM, for ASIC, ASSP and also FPGA?I really would appreciate your comments about this!

One of the important but often unrecognized aspects of engineering is re-building the infrastructure underneath key design tools. Sometimes this gives a new desirable capability but often a lot of the effort is simply to modernize the code base so that it is possible to continue development effectively going forward. For example, I remember in Compass days replacing our creaky graphics infrastructure with something more modern. It was expensive to do and it didn’t generate any additional revenue, but the old code had been written well over a decade before and was no longer adequate. Because this sort of infrastructure underlies everything, it is rather like changing the wheel of a car without stopping.

I met with Bob Smith of Magma late last year, and coincidentally I ran into Hamid Savoj, the CTO, at a conference on 3D chips a few days later. They have successfully done one of these changing the wheels without stopping exercises recently.

Magma’s engineering team have swapped out the old timing and extraction engines from Talus and replacing them with the Tekton timing engine and the QCP extraction engine to create Talus Vortex 1.2. This can place and route over one million cells per day with all the modern requirements for crosstalk, metal migration, multi-corner etc. It can handle up to 3M cells flat, which is important since probably one of the biggest wishes of the semiconductor customers is to be able to handle designs flat, or with as little hierarchy as they can get away with. Ideally today they would like to be able to handle 20 million cells or more flat. All hierarchy added in any design tool due to capacity limitations of the tool tends to cause design efficiency to drop, sometimes dramatically if the number of blocks grows large. But wait, there’s more, as the old ads say.

Along with some further infrastructure work they have also created Talus Vortex FX which is the first distributed place and route solution. This pushes up the performance to over 3 million cells per day, and the capacity up above 8 million cells, which more than triples designer productivity. It analyzes the design, then partitions it into pieces that can be processed separately on their own server, and then eventually combines all the results back together (they call this Smart Sync). Some design tools are fairly easy to distribute (for example, DRC can be run on different parts of the chip in parallel and then stitched back together), some are very difficult (simulation, because there is a single global time-base so it is hard to find things that are independent) and some in between like place and route, although clever algorithms are needed to decide how to divide up the design amongst the computing resources.

As an irrelevant aside, in 1952 a car was driven across the US and back without stopping; of course it needed to have facilities to change a wheel without stopping. It can be seen today in the San Diego Automotive Museum.