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Common Platform Technology Forum: Peering into the Future

Common Platform Technology Forum: Peering into the Future
by Paul McLellan on 03-10-2012 at 9:00 am
Categories: Cadence, EDA, Foundries, GlobalFoundries, Siemens EDA, Synopsys

Next Wednesday is the Common Platform Technology Forum. “Common Platform” is a name that only a committee could have come up with, giving no clue as to what it actually is. As you probably know, there are various process clubs sharing the costs of technology development (TD) and one of them consists of IBM, Samsung and Global Foundries. Although they have many partners, historically they have worked closely with ARM and Synopsys.

TD versus capital has gone through a couple of phases. It used to be that anyone could build a fab but getting a process to run in it was expensive. Then in the 90s, fabs suddenly became really expensive and the cost of licensing a process was a lot less. But then TD got really hard again, and it became so expensive that only Intel could really afford to go it completely alone. Hence alliances like the Common Platform.

Wednesday March 14th at the Santa Clara Convention Center is this years Common Platform Technology Forum. The keynote speakers (from 9am to 11.30am) are:

  • Dr. Gary Patton, Vice President of Semiconductor Research & Development Center, IBM
  • Gregg Bartlett, Chief Technology Officer, GLOBALFOUNDRIES
  • Dr. Jong Shik Yoon, Senior Vice President of Semiconductor R&D, Samsung
  • Simon Segars, Executive Vice President and General Manager, Physical IP Division, ARM

There is a partner pavilion then open for the rest of the day. I’m presuming lunch is provided there too. And since it is Pi day (3.14), from 1.30pm they will be serving…wait for it…specialty pies.

From 1-2pm is a panel session on the R&D pipeline for future technology innovation. There are representatives of (surprise) Global Foundries, Samsung and IBM. Along with ARM and the College of Nanoscale Science and Engineering (which I confess to never having heard of).

In the afternoon are presentations from Synopsys, Cadence and Mentor (how’s that for EDA neutrality?).

At 2pm, John Chilton of Synopsys talks about designing ARM-based SoCs at 28nm and 20nm. He is followed, at 3pm, by Sampta Bansal of Cadence, who sees Synopsys’s 20nm and raises it by talking about delivering on 20nm and embarking on 14nm. Then, at 4pm, Mentor’s Michael White talks about double patterning at 20nm.

For me the Mentor presentation looks the most interesting since it looks like a sort of introduction to double patterning, a subject that I need to learn a lot more about. And so, probably, do you. To register click on the banner below.

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Elpida and Japan Inc

Elpida and Japan Inc
by Paul McLellan on 03-09-2012 at 2:17 pm
Categories: General

Last week, the Japanese memory company Elpida filed for bankruptcy. There is worldwide overcapacity in DRAM and somebody had to go. Its strength and the weakness was that it was much more outward facing than most of the Japanese semiconductor and electronic industry. So it had to compete globally and wasn’t up to the task.

I think looking at the Japanese mobile phone industry is revealing. If you visit Japan you get some idea of the problem. Everything is too inward looking. All the mobile phones are great and seem in some ways to be ahead of what we have in the US, and they are all made by Japanese manufacturers. But that is the problem, they are made by manufacturers who have given up in the rest of the world.

Greg Hinckley, the COO of Mentor Graphics, once told me about interviewing a candidate for a finance position who came from American Airlines. Their focus, the candidate said, was to touch down 30 seconds ahead of United. It was as if Southwest and Jet Blue and all the rest didn’t even exist. Being the best airline just meant being the best legacy airline: beat United, Delta and the others.

The Japanese cell-phone companies are like that. They are so competitive for their share of the Japanese market that they have given up on the global market and what it takes to compete there. Of course, the Japanese cell-phone transmission standards are different which means that you have to decide whether to compete in Japan, overseas or both. Those different standards may have looked like a giving a good unfair advantage to the Japanese since Nokia, Ericsson or Samsung were unlikely to focus on the Japanese standard first even during the initial high-growth period. But on the other hand the Japanese manufacturers have no market share in the rest of the world, which is orders of magnitude bigger.

Last time I visited the usual Japanese semiconductor companies I got the feeling that they were all only competing with each other. By and large they were making chips to go into consumer electronics products for the Japanese market. There were obviously far more products and far more chips being done than could possibly make money, just like all those cell-phones and cell-phone chips couldn’t be making money (not to mention that the Japanese market is already saturated).

With too many companies, and too many uncompetitive semiconductor divisions, consolidation is to be expected. But Japanese politics is inward facing too and so they can only merge with each other and gradually move towards what I call Japan Inc in the semiconductor world (to be fair, this same issue is one that affects my American Airlines example; British Airways or Lufthansa is simply not allowed to buy a major stake, recapitalize them and clean them up because congress has laws preventing it).

I said a couple of years ago: “So it looks like gradually the semiconductor companies will consolidate into a memory company (Elpida) and a logic company and, based on past history, they won’t take the hard decisions necessary to be competitive globally rather than just in Japan.”

Well, it didn’t work out too well in memory, although presumably Elpida will re-emerge in some form.

On the logic side, NEC/Renasas(Hitachi/Mitsubishi), Fujutsu and Panasonic are rumored to be in discussions to merge. Toshiba is not on the list since it seems to be strong enough to go it alone, at least for now. But as fabs get bigger, and the cost of an individual design gets bigger, you can only make money addressing large global markets, not supplying a fragmented domestic market. Based on past form, merging Mitsubishi and Hitachi to form Renasas, and before they had finished getting that sorted out, adding them into NEC, and before that was done throwing in Fujitsu and Panasonic…let’s come back in a year or two and see how that’s working.

I guess I’ll stick with my statement from a couple of years ago. It’s still looking good.

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Apple’s New iPAD and the End of PC Benchmarks

Apple’s New iPAD and the End of PC Benchmarks
by Ed McKernan on 03-09-2012 at 10:19 am
Categories: Arm, Foundries, Intel Foundry, IP

With the introduction of the “New iPAD”, we now have the 2012 benchmark for the tablet market, including the offerings that will come from Amazon later in the year. As has been noted earlier, with each new mobile product iteration Apple unmoors itself from the PC foundations of Microsoft, Intel and even nVidia and AMD. At the unveiling of the new iPAD, Apple spent very little time extolling its wonderful, new A5X CPU and instead played up the experiences possible with their high definition Retina Display and high-speed 4G LTE communications. The number of ARM cores, the speed of the processors, the graphics engines are all of lesser concern than what the consumer experiences with the New iPAD connected to the Apple Ecosystem.

Back in the mid 1990s, when the world was trained to measure the value of their PC with the simple three letters: M-H-z and Intel was able to build an empire by delivering a new chip at a cadence of every 2 months backed by a full suite of synthetic benchmarks, there was the beginnings of an alternative vision of the future. The internet was just beginning to take off and just as significant, the bandwidth and wireless revolution that was well articulated by George Gilder in his book Telecosm pointed to a time in the future when the processor’s value would decrease relative to that of the communications infrastructure. Qualcomm was one company that Gilder tracked closely and looking back now almost 20 years later we can say it was his most prophetic selection.

Overlooked by nearly everyone in the 1990s was the importance and rise of the role of the graphics processor. Jen Hsun Huang’s vision of the future where the graphics processor becomes more important than the x86 processor was correct as can be seen in the increased die area dedicated to graphics within Intel’s Ivy Bridge and AMD’s APU offerings. After 4 cores, is there any value in an additional x86 CPU? The data says no. Intel’s transition from Sandy Bridge to Ivy Bridge is all about a vastly expanded graphics chip that for once challenges nVidia. As with processors, the graphics vendors measured their greatness with a full suite of benchmarks, which are now going to be cast into irrelevance in the new mobile markets with the New iPAD as the standard bearer. And soon to be followed by the iPhone 5 and a smaller $299 Retina display based iPAD in the fall. Did I mention the awesome Retina Display?

Because Apple is the leader in the mobile industry it is given great regard as to what is significant and supposedly true. When Apple’s Phil Schiller, Senior VP of Worldwide Marketing, displayed a graph that showed the new A5X with its quad core graphics is 4 times faster than the Tegra 3 without showing a benchmark, no one begged to question him. It is now written in hundreds of articles and plastered over the Apple web site. Personally, I am sure the Tegra 3 stacks up well to the A5X.

On the day after the launch, the technical web site Tom’s Hardware asked nVidia if it was true that the A5X was 4 times faster than Tegra 3. The response was telling in that nVidia wasn’t willing to challenge Apple’s claim on benchmarks without hardware to test. Should nVidia find out in the coming weeks that the Tegra 3 is indeed on a par or better than the A5X, I doubt that they will make it public. To do so would jeopardize their attempts to win the next generation MacBook Pro graphics sockets. And so they face a dilemma of losing their benchmark marketing tools in order to remain a supplier. Apple has effectively de-positioned nVidia’s Tegra 3 that is slated to be in a number of Android based tablets and smartphones this year. The Tegra 3 was smothered in the cradle. Qualcomm and Intel will be the benefactors of this deliberate Apple Branding slight of hand.

As I wrap up this blog posting, TI has just reported that sales will come in less than previous guidance based on slowing OMAP sales. In addition there are reports that Broadcom is challenging TI for the sockets for the next Amazon Kindle. Combine this with Intel’s aggressive push into ZTE, Lava, Orange, Lenovo and Motorola and one gets a picture of a fast commoditizing application processor and graphics market. The one chip inside the mobile smartphone and tablet that demonstrates high value is the baseband chip, which is being dominated by Qualcomm as they start to ramp 4G. Intel knows this and has a massive R&D effort underway to catch them in time for the launch of Haswell based ultrabook platforms in 2013.

Recent remarks by Intel executives appear to support the position that Intel would gladly torch the market with which the Atom Medfield processor is designed to serve in order to eliminate nVidia, Broadcom, TI, Marvell and AMD as viable competitors and more importantly to increase the data center footprint that spits out an unbelievable 50% operating margins. Qualcomm and Intel share a common goal of ramping 4G LTE into mainstream price points so that the Mobile Bandwidth Tsunami causes profits to rain down on the two ends of the wireless network.

The Era of Benchmarks is Coming to an End or I should say the new mobile market has tossed aside the benchmarks with which the PC market operated under for the last 20 years. I expect the Ultrabook PCs due out this year with their Retina based touch screeens and extended battery life to follow the pattern set by smartphones and tablets. The semiconductor playing field continues to experience rapid and dramatic change.

Full Disclosure: I am Long AAPL, QCOM, INTC, and ALTR

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Formale Verifikation in München

Formale Verifikation in München
by Paul McLellan on 03-08-2012 at 9:00 am
Categories: EDA

With DATE next week in Dresden, all eyes turn to Germany. Not to be left out, Jasper has a seminar on formal verification coming up on March 19th in the Kempinski Hotel at Munich airport. Unlike most “airport” hotels the Kempinski is indeed right in the heart of the airport. And for those of us who like a good German beer, the airport also contains a micro-brewery Airbräu where they brew their own beer in the airport, which I believe is unique.

Breakfast and lunch are provided, although I very much doubt that they serve the traditional Bavarian breakfast of beer and weisswurst. What they do serve, though, is lots of useful information about formal verification:

  • Formal verification of RTL blocks
  • Debug and design exploration
  • Post – silicon debug and root cause analysis
  • Verification of ARM-protocol based SoCs (AXI, AMBA, AHB, ACE)
  • Verification of SoCs with complex memory sub-systems (DDRxx)
  • SoC and IP connectivity
  • Control status registers
  • Closure and coverage
  • Clock domain crossing
  • X-propagation
  • Verification of designs including power-management structures

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TSMC absolutely did NOT halt 28nm production!

TSMC absolutely did NOT halt 28nm production!
by Daniel Nenni on 03-07-2012 at 6:18 pm
Categories: Foundries, TSMC

Once again industry professionals get duped! Tabloid journalism runs amok inside the semiconductor ecosystem! As if our industry does not face enough challenges, why are we wasting time on drivel like this? This is a TSMC 28nm wafer by the way and thousands of them are being shipped around the world, believe it.
 Continue reading “TSMC absolutely did NOT halt 28nm production!”

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CDNLive: two days of all things Cadence

CDNLive: two days of all things Cadence
by Paul McLellan on 03-07-2012 at 4:17 pm
Categories: Cadence, EDA

Next Tuesday and Wednesday, March 13-14th, is CDNLive in Silicon Valley at the DoubleTree Hotel (which I see we are now meant to call DoubleTree by Hilton, although I still have to think twice not to call it the Red Lion, the group whose CFO at one point was Ray Bingham who was CFO and then CEO of Cadence. Trivia fact for the day).

CDNlive has a new format and going forward it will be much more technically focused. In the early days of CDNLive, which was the Fister era, CDNlive was modeled on the Intel developer forum. But Cadence markets to engineers who want to know about technology and practical techniques. So most of the people at CDNLive are users and relatively few Cadence people. Of the 90 sessions taking place over the two days, 76 are user-driven.

There are 3 keynotes on the first day, starting at 10.30:

  • Lip-Bu Tan, Cadence CEO Challenges, opportunities and collaboration
  • Rick Cassidy, President of TSMC North America Life in the silicon century
  • Tom Lantzsch, Exec VP of ARM Corporate Development Your world at your fingertips

Following that at noon a buffet lunch is served in the expo hall where Cadence has a booth with 14 demos and partners from ANSYS to TSMC also have booths and demos. Lunch during the second day offers a chance to meet R&D engineers from Cadence.

Before the keynotes, and after lunch, and through all of the second day, there are 8 tracks of detailed technical presentations running in parallel. The tracks are:
[LIST=1]

  • Digital Design
  • Mixed-signal/Low Power
  • Custom
  • Verification
  • SoC/DIP
  • System/Software
  • System Verifcation
  • High Performance

    Companies presenting include Cadence (of course), TSMC, Qualcomm, Broadcom, IBM, Cisco, AMD, Xilinx, ARM, Rambus and many others. A lot of customers designing chips on the leading edge with stories from the trenches.

    At the end of the day, back to the expo for a reception from 5.45 to 7.30. Demos and drinks.

    More information about the conference is here.
    Registration is here, or if you really procrastinate you can register on the day.

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    Kathryn Kranen Interview in San Jose Mercury News

    Kathryn Kranen Interview in San Jose Mercury News
    by Paul McLellan on 03-07-2012 at 1:22 pm
    Categories: EDA

    There is an interview in the San Jose Mercury News with Kathryn Kranen, Jasper’s CEO. Of course the Mercury is a general newspaper and can’t expect most of its readership to have a clue what EDA is, never mind formal verification. It’s a similar problem to the one we all have when we try and explain to our families just what we do. Steve Johnson does his best to understand.

    Q: Say a company designs a new chip for an automobile. How would your formal-verification software prevent the design from having a glitch that blows a car fuse, for example?
    A: What we do is all mathematical. We can just say there is a rule, or it’s called a property, that this fuse should not blow. And then the software will automatically reverse engineer what conditions could cause that to fail. It tells you if you were driving in reverse while you moved your seat and shifted into park, the fuse will blow. It’s very reliable. It solves problems about connections inside the chip.

    I knew that Kathryn and her husband Kevin both had initial “K”. I didn’t know their kids did. I think sending lots of mail to “K. Kranen” could cause some fun.

    The article is here.

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    Clock Domain Crossing (CDC): Survey Says

    Clock Domain Crossing (CDC): Survey Says
    by Paul McLellan on 03-06-2012 at 11:30 pm
    Categories: EDA

    I had no idea that there was a clock domain crossing (CDC) linkedIn group but indeed there is. Richard Brabant has set up a survey to see which tools people are using.


    The graph is somewhat confusing since, for example, Cadence Conformal is currently at zero but has a significant looking bar. But far and away the market leader (in this very limited “market”) is Atrenta’s SpyGlass product, with Real Intent a comfortable second.

    If you click over to the survey and vote then you can see the current numbers since the graph I have is presumably already out of date.

    Details of SpyGlass CDC, Atrenta’s clock domain crossing verification tool, are here (or click on the banner at the bottom).

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    IC Custom IP Blocks – EM and IR Drop Effects

    IC Custom IP Blocks – EM and IR Drop Effects
    by Daniel Payne on 03-06-2012 at 5:33 pm
    Categories: EDA, Synopsys

    Designing custom IP blocks is a challenge at the transistor-level and I wanted to learn what the recommended methodology and EDA tool flow was at Synopsys. They have a webinar that you can register for and it takes 30 minutes to learn what they have to say, or you can read a White Paper. If you cannot spare that much time, then my summary should answer some of your initial questions in about 10 minutes.
    Continue reading “IC Custom IP Blocks – EM and IR Drop Effects”

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    Test Synopsys offensive in VIP and try the quiz

    Test Synopsys offensive in VIP and try the quiz
    by Eric Esteve on 03-06-2012 at 11:33 am
    Categories: EDA, IP, Synopsys

    I have recently blogged about Synopsys offensive in the Verification IP market. Did Synopsys again launched a new product, or announced a new acquisition? This would be a serious topic to blog, but today’s blog is closer to gaming than market analysis. Sometimes it’s good to have fun, even if the topic is serious! In fact, Synopsys has launched a quiz, the questions are centered about Verification and protocols: Ethernet, PCI Express, AXI4… I tried it, and I realized that I was certainly missing know how about these protocols… Do you want to check your VIP level of knowledge? Just go here!

    The above histogram is exhibiting a perfect Gaussian distribution, showing that the average player knows 50% of the right answer. Or, if you prefer, that half of the people who have tried the quiz have given a wrong answer once every two questions… If you plan to do this quiz, maybe you should review the protocol standards, listed in the picture below as well as the Discovery product brief. And keep in mind that the Discovery related questions have been created to highlight the advantages of the product (see my previous blog, or the list below), this may help you to correctly answer these questions.

    • Synopsys Discovery VIP speeds and simplifies verification of the most complex system-on-chip (SoC) designs.
    • Synopsys Discovery VIP offers greater performance, debug and coverage management features, ease-of-use and ease-of-integration for complex SoCs.
    • Synopsys Discovery VIP is written entirely in SystemVerilog, includes native support for UVM, VMM, and OVM, and is compatible with all related verification environments.
    • Synopsys Discovery VIP supports all major simulators.
    • Included with Discovery VIP, Protocol Analyzer enables engineers to quickly understand, identify and debug protocols in their designs.

    How did I score the quiz? That’s a very good question! To answer to it, I would say that I spend more time surfing the web for information, and blogging, than carefully reading the various protocol standard documentation. I hope it’s a fair answer!

    From Eric Esteve from IPnest