A growing number of reports highlight a class of design errors that is difficult to check using more traditional methods, and can potentially affect a wide range of IC designs, especially where high reliability is a must.By Matthew Hogan

Today’s IC designs are complex. They contain vast arrays of features and functionality in addition to multiple power domains required to reduce power consumption and improve design efficiency. With so much going on, design verification plays an important role in assuring that your design does what you intended.Often, verification will include simulations (for functional compliance), and extensive physical verification (PV) checks to ensure that the IC has been implemented correctly, including DRC, LVS, DFM and others. A growing number of reports highlight a class of design errors that is difficult to check using more traditional methods, and can potentially affect a wide range of IC designs, especially where high reliability is a must.

To address these types of design errors, electrical rule checking (ERC) has seen significant growth in recent years. Teams developing submicron, mixed-signal, or low-power devices used in mobile and other applications are particularly concerned about advanced ERC. This concern has lead to investments by circuit designers, CAD engineers, design project managers, verification engineers, and process modeling engineers to increase coverage, and by the EDA tool vendors to enable advanced checks and make describing the rules simpler. The investment has a large ROI because robust ERC reduces the number of die susceptible to catastrophic electrical failures during final testing, as well as premature failures in the field.

Electrical rules are relatively complex, non-standard, and growing in number and type, creating a need for a highly flexible, user-configurable tool. ERCs are important, but particularly challenging in designs with multiple voltage domains and mixed analog/digital circuits, such as low-power devices targeting mobile and other battery-powered applications.

Designs that incorporate multiple power domain checks are particularly susceptible to subtle design errors that are difficult to identify in the simulation space or with traditional PV techniques. Often these subtle errors don’t result in immediate part failure, but performance degradation over time. Effects such as Negative Bias Temperature Instability (NBTI) can lead to the threshold voltage of the PMOS transistors increasing over time, resulting in reduced switching speeds for logic gates [1] [2] [3], and Hot Carrier Injection (HCI), which alters the threshold voltage of NMOS devices over time [4]. Soft breakdown (SBD) [4] also contributes as a time-dependent failure mechanism, contributing to the degradation effects of gate oxide breakdown.

Some electrical rule checks are based on the netlist and include looking for floating devices, nets, or pins, detecting thin gates connected to excessive voltages, checking for violations of the maximum allowed number of series pass gates, and finding issues related to level shifter designs. Other checks are performed using geometric layout information, such as net area ratios for antenna rules, floating wells, and minimum “hot” NWELL width.

Topological ESD check:Device gates connected to I/O pads should be protected by resistor and turn-off MOS device.

An important application of ERC is verifying that electrostatic discharge (ESD) protection circuits are in place wherever the device is vulnerable, whether those circuits are included in the schematic and netlist or not. To ensure a robust design, the ERC tool must go beyond simple schematic or netlist-to-layout verification and recognize where ESD protection elements are needed, based on combined information from the netlist and the layout topology.

In multiple power domains, other precautions have to be considered. For example, IP reuse may require more robust rules to avoid device burnout at the system integration stage. This is particularly the case where an IP block is being re-targeted to a different process node or power domain [1]. The introduction of lower voltage power domains is also an area where IP reuse and the contribution to the overall reliability of the chip must be considered. Often, to attain lower voltage thresholds for lower power circuits, the oxide layer of a transistor is made thinner. While this has significant voltage and power benefits, there are areas of concern. One of these is when thin-oxide gates have paths to specific voltage rails. To avoid long term damage to the gate over a period of time, which results in performance degradation, the voltage rail must be carefully chosen. A previous implementation may have the gate tied at a voltage that is too high for the current use.

Successful integration of physical IP blocks requires knowledge of the design hierarchy as well as the structure of voltage domains and cell voltage constraints. Design hierarchy also comes into play when one set of rules is applied to upper layer interconnects and pad frames, while different rules are applied between blocks crossing multiple power domains.

In the figure below, we can see results from a check to verify that a signal net from one power domain does not directly cross into another. In this case, we would probably expect a level shifter or some other protection circuit to allow the safe passage of a signal from one power domain to another.

Topological ERC example that needs circuit identification programmable entry. Advanced ERC: Serially connected gates cannot be on different supplies or grounds.

As ERC becomes more critical to producing a reliable product, designers and engineers are constantly discovering new checks that they would like to make during verification. These checks are based on their accumulated knowledge and best practices of design groups; thus, there is no “standard” set of checks. Consequently, it is crucial that an ERC tool be easily programmable, allowing users to adapt it quickly to new checks as they become needed.

As an example of advanced ERC, the circuit below shows PMOS and NMOS thin-oxide gates with direct and indirect connections to power the domains VDD2 and VSS2. An indirect connection may be through another transistor, diode, resistor, or other circuit elements. These connections often form the basis of “missed” paths that are not readily identified during design reviews. This is particularly true if the indirect path is through a circuit elsewhere in the design hierarchy that is not obvious. The local power connections in the sub-circuit itself (VDD/VSS) are seen in the context of the larger design. The external connections to an otherwise verified IP block must be evaluated.

To show how designers can use new ERC verification tools we provide an example check based on Mentor Graphics’ Calibre® PERC product, which can be used to find design errors not identified by traditional PV tools. Typically Calibre PERC is used in combination with Calibre nmLVS allowing users to run multiple electrical rule checks independently or together, using either standard rules from the foundry, or their own custom rules. Users can insert electrical rule checks into their design flow with Calibre PERC as part of an integrated Calibre platform for cell, block, and full-chip verification. Combining rules expressed in SVRF and the TCL-based TVF language across all applications provides users with flexibility to meet the specific and evolving needs of their design teams, while ensuring compatibility with all foundries.

To identify thin-oxide gates at risk, designers could define a check in Calibre PERC expressed in pseudo code here for simplicity:
1) Identify power domains in the design
2) Identify which power domains are “not safe” for thin-oxide gates
3) Identify the specific device types and subtypes that corresponding to thin oxide MOS devices
4) Check the related “source”, “drain”, or “bulk” pin connection on these thin-oxide MOS devices to power domains
a) Evaluate both direct and indirect paths
b) Flag an error for this-oxide MOS connections that are to “not safe” power domains

In complex systems, it is not uncommon to have multiple power domains, which require complex design rules to determine which domains are safe, and under what conditions.

Thin-oxide gates with direct and indirect paths to VDD2/VSS2. These connections are made outside the sub-circuit.

Verification of bulk pin connectivity is particularly import for determining if a circuit is susceptible to these time related reliability issues. As shown below, an incorrect bulk connection may make this PMOS gate vulnerable to NBTI due to a high bulk voltage.

A Thin-oxide PMOS (Model: mos_lv) with a path to high voltage may lead to NBTI susceptibility

To learn more about reliability checking, download the white paper “Addressing Reliability and Circuit Verification Challenges with Calibre® PERC“. Also, visit my personal blog at http://blogs.mentor.com/matthew_hogan/.

References
[1] Hamed Abrishami, et. al., “NBTI-Aware Flip-Flop Characterization and Design”, GLSVLSI’08, May 4–6, 2008
[2] B.C. Paul, K. Kang, H. Kuflouglu, M. A. Alam and K. Roy, “Impact of NBTI on the temporal performance degradation of digital circuits,” Electron Device Letter, vol. 26, no. 8, pp. 560-562, Aug. 2005.
[3] Hong Luo, et. al., “Modeling of PMOS NBTI Effect Considering Temperature Variation”, 8th International Symposium on Quality Electronic Design (ISQED’07)
[4] Jin Qin, et. al., “SRAM Stability Analysis Considering Gate Oxide SBD, NBTI and HCI”, 2007 IIRW FINAL REPORT