Two More Transistor-Level Companies at DAC

Two More Transistor-Level Companies at DAC
by Daniel Payne on 07-02-2011 at 8:38 pm

In my rush on Wednesday at DAC I had almost over-looked the last two companies I talked with: Invarian and AnaGlobe. These last two I had hand-written notes on paper, so I just got to the bottom of my inbox tonight to write up the final trip reports.

Jens Andersen and Vladimir Schellbach gave me an overview of tools that perform temperature, package and analog layout analysis:

  • Models actual component temperature
  • Identifies electromigration
  • Finds hotspots
  • Solves full 3D heat transfer equation
  • Accounts for block layout impact
  • Accounts for power dissipation

The Invarian tool named InVar works with a SPICE simulator like Berkeley’s Analog Fast SPICE tool. They analyze both analog and digital design flows. The only other competitor in this space would be Gradient DA.

Watch this startup, even with under a dozen people in Moscow and Silicon Valley they have an interesting focus on temperature variation that the big four in EDA haven’t starting serving yet. Their IR drop and EM analysis have plenty of competitors.

How would you load an IC layout that was 180GB in size? At AnaGlobe they use the Thunder chip assembly tool and get the design loaded in under two hours. Yan Lin gave me a quick overview of their tools.

GOLF is a new PCell design environment based on OA.

PLAG is another OA tool for flat panel layout.

AnaGlobe is certainly a technology leader for large IC database assembly. Their GOLF tool competes with Virtuoso, Ciranova and SpringSoft. PLAG looks to have little competition. Big name design companies use AnaGlobe tools: Nvidia, Marvell, SMIC, AMCC.

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