So you’ve got questions about FD-SOI? For chip designers in Silicon Valley, there’s a great opportunity to get answers from some of the world’s leading design experts. It’s coming up fast: April 14th, the SOI Consortium is organizing a full day of FDSOI tutorials for chip designers. Bear in mind that … Read More
Tag: ulp
Designing for Ultra-Low Power? Easier with “CLICK” IP
Designing for ultra-low power will become the mantra for many of the new SoC designs, but the related SoC architecture can be very complex to handle. Make or buy is the project manager choice, but if you decide to ask for an expert advice before jumping start an ULP SoC design, attending thiswebinar from Dolphin Integration “The Proven… Read More
Dolphin Webinar “The proven recipe for uLP SoC”
Dolphin will hold a live webinar on November 15, 9:00 AM PST or November 22, 10:00 AM GMT. This webinar targets the SoC designers wanting to learn how to quickly implement ultra-low power (uLP) techniques, using proven recipes.… Read More
TSMC OIP: What to Do With 20,000 Wafers Per Day
Today it is TSMC’s OIP Ecosystem Innovation forum. This is an annual event but is also a semi-annual update on TSMC’s processes, investment, volume ramps and more. TSMC have changed the rules for the conference this year: they have published all the presentations by their partners/customers. Tom Quan of TSMC told… Read More
Older Nodes Get New Life With Ultra Low Power Variants for IoT
Ever since I can remember, and I’ve been in EDA since the early 80’s, new process development has largely focused on the latest nodes. Trailing nodes were quickly put into support mode. New nodes benefited the most from static and dynamic voltage reduction efforts, as well as improvements in flows and performance. Only a small number… Read More
Build Low Power IoT Design with Foundation IP at 40nm
In a power hungry world of semiconductor devices, multiple ways are being devised to budget power from system to transistor level. The success of IoT (Internet of Things) Edge devices specifically depend on lowest power, lowest area, optimal performance, and lowest cost. These devices need to be highly energy efficient for sustained… Read More
Can FD-SOI Change the Rule of Game?
It appears so. Why there is so much rush towards FD-SOI in recent days? Before talking about the game, let me reflect a bit on the FD-SOI technology first. The FD-SOI at 28nm claims to be the most power-efficient and lesser cost technology compared to any other technology available at that node. There are many other advantages from… Read More