The Intelligence Revolution: TSMC’s OIP Ecosystem Forges the Path to Trillion-Transistor AI Systems

The Intelligence Revolution: TSMC’s OIP Ecosystem Forges the Path to Trillion-Transistor AI Systems
by Kalar Rajendiran on 09-23-2026 at 2:00 pm

Broadest Portfolio of Silicon Validated IP

At the 2026 OIP Ecosystem Forum, the industry narrative shifted from incremental scaling to what TSMC defines as the “Intelligence Revolution.” Akin to the 18th-century Industrial Revolution which transitioned human physical labor to mechanical power, the current era is augmenting human ingenuity through … Read More


Podcast EP368: An Overview of TSMC Open Innovation Platform (OIP) event with Aveek Sarkar

Podcast EP368: An Overview of TSMC Open Innovation Platform (OIP) event with Aveek Sarkar
by Daniel Nenni on 09-23-2026 at 2:00 pm

Daniel is joined by Aveek Sarkar, who heads TSMC’s Ecosystem and Alliance Management Division. Along with his team, he is responsible for driving semiconductor design enablement in collaboration with the partner ecosystem through TSMC’s Open Innovation Platform® (OIP). Prior to TSMC, Aveek worked on chip designs at Sun Microsystems… Read More


Why ASML Is Racing to Build 110 EUV Machines

Why ASML Is Racing to Build 110 EUV Machines
by Daniel Nenni on 09-23-2026 at 6:00 am

Why ASML Is Racing to Build 110 EUV Machines

ASML is exploring how to produce more than 110 extreme ultraviolet lithography machines in 2028, reflecting the extraordinary investment flowing into artificial intelligence infrastructure. The Dutch semiconductor-equipment company expects to manufacture at least 80 EUV systems in 2027 and is considering another production… Read More


Comparison of TSMC CoWoS-S, CoWoS-R, and CoWoS-L

Comparison of TSMC CoWoS-S, CoWoS-R, and CoWoS-L
by Daniel Nenni on 09-22-2026 at 6:00 am

TSMC CoWos Packaging Comparison

Chip-on-Wafer-on-Substrate, commonly called CoWoS, is an advanced packaging platform developed by TSMC. It allows processors, chiplets, and high-bandwidth memory stacks to be integrated within a single package. CoWoS has become especially important for artificial-intelligence accelerators and high-performance computing… Read More


TSMC’s CoWoS Capacity to Double by 2028—and Rivals Will Still Win Orders

TSMC’s CoWoS Capacity to Double by 2028—and Rivals Will Still Win Orders
by Daniel Nenni on 09-18-2026 at 8:00 am

TSMC’s CoWoS Capacity to Double by 2028—and Rivals Will Still Win Orders

TSMC reportedly plans to double its Chip-on-Wafer-on-Substrate capacity from approximately 130,000 300mm-equivalent wafers per month at the end of 2026 to 260,000 by 2028. The estimate is not formal company guidance and should be treated as a supply-chain projection. Nevertheless, the direction is consistent with TSMC’s… Read More


Rethinking AI Chips: How VSORA Redesigned the Hardware That Runs AI

Rethinking AI Chips: How VSORA Redesigned the Hardware That Runs AI
by Lauro Rizzatti on 09-16-2026 at 6:00 am

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Instead of tweaking existing designs, VSORA built an AI chip from scratch to fix the real bottleneck: moving data fast enough to keep the math circuits busy.

There’s a version of the AI hardware story that everyone in the chip industry has heard a hundred times. A startup raises money on a clever chip design, promises to topple… Read More


UWB Without the Integration Headache: Ceva and LG Bring Precision to More Chips

UWB Without the Integration Headache: Ceva and LG Bring Precision to More Chips
by Daniel Nenni on 09-15-2026 at 8:00 am

UWB Without the Integration Headache Ceva and LG Bring Precision to More Chips

Ceva and LG Electronics have joined forces to remove one of the biggest obstacles to ultra-wideband adoption: integrating a complete radio, baseband and software stack into a production system-on-chip. Their joint platform combines Ceva-Waves UWB baseband intellectual property and software with an RF front end developed… Read More


ASML and TSMC’s 12-Inch Photomask Initiative: Technical Significance

ASML and TSMC’s 12-Inch Photomask Initiative: Technical Significance
by Daniel Nenni on 09-07-2026 at 11:00 pm

ASML and TSMC’s 12 Inch Photomask Initiative

ASML and TSMC’s proposed shift from 6-inch to 12-inch photomasks is an attempt to redesign a critical but often overlooked part of advanced semiconductor manufacturing. Photomasks are precision plates carrying the circuit patterns projected by a lithography scanner onto a silicon wafer. In extreme-ultraviolet lithography,… Read More


Comparing Advanced Packaging from TSMC, Intel Foundry, and Samsung Foundry

Comparing Advanced Packaging from TSMC, Intel Foundry, and Samsung Foundry
by Daniel Nenni on 09-06-2026 at 10:00 am

Advanced Chip Packaging Comparison INtel TSMC Samsung

Advanced semiconductor packaging has become essential to improving computing performance as conventional transistor scaling grows more difficult and expensive. Instead of manufacturing an entire processor as one large monolithic die, chipmakers can divide it into smaller chiplets and combine logic, memory, input/output… Read More


HBM’s Vertical Ascent: Why Packaging Is Becoming the Heart of AI Memory

HBM’s Vertical Ascent: Why Packaging Is Becoming the Heart of AI Memory
by Admin on 09-03-2026 at 6:00 am

HBM’s Vertical Ascent

SK hynix’s Hot Chips 2026 presentation explains how High Bandwidth Memory (HBM) is evolving to meet the extraordinary memory requirements of artificial intelligence. Its central message is that future progress will depend not only on better DRAM circuits but also on advanced packaging, denser vertical integration, improved… Read More