Huawei Can’t Shrink Its Chips, So It’s Folding Them

Huawei Can’t Shrink Its Chips, So It’s Folding Them
by Daniel Nenni on 08-27-2026 at 8:00 am

Huawei Can’t Shrink Its Chips, So It’s Folding Them

On May 25, Huawei semiconductor chief He Tingbo unveiled LogicFolding, an architecture intended to advance chip performance without relying on ever-smaller transistors. Presented alongside Huawei’s “Tau Scaling Law,” the approach prioritizes signal speed over transistor dimensions. It is a genuine engineering response… Read More


Europe OIP Ecosystem Workshop

Europe OIP Ecosystem Workshop
by Admin on 08-24-2026 at 12:15 am

Join Us to Connect, Collaborate, and Shape the Future of AI

Get ready to immerse yourself in the future of semiconductor design at the 2026 TSMC Global Open Innovation Platform® (OIP) Ecosystem Forum! This isn’t just an event—it’s the ultimate collaborative hub where the world’s leading technology pioneers gather to discuss… Read More


Japan OIP Ecosystem Workshop

Japan OIP Ecosystem Workshop
by Admin on 08-24-2026 at 12:06 am

Join Us to Connect, Collaborate, and Shape the Future of AI

Get ready to immerse yourself in the future of semiconductor design at the 2026 TSMC Global Open Innovation Platform® (OIP) Ecosystem Forum! This isn’t just an event—it’s the ultimate collaborative hub where the world’s leading technology pioneers gather to discuss… Read More


TSMC 2026 North America OIP Ecosystem Forum

TSMC 2026 North America OIP Ecosystem Forum
by Admin on 08-24-2026 at 12:04 am

Join Us to Connect, Collaborate, and Shape the Future of AI

Get ready to immerse yourself in the future of semiconductor design at the 2026 TSMC Global Open Innovation Platform® (OIP) Ecosystem Forum! This isn’t just an event—it’s the ultimate collaborative hub where the world’s leading technology pioneers gather to discuss… Read More


The Twelve-Month Rule Does Not Describe a New Fab

The Twelve-Month Rule Does Not Describe a New Fab
by Admin on 08-23-2026 at 10:00 am

capex to wafer starts lag

By Nikhil Shah

Capital spending is often treated as if it becomes semiconductor capacity about twelve months later. That can be a useful rule for equipment installed in an existing fab. It is a poor description of a new fab built from the ground up.

I tested the distinction using five advanced-node projects in the United States where… Read More


How TSMC Is Wiring the AI Era With Light

How TSMC Is Wiring the AI Era With Light
by Daniel Nenni on 08-21-2026 at 10:00 am

How TSMC Is Wiring the AI Era With Light

TSMC’s photonics strategy is centered on integrating optical input-output with advanced logic, rather than selling conventional optical transceivers as standalone products. The company is developing a silicon-photonics foundry platform and a packaging architecture called TSMC-COUPE, or Compact Universal Photonic … Read More


A 0.42-Nanometer Breakthrough From TSMC Could Push Transistors Beyond Silicon

A 0.42-Nanometer Breakthrough From TSMC Could Push Transistors Beyond Silicon
by Daniel Nenni on 08-14-2026 at 8:00 am

A 0.42 Nanometer Breakthrough Could Push Transistors Beyond Silicon

Researchers at National Yang Ming Chiao Tung University and TSMC Corporate Research engineered a 0.42-nanometer aluminum-oxide interface that protects electron transport in monolayer MoS₂ transistors while enabling strong gate control.

Silicon transistors are approaching physical limits that make each new generation… Read More


Intel and TSMC Take Different Paths to High-NA EUV

Intel and TSMC Take Different Paths to High-NA EUV
by Daniel Nenni on 08-07-2026 at 8:00 am

Intel TSMC HNA EUV 2026

Intel and TSMC are pursuing the same objective—manufacturing smaller, faster, and more energy-efficient semiconductors—but they have adopted different strategies for advanced lithography. Intel moved early to develop High-Numerical-Aperture Extreme Ultraviolet lithography, commonly called High-NA EUV, while TSMC… Read More