Nine Cost Considerations to Keep IP Relevant –Part2

Nine Cost Considerations to Keep IP Relevant –Part2
by Pawan Fangaria on 10-06-2015 at 7:00 am

In the first part of this article I wrote about four types of costs which must be considered when an IP goes through design differentiation, customization, characterization, and selection and evaluation for acquisition. In this part of the article, I will discuss about the other five types of costs which must be considered to enhance… Read More


Leveraging Synopsys’ Lynx Design System for SoC Designs on Advanced Nodes

Leveraging Synopsys’ Lynx Design System for SoC Designs on Advanced Nodes
by Pawan Fangaria on 10-04-2015 at 7:00 am

There was a time when design goals were decided in the beginning, targeted on a particular technology node, design planning done for the same, and implementation done through point tools connected indesign flows customized according to the design. It’s no longer the case for modern SoC designs; there are multiple technology … Read More


Automotive MCU code fault-busting with vHIL

Automotive MCU code fault-busting with vHIL
by Don Dingee on 09-30-2015 at 7:00 pm

With electronic and software content in vehicles skyrocketing, and the expectations for flawless operation getting larger, the need for system-level verification continues to grow. Last month, we looked at a Synopsys methodology for virtual hardware in the loop, or vHIL… Read More


Nine Cost Considerations to Keep IP Relevant

Nine Cost Considerations to Keep IP Relevant
by Pawan Fangaria on 09-27-2015 at 12:00 pm

It’s about 15 years the concept of IP development and its usage took place. In the recent past the semiconductor industry witnessed start of a large number of IP companies across the globe. However, according to Gary Smith’s presentation before the start of 52[SUP]nd[/SUP] DAC, IP business is expected to remain stagnant for next… Read More


A Brief History of FPGA Prototyping

A Brief History of FPGA Prototyping
by Paul McLellan on 09-25-2015 at 7:00 am

Verifying chip designs has always suffered from a two-pronged problem. The first problem is that actually building silicon is too expensive and too slow to use as a verification tool (when it happens, it is not a good thing and is called a “re-spin”). The second problem is that simulation is, and has always been, too slow.

When Xilinx… Read More


We’re Number Two, We Try Harder

We’re Number Two, We Try Harder
by Paul McLellan on 09-19-2015 at 7:00 am

One of the big surprises I got at Synopsys’ ARC conference is that ARC is #2 in terms of share of licensed microprocessor shipments. I think most readers of Semiwiki would know ARM is #1 but would guess that MIPS (now owned by Imagination Technologies) is #2. But you’d be wrong, ARC is over twice as big.

Last week Synopsys… Read More


FPGA Prototyping: From Homebrew to Integrated Solutions

FPGA Prototyping: From Homebrew to Integrated Solutions
by Paul McLellan on 09-16-2015 at 7:01 am

Years ago, when FPGA prototyping started, there were no solutions that you could go out and buy and everything was created as a one-off: buy some FPGAs or an FPGA-based board, and put it all together. It was a lot of effort, nobody really knew in advance how long it would take, there was very limited visibility for debug and the whole … Read More


Michael Sanie Plays the Synopsys Verification Variations

Michael Sanie Plays the Synopsys Verification Variations
by Paul McLellan on 08-31-2015 at 7:00 am

I met Michael Sanie last week. He is in charge of verification marketing at Synopsys. I know him well since he worked for me at both VLSI Technology and Cadence. In fact his first job out of college was to take over support of VLSIextract (our circuit extractor), which I had written. But we are getting ahead.

Michael was born in Iran and… Read More


Simulating to a fault in automotive and more

Simulating to a fault in automotive and more
by Don Dingee on 08-30-2015 at 12:00 pm

We’re putting the finishing touches on Chapter 9 of our upcoming book on ARM processors in mobile, this chapter looking at the evolution of Qualcomm. One of the things that made Qualcomm go was their innovative use of digital simulation. First, simulation proved out the Viterbi decoder (which Viterbi wasn’t convinced had a lot … Read More


Older Nodes Get New Life With Ultra Low Power Variants for IoT

Older Nodes Get New Life With Ultra Low Power Variants for IoT
by Tom Simon on 08-20-2015 at 12:00 pm

Ever since I can remember, and I’ve been in EDA since the early 80’s, new process development has largely focused on the latest nodes. Trailing nodes were quickly put into support mode. New nodes benefited the most from static and dynamic voltage reduction efforts, as well as improvements in flows and performance. Only a small number… Read More