Optimizing SRAM IP for Yield and Reliability

Optimizing SRAM IP for Yield and Reliability
by Daniel Payne on 08-31-2015 at 12:00 pm

My IC design career started out with DRAM at Intel, and included SRAM embedded in GPUs, so I recall some common questions that face memory IP designers even today, like:

  • Does reading a bit flip the stored data?
  • Can I write both 0 and 1 into every cell?
  • Will read access times be met?
  • While lowering the supply voltage does the cell data retain?
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Jen-Tai Hsu Joins Kilopass and Looks to the Future of Memories

Jen-Tai Hsu Joins Kilopass and Looks to the Future of Memories
by Paul McLellan on 08-18-2015 at 7:00 am

Kilopass has a new VP of engineering, Jen-Tai Hsu. I sat down with him last week to find out where he came from and where he and Kilopass are going.

He grew up in Taiwan and went to National Taiwan University where he studied electrical engineering. Then he came to the US and went to Case Western Reserve University to get a masters degree,… Read More


Ultra-low Power IP for Wearables

Ultra-low Power IP for Wearables
by Paul McLellan on 07-28-2015 at 7:00 am

Wearables and the Internet of Things (IoT) in general are all about low power. Everyone must have read (or even experienced) the phenomenon of putting something like a Fitbit on and then after a short period leaving it in a drawer or putting it to recharge and forgetting about it for weeks. The longer devices can last the more likely… Read More


What Can Accelerate 3D Semiconductor Manufacturing?

What Can Accelerate 3D Semiconductor Manufacturing?
by Pawan Fangaria on 10-12-2013 at 9:30 am

In the beginning of this decade there was a lot of buzz around 3D chip manufacturing. Many EDA tools were developed to facilitate semiconductor designs in 3D space. Naturally, we are moving to the edge on 2D without much room to further squeeze transistors and interconnect. However, lately I haven’t heard much about 3D products.… Read More


Robust Design <- Robust Flow <- Robust Tools

Robust Design <- Robust Flow <- Robust Tools
by Pawan Fangaria on 08-10-2013 at 6:00 pm

I could have written the sequence of the title in reverse order, but no, design is the one which initiates the need of a particular flow and the flow needs support of EDA tools to satisfy that need. It’s okay if the design is small; some manual procedures and workarounds/scripts may be able to perform certain jobs. However, as the design… Read More


TSMC ♥ Berkeley Design Automation

TSMC ♥ Berkeley Design Automation
by Daniel Nenni on 05-30-2013 at 11:00 am

As I mentioned in BDA Takes on FinFET Based Memories with AFS Mega:

Is AFS Mega real? Of course it is, I’m an SRAM guy and I worked with BDA on this product so I know. But don’t take my word for it, stay tuned for endorsements from the top SRAM suppliers around the world.

Here is the first customer endorsement from the #1 foundry.… Read More


BDA Takes on FinFET-based Memories with AFS Mega

BDA Takes on FinFET-based Memories with AFS Mega
by Daniel Nenni on 05-29-2013 at 12:00 pm

Berkeley Design Automation today announced the first silicon-accurate circuit simulation for mega-scale arrays like memories and CMOS image sensors. If this tool lives up to its claims, it is going to be a big deal for FinFET-based circuits, Memory designers are rightly worried about having the accuracy necessary to include… Read More


How much SRAM proportion could be integrated in SoC at 20 nm and below?

How much SRAM proportion could be integrated in SoC at 20 nm and below?
by Eric Esteve on 11-20-2012 at 4:45 am

Once upon a time, ASIC designers were integrating memories in their design (using a memory compiler being part of the design tools provided by the ASIC vendor), then they had to make the memory observable, controllable… and start developing the test program for the function, not a very enthusiastic task (“AAAA” and “5555” and other… Read More


Current Embedded Memory Solutions Are Inadequate for 100G Ethernet

Current Embedded Memory Solutions Are Inadequate for 100G Ethernet
by Sundar Iyer on 10-01-2012 at 7:00 pm

With an estimated 7 billion connected devices, the demand for rich content, including video, games, and mobile apps is skyrocketing. Service providers around the globe are scrambling to transform their networks to satisfy the overwhelming demand for content bandwidth. Over the next few years, they will be looking to network… Read More


The Business Case for Algorithmic Memories

The Business Case for Algorithmic Memories
by Adam Kablanian on 08-20-2012 at 11:00 am

Economic considerations are a primary driver in determining which technology solutions will be selected, and how they will be implemented in a company’s design environment. In the process of developing Memoir’s Algorithmic Memory technology and our Renaissance product line, we have held fast to two basic premises: Our technology… Read More