Transforming the electronics ecosystem with the component digital thread

Transforming the electronics ecosystem with the component digital thread
by Kalar Rajendiran on 06-27-2023 at 6:00 am

Complexity from Disaggregated Electronics Value Chain

The transformation of the vertically integrated electronics value chain to a disaggregated supply chain has brought tremendous value to the electronics industry and benefits to the consumers. This transformation has driven the various players to become highly specialized in order to support the market trends and demands … Read More


Getting the most out of a shift-left IC physical verification flow with the Calibre nmPlatform

Getting the most out of a shift-left IC physical verification flow with the Calibre nmPlatform
by Peter Bennet on 06-08-2023 at 10:00 am

Correct Verify Debug

Who first came up with this term shift-left ? I’d assumed Siemens EDA as they use it so widely. But their latest white paper on the productivity improvements possible with shift-left Calibre IC verification flows puts the record straight: a software engineer called Larry Smith bagged the naming rights in a 2001 paper (leapfrogging… Read More


Securing PCIe Transaction Layer Packet (TLP) Transfers Against Digital Attacks

Securing PCIe Transaction Layer Packet (TLP) Transfers Against Digital Attacks
by Kalar Rajendiran on 06-01-2023 at 10:00 am

PCIe TLP Encryption

In the fast moving world of data communications, the appetite for high speed data transfers is accompanied by a growing need for data confidentiality and integrity. The wildly popular PCIe interface standard for connectivity has not only been increasing data transfer rates but has also introduced an Integrity and Data Encryption… Read More


Emerging Stronger from the Downturn

Emerging Stronger from the Downturn
by Kalar Rajendiran on 05-16-2023 at 6:00 am

Full Flow from HL Synthesis through to GDSII Accelerates the creation of AI IP

It was refreshing to hear a talk focused on emerging stronger from the downturn when the news and media are focused on the gloom. At the recent Siemens EDA User2User conference, Joe Sawicki, executive vice president, IC, gave an uplifting keynote talk to the audience. He highlighted a secular growth trend happening in the semiconductor… Read More


Chiplet Modeling and Workflow Standardization Through CDX

Chiplet Modeling and Workflow Standardization Through CDX
by Kalar Rajendiran on 05-15-2023 at 6:00 am

Chiplet Integration Workflow

Chiplet is a hot topic in the semiconductor world these days. So much so that if one hasn’t heard that term, the person must be living on a very isolated islet. Humor aside, products built using chiplets-based methodology have been in existence for at least some years now. Companies such as Intel, AMD, Apple and others have integrated… Read More


Tessent SSN Enables Significant Test Time Savings for SoC ATPG

Tessent SSN Enables Significant Test Time Savings for SoC ATPG
by Kalar Rajendiran on 05-08-2023 at 6:00 am

Pattern Generation Block Level ATPG Flow

SoC test challenges arise due to the complexity and diversity of the functional blocks integrated into the chip. As SoCs become more complex, it becomes increasingly difficult to access all of the functional blocks within the chip for testing. SoCs also can contain billions of transistors, making it extremely time-consuming… Read More


Achieving Optimal PPA at Placement and Carrying it Through to Signoff

Achieving Optimal PPA at Placement and Carrying it Through to Signoff
by Kalar Rajendiran on 05-02-2023 at 10:00 am

PreRoute PostRoute Net Length Correlation

Performance, Power and Area (PPA) metrics are the driving force in the semiconductor market and impact all electronic products that are developed. PPA tradeoff decisions are not engineering decisions, but rather business decisions made by product companies as they decide to enter target end markets. As such, the sooner a company… Read More


Mitigating the Effects of DFE Error Propagation on High-Speed SerDes Links

Mitigating the Effects of DFE Error Propagation on High-Speed SerDes Links
by Kalar Rajendiran on 04-18-2023 at 10:00 am

Pre and Post FEC BER as FEC Matrix size Reduces

As digital transmission speeds increase, designers use various techniques to improve the signal-to-noise ratio at the receiver output. One such technique is the Decision Feedback Equalizer (DFE) scheme, commonly used in high-speed Serializer-Deserializer (SerDes) circuits to mitigate the effects of channel noise and … Read More


Building better design flows with tool Open APIs – Calibre RealTime integration shows the way forward

Building better design flows with tool Open APIs – Calibre RealTime integration shows the way forward
by Peter Bennet on 12-22-2022 at 10:00 am

calibre real time digital and custom

You don’t often hear about the inner workings of EDA tools and flows – the marketing guys much prefer telling us about all the exciting things their tools can do rather than the internal plumbing. But this matters for making design flows – and building these has largely been left to the users to sort out. That’s an increasing challenge… Read More


Calibre: Early Design LVS and ERC Checking gets Interesting

Calibre: Early Design LVS and ERC Checking gets Interesting
by Peter Bennet on 11-22-2022 at 6:00 am

fig1

The last thing you want when taping out a design is to hit large numbers of violations in signoff checks that could have been flushed out and resolved in earlier flow iterations. For implementation flows (floorplanning, synthesis, place and route), it’s usual to do a lot of flow flushing work early in the design cycle and iteratively… Read More