TSMC OIP: Registration Open

TSMC OIP: Registration Open
by Paul McLellan on 09-06-2014 at 9:00 am

It’s that time of year again! The 4th TSMC Open Innovation Platform Ecosystem Forum is coming up on September 30th. As usual it is in the San Jose conference center. The TSMC OIP Ecosystem Forum brings together TSMC’s design ecosystem companies and their customers to share real case solutions to today’s design challenges.… Read More


SmartScan Addresses Test Challenges of SoCs

SmartScan Addresses Test Challenges of SoCs
by Pawan Fangaria on 09-04-2014 at 4:00 pm

With advancement of semiconductor technologies, ever increasing sizes of SoCs bank on higher densities of design rather than giving any leeway towards increasing chip area and package sizes; a phenomenon often overlooked. The result is – larger designs with lesser number of pins bonded out of ever shrinking package sizes;… Read More


Design Collaboration across Multiple Sites

Design Collaboration across Multiple Sites
by Pawan Fangaria on 09-02-2014 at 12:00 pm

Any SoC or IC design project, whether implemented at the same design site or multiple sites requires some data management tools to manage things such as a central data repository, revision management of files, etc., for effective co-ordination of work among different team members. Given the challenge of meeting the shrinking… Read More


Know All About ESD and Save Your Chips & Systems

Know All About ESD and Save Your Chips & Systems
by Pawan Fangaria on 08-24-2014 at 7:30 pm

In this age of electronics, especially with so many different types of human held devices and more upcoming wearable devices, it’s utmost important to protect the massive circuitry inside those tiny parts in the devices from ESD related failures. The protection needs to happen at all stages – cells inside the chips, package… Read More


Crossfire – Your partner for IP development, what’s new?

Crossfire – Your partner for IP development, what’s new?
by Pawan Fangaria on 08-21-2014 at 4:00 pm

As the SoCs and IPs grow in sizes and complexities, the number of formats, databases, libraries of standard cells and IOs also increase. It becomes a clumsy task to check every cell in a library, its consistency among various format with respect to functionality, timing, naming, labels and so on, and its complex physical properties… Read More


Synopsys Earnings

Synopsys Earnings
by Paul McLellan on 08-21-2014 at 12:00 pm

The perfect quarterly results are to slightly beat the consensus for earnings and profit, and not say anything negative about guidance for the upcoming quarter. Synopsys delivered all that with their latest quarter yesterday. Revenue was $521M versus $483M last year, giving solid growth of over 8%. Non-GAAP earnings per share… Read More


What Comes After FinFET?

What Comes After FinFET?
by Paul McLellan on 08-10-2014 at 11:01 pm

So what comes after FinFETs? At 14/16nm (or 22nm if you are Intel) we had FinFET transistors, where the channel was no longer planar but stuck out of the wafer vertically, and the gate wrapped around it on 3 sides. The key thing that made FinFET transistors attractive was that the channel was thin so that the gate controlled it well. … Read More


Semiconductor Revenue Trends

Semiconductor Revenue Trends
by Peter Gasperini on 08-10-2014 at 9:00 am


Image Source: Wikipedia

Nescire autem quid ante quam natus sis acciderit, id est semper esse puerum. (Not to know what happened before you were born is to remain forever a child.)Cicero

2014 is destined to be a pivotal year for Silicon Valley and High Tech in general. End user markets have been stagnating or declining over the last… Read More


The Carrington Event

The Carrington Event
by Paul McLellan on 08-05-2014 at 7:01 am

Back in the pre-SemiWiki days when I had the EdaGrafitti blog I wrote about the Carrington event. This was a solar storm in 1859 that lasted for several days. On September 1st there was a coronal mass ejection (CME) traveling directly towards earth. Normally such an event would take several days to reach earth but an earlier ejection… Read More


eSilicon and the Ten Minute Quote

eSilicon and the Ten Minute Quote
by Paul McLellan on 08-01-2014 at 8:01 am

One of the challenges in bringing a design into production is getting a quote that includes all the various stages of the process. The quote cycle typically takes a couple of weeks. It is also pretty wasteful. A typical design might be quoted by 3 manufacturers and so 2 out of 3 quotes are wasted expense because the design is lost to a … Read More