Parasitic Debugging in Complex Design – How Easy?

Parasitic Debugging in Complex Design – How Easy?
by Pawan Fangaria on 01-23-2014 at 9:00 am

When we talk about parasitic, we talk about post layout design further expanded in terms of electrical components such as resistances and capacitances. In the semiconductor design environment where multiple parts of a design from different sources are assembled together into highly complex, high density SoC, imagine how complex… Read More


Smart Clock Gating for Meaningful Power Saving

Smart Clock Gating for Meaningful Power Saving
by Pawan Fangaria on 01-21-2014 at 5:30 am

Since power has acquired a prime spot in SoCs catering to smart electronics performing multiple jobs at highest speed; the semiconductor design community is hard pressed to find various avenues to reduce power consumption without affecting functionality and performance. And most of the chips are driven by multiple clocks that… Read More


Managing Heat for System Reliability

Managing Heat for System Reliability
by Pawan Fangaria on 01-17-2014 at 8:30 am

In most of the electronic equipments, semiconductor chips are a major source of heat generation. And in semiconductor designs several hardware and software techniques are being used to contain power dissipation; a major cause for heat. However due to multiple functionality being squeezed into small form factors, we continue… Read More


How to Develop Accurate Yet High Performance Models

How to Develop Accurate Yet High Performance Models
by Pawan Fangaria on 01-13-2014 at 12:00 pm

In today’s environment of semiconductor design, SoCs are crammed with various IPs with multiple functionalities and processors integrated together. In such an event it has become necessary to model the system and verify on Virtual Platform before getting into actual design and fabrication. And that requires modelling of each… Read More


Migrating SOCs from 8051 to 32-bits

Migrating SOCs from 8051 to 32-bits
by Daniel Nenni on 01-12-2014 at 10:00 pm

The 8051 processor has been widely used in many embedded applications over the past 30 years. While the 8051 core is small and simple-to-use, the newest generation of consumer electronics being developed today often require more than the 8051 MCU can reasonably deliver. New SOC applications such as flash drives, power managementRead More


How to Optimize Analog IPs for High-end SoCs?

How to Optimize Analog IPs for High-end SoCs?
by Pawan Fangaria on 01-07-2014 at 12:00 pm

Gone are the days when analog design had its sweet space on a single chip. However, it’s the main driver in this new electronic world which is geared by Internet-of-Things, wireless, mobile, remote control and so on. How does an electronic device sense a touch by human, motion, temperature, sound etc.? It’s the analog circuitry … Read More


Quick MEMS Development Through Virtual Fabrication

Quick MEMS Development Through Virtual Fabrication
by Pawan Fangaria on 01-01-2014 at 7:00 am

The design and manufacture of MEMS is very different and in many ways more complex process than even the most advanced ICs. MEMS involve multiple degrees of freedom (i.e. the device to exhibit different characteristics under different physical state, motion or mechanics), making fabrication of MEMS extremely complex; and hence… Read More


Highest Test Quality in Shortest Time – It’s Possible!

Highest Test Quality in Shortest Time – It’s Possible!
by Pawan Fangaria on 12-26-2013 at 10:30 am

Traditionally ATPG (Automatic Test Pattern Generation) and BIST (Built-In-Self-Test) are the two approaches for testing the whole semiconductor design squeezed on an IC; ATPG requires external test equipment and test vectors to test targeted faults, BIST circuit is implemented on chip along with the functional logic of IC.… Read More


DAC 2014: Designer Track/IP Call for Submissions

DAC 2014: Designer Track/IP Call for Submissions
by Daniel Nenni on 12-17-2013 at 8:00 pm

Yes, it is that time of year again, DAC is coming and it is in San Francisco so you can bet we will break attendance records, absolutely. I would like to call on ALL semiconductor IP companies to exhibit this year. IP is the center of the semiconductor design universe, DAC is the premier semiconductor design event, and San Francisco … Read More


Taming The Interconnect In Real World For SoCs

Taming The Interconnect In Real World For SoCs
by Pawan Fangaria on 12-13-2013 at 1:30 pm

Interconnect plays a significant role in the semiconductor design of a SoC; if not architected and handled well, it can lead to an overdesigned SoC impacting on its power, performance and area. Since a SoC generally contains multiple IPs requiring different data paths to satisfy varying latency and performance cycles, it has … Read More