Podcast EP63: The growing importance of interconnect architecture

Podcast EP63: The growing importance of interconnect architecture
by Daniel Nenni on 02-18-2022 at 10:00 am

Dan and Mike are joined by Matt Burns, technical marketing manager at Samtec. Matt focuses on why interconnect architecture has become so important for state-of-the-art system designs. The markets that are driving these requirements, along with the challenges and how to address them are provided.

The discussion concludes… Read More


Samtec Dominates DesignCon 2021

Samtec Dominates DesignCon 2021
by Mike Gianfagna on 08-15-2021 at 6:00 am

Samtec Dominates DesignCon 2021

DesignCon has grown over the years to become a true system design show. The show’s tagline is WHERE THE CHIP MEETS TO BOARD. This is just the beginning. Besides the chip and the board there are all the challenges, opportunities, and options to get signals reliably propagated throughout the entire system. Power, signal integrity,… Read More


Electronic Systems SI/IP Forum

Electronic Systems SI/IP Forum
by Daniel Nenni on 04-06-2021 at 6:39 am

Title: KEYNOTE: Is Power Integrity the New Black Magic?

Date: Thursday, April 22, 2021

Time: 01:00 PM Eastern Daylight Time

Duration: 1 hour

Summary

Electronic Systems SI/PI Forum

KEYNOTE: Is Power Integrity the New Black Magic?

Sponsored by: Cadence

Presented by: Istvan Novak, Principal Signal and Power Integrity Engineer,

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Podcast EP7: Signal Integrity and Killer Robots

Podcast EP7: Signal Integrity and Killer Robots
by Daniel Nenni on 02-12-2021 at 10:00 am

Dan and Mike are joined by Matt Burns, technical marketing manager at Samtec. Matt discusses the signal integrity challenges faced by system designers. The materials and protocols used for channels on a board, between boards on a rack and even between racks are discussed. Matt also touches on the work Samtec is doing with BattleBots.… Read More


S2C Raises the Bar for High Capacity, High-Performance FPGA Prototyping

S2C Raises the Bar for High Capacity, High-Performance FPGA Prototyping
by Daniel Nenni on 12-29-2020 at 10:00 am

Logic Matrix

It should come as no surprise that S2C would step out in front with a high-density FPGA prototyping hardware platform for users who would like to scale to large numbers of FPGAs and high performance.  That’s exactly what they have done with their new Prodigy Logic Matrix family of FPGA prototyping products that S2C announced in December. … Read More


How Samtec Puts the Customer First

How Samtec Puts the Customer First
by Mike Gianfagna on 08-05-2020 at 10:00 am

Samtec SnapEDA

An exceptional customer experience starts before the sale. Successful companies realize it never ends. Dedicated post-sales support and a robust ecosystem for aftermarket product extensions are ingredients that tend to delight the customer. These comments are relevant in the consumer sector, but they apply to high tech as… Read More


Trace Design for Crosstalk Reduction

Trace Design for Crosstalk Reduction
by admin on 06-23-2020 at 3:58 pm

Trace Design for Crosstalk Reduction
Presented by: Scott McMorrow

Returning to basics, we’ll investigate the relationship of trace geometry to crosstalk in interconnect design, and draw some conclusions based on system constraints. Microstrip, stripline, and dual-stripline layer geometries will be examined,

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Welcome Samtec and System Design on SemiWiki

Welcome Samtec and System Design on SemiWiki
by Mike Gianfagna on 06-08-2020 at 10:00 am

Samtec Cables in Action

I always enjoy welcoming new corporate members to the SemiWiki platform. Each company brings new technology, a different perspective and the opportunity for the SemiWiki community to hear about another aspect of chip design and manufacturing. But this introduction is different. This time, a new corporate member is opening … Read More


eSilicon’s Latest SerDes Solution is Here – And It Took A Village

eSilicon’s Latest SerDes Solution is Here – And It Took A Village
by Randy Smith on 07-22-2019 at 10:00 am

I recently watched a webinar given by eSilicon about its project to enhance its licensable solution for 56 and 112 Gigabit per second PAM4 & NRZ DSP-based SerDes family in 7nm. I am sure it was complicated enough to coordinate a webinar with a host, a moderator, and three different technical presenters – however when we are talking… Read More


eSilicon Bucking the Trend at OFC with 7nm SerDes

eSilicon Bucking the Trend at OFC with 7nm SerDes
by Daniel Nenni on 03-11-2019 at 8:00 am

A recent press release from eSilicon caught my eye. The company has been touting their 7nm SerDes quite a bit lately – reach, power, flexibility, things like that. While those capabilities are important, any high-performance chip needs to work in the context of the system, which usually contains technology from multiple sources.… Read More