Earlier this week I moderated a webinar at Sonics entitled NoC 102: Using SonicsGN to Address Low Power Requirements. Drew Wingard, the CTO of Sonics, presented it. It goes without saying that power is a major concern in SoC design, not just with chips for battery powered devices but also tethered devices. A major cost of ownership… Read More
Tag: power
Temperature Monitoring IP to Revamp SoCs
With increasing density and functionality of chips at extremely thin silicon and metal layers, temperature has become critical. The temperature situation can become worse with wireless enabled 24/7 power-on devices. In such a scenario, a device must manage its thermal profile dynamically to keep the temperature within tolerable… Read More
Analyzing Power Nets
One of the big challenges in a modern SoC is doing an accurate analysis of the power nets. Different layers of metal have very different resistance characteristics (since they vary so much in width and height). Even vias can cause problems due to high resistance. Typically power is distributed globally on high-level metal layers,… Read More
Components for Wearables, Making the IoT Real
The screenwriter William Goldman is famous for saying that in Hollywood “Nobody knows anything.” Meaning that there is simply no way for any of the people involved to be able to predict which movies will turn out to be hits and which will be flops. I think the internet of things (IoT) is going to be like that. There will … Read More
How to Optimize for Power at RTL
Last week I was traveling in Munich attending the MunEDA User Group meetingso I missed a live webinar on the topic of optimizing for power at RTL. I finally got caught up in my email this week and had time to view this 47 minute webinar, presented by Guillaume Boilletof Atrenta. He recommended using a combination of automatic, semi-automatic… Read More
Solution for PI, TI & SI Issues in 3D-ICs
As we move towards packing more and more functionalities and increasing densities of SoCs, the power, thermal and signal integrity issues keep on rising. 3D-IC is a great concept to stack multiple dies on top of each other vertically. While it brings lot of avenues to package dies with multiple functions together, it has challenges… Read More
Simulation and Analysis of Power and Thermal Management Policies
Earlier this month I blogged about Power Management Policies for Android Devices, so this blog is part two in the series and delves into the details of using ESL-level tools for simulation and analysis. The motivation behind all of this is to optimize a power management system during the early design phase, instead of waiting until… Read More
Power Management Policies for Android Devices
I’ll never forget the shock when I upgraded from a Feature Phone to my first Android-powered SmartPhone, because all of a sudden my battery life went from 6 days down to only 1 day between charges. As a consumer, I really want my battery to last much longer than one day, so the race is on for mobile phone companies to design their… Read More
A Complete Scalable Solution for IP Signoff
In an SoC world driven by IP, where an SoC can have hundreds of IP (sourced not only from 3[SUP]rd[/SUP] party but also from internal business units which can have a lot of legacy) integrated together, it has become essential to have a comprehensive and standard method to verify and signoff the IP. Additionally, these checks must … Read More
FinFET Design for Power, Noise and Reliability
IC designers have been running analysis tools for power, noise and reliability for many years now, so what is new when you start using FinFET transistors instead of planar transistors? Calvin Chow from ANSYS (Apache Design) presented on this topic earlier in the summer through a 33 minutewebinar that has been archived. There is… Read More