On-Chip Networks at the Bleeding Edge of ML

On-Chip Networks at the Bleeding Edge of ML
by Bernard Murphy on 11-29-2018 at 7:00 am

I wrote a while back about some of the more exotic architectures for machine learning (ML), especially for neural net (NN) training in the data center but also in some edge applications. In less hairy applications, we’re used to seeing CPU-based NNs at the low end, GPUs most commonly (and most widely known) in data centers as the workhorse… Read More


Supporting ASIL-D Through Your Network on Chip

Supporting ASIL-D Through Your Network on Chip
by Bernard Murphy on 09-20-2018 at 7:00 am

The ISO 26262 standard defines four Automotive Safety Integrity Levels (ASILs), from A to D, technically measures of risk rather than safety mechanisms, of which ASIL-D is the highest. ASIL-D represents a failure potentially causing severe or fatal injury in a reasonably common situation over which the driver has little control.… Read More


Netspeed and NSITEXE talk about automotive design trends at 55DAC

Netspeed and NSITEXE talk about automotive design trends at 55DAC
by Tom Simon on 08-02-2018 at 12:00 pm

DAC is where both sides of the design equation come together for discussion and learning. This is what makes attending DAC discussion panels so interesting; you are going to hear from providers of tools, methodologies and IP as well as those who need to use them to deliver working solutions. There are few places where the interplay… Read More


Safety in the Interconnect

Safety in the Interconnect
by Bernard Murphy on 04-26-2018 at 7:00 am

Safety is a big deal these days, not only in automotive applications, but also in critical infrastructure and industrial applications (the power grid, nuclear reactors and spacecraft, to name just a few compelling examples). We generally understand that functional blocks like CPUs and GPUs have to be safe, but what about the … Read More


Machine Learning Neural Nets and the On-Chip Network

Machine Learning Neural Nets and the On-Chip Network
by Bernard Murphy on 03-15-2018 at 7:00 am

Machine learning (ML), and neural nets (NNs) as a subset of ML, are blossoming in all sorts of applications, not just in the cloud but now even more at the edge. We can now find them in our phones, in our cars, even in IoT applications. We have all seen applications for intelligent vision (e.g. pedestrian detection) and voice recognition… Read More


CES: An Exhibitor’s Takeaway

CES: An Exhibitor’s Takeaway
by Bernard Murphy on 02-06-2018 at 7:00 am

There are few tech promises these days as prominent as those surrounding driverless cars (trucks, buses, …). But thanks to always-on media amplifiers, it’s not always easy to separate potential from reality. I recently talked to Kurt Shuler, VP Marketing at Arteris, who shared his view after returning from this year’s CES. Kurt… Read More


AI Based Software Designing AI Based Hardware – Autonomous Automotive SoC Platform

AI Based Software Designing AI Based Hardware – Autonomous Automotive SoC Platform
by Mitch Heins on 10-10-2017 at 12:00 pm


For those of you who missed the NetSpeed Systems, Imagination Technologies webinar, “Alexa, can you help me build a better SoC”, you’ll be happy to hear that the session was recorded and can still be viewed (see link at the bottom of this page). I’ll warn you now however, that this was a high-bandwidth session packed with information,… Read More


CTO Interview: Ty Garibay of ArterisIP

CTO Interview: Ty Garibay of ArterisIP
by Daniel Nenni on 09-06-2017 at 12:00 pm

ArterisIP has been a SemiWiki subscriber since the first year we went live. Thus far we have published 61 Arteris related blogs that have garnered close to 300,000 visits making Arteris and NoC one of our top attractions, absolutely.

One of the more newsworthy announcements this week is the addition of Ty Garibay to the Arteris executiveRead More


NetSpeed’s Pegasus Last-Level Cache IP Improves SoC Performance and Reduces Latency

NetSpeed’s Pegasus Last-Level Cache IP Improves SoC Performance and Reduces Latency
by Mitch Heins on 07-17-2017 at 7:00 am

Memory is always a critical resource for a System-on-Chip (SoC) design. It seems like designers are always wanting more memory, and the memory they have is never fast enough to keep up with the processors, especially when using multi-core processors and GPUs. To complicate matters, today’s SoC architectures tend to share memory… Read More


NetSpeed Taking a Ride with Autonomous Automobiles

NetSpeed Taking a Ride with Autonomous Automobiles
by Mitch Heins on 04-24-2017 at 12:00 pm

The push for autonomous automobiles continues at a rapid pace. Last week a new conference was held in Santa Clara, CA by the Linley Group focused on Autonomous Hardware. The group included presentations from GLOBAL FOUNDRIES, Synopsys, NetSpeed Systems, Arteris, EMBC, Cadence, CEVA, ARM and Trilumina covering ADAS and autonomous… Read More