Moore’s Law and Semiconductor Design and Manufacturing

Moore’s Law and Semiconductor Design and Manufacturing
by Daniel Nenni on 03-12-2011 at 4:51 am

The semiconductor design and manufacturing challenges at 40nm and 28nm are a direct result ofMoore’s Law, the climbing transistor count and shrinking geometries. It’s a process AND design issue and the interaction is at the transistor level. Transistors may be shrinking, but atoms aren’t. So now it actually matters when even… Read More


Moore’s (Empirical Observation) Law!

Moore’s (Empirical Observation) Law!
by Daniel Nenni on 04-18-2010 at 10:49 pm

“What would you like your legacy to the world to be? Anything but Moore’s Law!”

 

Gordon Moore, May 2008.

Moore slightly altered the formulation of the law over time, bolstering the perceived accuracy of Moore’s law in retrospect. Most notably, in 1975, Moore altered his projection to a doubling every two years. Despite popular… Read More


TSMC 28nm Design Advisory

TSMC 28nm Design Advisory
by Daniel Nenni on 01-31-2010 at 11:49 pm

Transistors may be shrinking but atoms are not. Transistors are now just a handful of atoms so it matters even more when a couple of those atoms are out of place. Process variations, whether they are statistical, proximity, or otherwise, have got to be thoughtfully accounted for if we are to achieve the low-power, high-performance,… Read More


Moore’s Law and 28nm Yield

Moore’s Law and 28nm Yield
by Daniel Nenni on 01-24-2010 at 10:44 pm

This blog is a follow-up to my second most viewed page Moore’s Law and 40nm Yield, with a strong recommendation of how to design for yield at the advanced nodes (32/28/22nm) with Verify High-Sigma design technology.

Case in point: Circuit blocks such as complex standard cells or memory bit cells are repeated thousands or even millions… Read More