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TSMC 28nm Design Advisory

TSMC 28nm Design Advisory
by Daniel Nenni on 01-31-2010 at 11:49 pm

Transistors may be shrinking but atoms are not. Transistors are now just a handful of atoms so it matters even more when a couple of those atoms are out of place. Process variations, whether they are statistical, proximity, or otherwise, have got to be thoughtfully accounted for if we are to achieve the low-power, high-performance, and high yield design goals at 28nm.

A recent seminar byTSMC and Synopsys entitled “32/28nm Challenges – The EDA Vendor and Foundry Perspective” brought perspective to the coming design challenges. The TSMC section presented by Tom Quan is well worth seeing. Tom Quan has 30 years design and product development experience in the AMS market space. You won’t find a more engaging speaker on process variation than Tom Quan.

TSMC’s value proposition for moving to the 28nm process supports Moore’s Law with a better than 2X gate density at 28nm versus 40nm, a significant speed gain, plus reduced power leakage and an overall cost reduction. Target applications for 28nm include high performance computing and peripherals, low power devices such as HD video cameras, mobile internet and mobile computing, home and portable entertainment. TSMC’s Advanced Technology Roadmap is on track for the low power 28nm process in Q210 and high performance-high K metal gate 28nm process in Q310.

Tom Quan’s emphasis on the importance of “Variation-Aware Design” is justified. To start with, a smaller manufacturing window with much less margin to begin with equals more variation. Add to that the fact that global variation is constant, but local variation increases significantly as channel width and length decreases, and you will have a requirement for variation-aware design tools prior to GDS.
The overall TSMC design ecosystem emphasis is on collaboration between design and process. Tom divided this responsibility into Foundry: better SPICE accuracy, DFM rules, providing variation aware reference design kits (RDKs), and restricted design rules (RDRs). Designers: must be aware of layout effects, analyze-fix variation-aware methodologies will be required for area-yield tradeoffs, and pre- vs. post-layout simulation accuracy. The clear implication is that designers need to change their mindset in adopting a variation-aware design methodology as a requirement versus a luxury.

The conclusions are obvious. Partnerships between the foundry, EDA and SemIP providers, and customers will be required to eliminate silicon waste at 28nm. Partnerships that are friendly and cost effective, with shared responsibility will result in productive and innovative solutions to even the most technologically advanced challenges.

I’ve covered semiconductor process variation in my blogs on TSMC Process Variation, TSMC 40nm Yield Explained, Moore’s Law and 40nm Yield, and most recently Moore’s Law and 28nm Yield. I also work on process variation with the foundries and top semiconductor companies through strategic relationships with Solido Design Automation. Device sensitivity and process variability is something you will have to carefully model and design to at 28nm so be sure and look for variation aware methodologies before you start.

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