Layout Pattern Matching for DRC, DFM, and Yield Improvement

Layout Pattern Matching for DRC, DFM, and Yield Improvement
by Tom Dillinger on 06-01-2016 at 12:00 pm

It is truly amazing to consider the advances in microelectronic process development, using 193i photolithography. The figure below is a stark reminder of the difference between the illuminating wavelength and the final imaged geometries. This technology evolution has been enabled by continued investment in mask data generation… Read More


What the #3 EDA company is showing at #53DAC this year

What the #3 EDA company is showing at #53DAC this year
by Daniel Payne on 05-29-2016 at 12:00 pm

I live in Tualatin, Oregon just a few miles away from the corporate headquarters of the #3 EDA company in the world, Mentor Graphics. Since DAC is fast approaching, I thought it would be useful to give you a quick overview of what Mentor is going to be talking about in Austin, Texas during June 5-9. … Read More


Testing IGBTs before they go into EVs

Testing IGBTs before they go into EVs
by Don Dingee on 05-23-2016 at 4:00 pm

In the pages of SemiWiki, we are usually talking about what to do with billions of really small transistors – for a change of pace today, we’ll discuss what to do with a few really big ones. Mentor Graphics has just announced their latest MicReD platform for thermal testing of IGBTs, experiencing a resurgence (pun intended) thanks… Read More


Army of Engineers on Site Only Masks Weakness

Army of Engineers on Site Only Masks Weakness
by Jean-Marie Brunet on 05-17-2016 at 7:00 am

Hardware emulation was conceived in the 1980s to address a design verification crisis looming on the horizon. In those days, the largest digital designs were stressing the limits of the software-based, gate-level simulator that was the mainstream tool for the task.

It was anticipated and confirmed in short notice that adopting… Read More


Channel Operating Margin (COM) — A Standard for SI Analysis

Channel Operating Margin (COM) — A Standard for SI Analysis
by Tom Dillinger on 05-12-2016 at 12:00 pm

There’s an old adage, attributed to renowned computer scientist Andrew Tannenbaum, one that perhaps only engineers find amusing: “The nice thing about standards is that you have so many to choose from.” Nevertheless, IEEE standards arise from customer requirements in the electronics industry. Many relate… Read More


Are Layoffs Good for the Semiconductor Industry?

Are Layoffs Good for the Semiconductor Industry?
by Daniel Nenni on 04-30-2016 at 7:00 am

As I have mentioned before, semiconductor professionals are very smart people, pound for pound the smartest in the workforce in my opinion. So what happens when thousands of engineers from Qualcomm, Broadcom, Altera, and Intel get shown the door? They don’t go to work for Starbucks, they don’t go to the unemployment line, they … Read More


Ecosystem Partnership for Effective Network Hardware Design

Ecosystem Partnership for Effective Network Hardware Design
by Bernard Murphy on 04-29-2016 at 12:00 pm

When you’re designing a hardware solution to plug into what is arguably the most complex system of all – the Internet – you can’t get away with a little fake traffic to test whether your box is going to do all the right things at the right performance. You have to model realistic voice, video, data and wireless traffic in… Read More


Semiconductor Merger Mania Explained!

Semiconductor Merger Mania Explained!
by Daniel Nenni on 04-17-2016 at 4:00 pm

Next week is the Mentor U2U Conference in Silicon Valley. By chance I had coffee with one of the U2U keynote speakers while we were waiting for the FD-SOI Symposium to start last week and can tell you this FREE event is one you don’t want to miss:… Read More


PCB Design Requires Both Speed and Accuracy of SI/PI Analysis

PCB Design Requires Both Speed and Accuracy of SI/PI Analysis
by Tom Dillinger on 04-04-2016 at 8:00 am

The prevailing industry trends are clear: (1) PCB and die package designs are becoming more complex, across both mobile and high-performance applications; (2) communication interface performance between chips (and their related protocols) is increasingly demanding to verify; (3) signal integrity and power integrity issues… Read More


Bridging Design Environments for Advanced Multi-Die Package Verification

Bridging Design Environments for Advanced Multi-Die Package Verification
by Tom Dillinger on 03-28-2016 at 12:00 pm

This year is shaping up to be an inflection point, when multi-die packaging technology will experience tremendous market growth. Advanced 2.5D/3D package offerings have been available for several years, utilizing a variety of technologies to serve as the package substrate, interposer material for embedding die micro-bump… Read More