When I first started doing IC design back in 1978 we had hierarchical designs, and that was doing a relatively simple 16Kb DRAM chip with only 32,000 transistors using 6um (aka 6,000 nm) design rules. SoC designs today make massive use of hierarchy at all levels of IC design: IC Layout, transistor netlist, gate level netlist, RTL … Read More
I’ve had the privilege over the years to be a part of a lot of great companies, teams and projects. Some of these efforts were quite successful while others were not. It begs the question of why is it so hard to enable design reuse and capture the untapped potential of the collective intelligence within our companies? Up till now, companies… Read More
I recently wrote an article about networks-on-chip (NoC) and how Systems-On-Chip integrated circuits (SoCs) are becoming increasingly more complex and heterogeneous in nature. While researching for that article I came upon a new micro-site by Dassault Systemes that goes into great detail about the operational challenges… Read More
We’ve been covering the Dassault Systèmes “Silicon Thinking” platform for a while here, but, as I’m often prone to do, I wanted to explore the backstory to uncover more about the concept. With over 25M users of their product lifecycle management (PLM) solutions, why is Dassault Systèmes becoming so interested in semiconductor… Read More
Enterprise design management can be summed up in one word: collaboration. Intellectual property (IP) reuse and the success of distributed system-on-chip (SoC) design efforts depend strongly on how well designers can collaborate. As time-to-market windows have shortened, the challenges around design collaboration have… Read More
Make-versus-buy inadequately describes what we do now in electronic systems design. We are on a continuum of design IP acquisition and use decisions, often with a portfolio of active projects and future projects depending on the outcome. Properly managing IP means adopting a build-borrow-buy mindset and tools capable of handling… Read More
In the late 1990s and early 2000s, during the adolescent days of the system-on-chip (SoC) design movement, there was a lot talk about IP and design reuse, but it was seldom put into practice. A decade later, SoC turned into a juggernaut with a tripartite alliance of chipmakers, IP suppliers and semiconductor manufacturing fabs.… Read More
Previously, I examined chip design in the late 1970s and early 1980s. It was a nostalgic ride – thanks to all those who shared their stories. I enjoyed reading all of them. I drew two basic conclusions in the prior post:
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For those who may not know me, here is a brief introduction. I started in the semiconductor business when RCA was still making vacuum tubes and I wrote EDA software before there was an EDA industry. I’ve designed and sold chips and developed, sold and used EDA tools at companies as big as General Electric and as small as seven people.… Read More
The last graphics chip that I worked on at Intel was functionally simulated with only a tiny display size of 16×16 pixels, because that size allowed a complete regression test to be simulated overnight. Our team designed three major IP blocks: Display Processor, Graphics Processor and Bus Interface Unit. We wanted to also… Read More
