Expansion at Calypto through Real Value Addition in SoC Design

Expansion at Calypto through Real Value Addition in SoC Design
by Pawan Fangaria on 09-22-2014 at 1:00 pm

When we get the notion of expansion of a company, it always provides a positive picture about something good happening to boost that expansion. There can be several reasons for expansion such as merger & acquisition, formation of joint venture or partnership, large customer orders and so on. However, organic expansion which… Read More


Designing the Right Architecture Using HLS

Designing the Right Architecture Using HLS
by Pawan Fangaria on 09-17-2014 at 9:05 am

With the advent of HLS tools, general notion which comes to mind is that okay, there’s an automated tool which can optimize your design description written in C++/SystemC and provide you a perfect RTL. In real life, it’s not so, any design description needs hardware designer’s expertise to adopt right algorithm and architecture… Read More


Accelerating SoC Verification Through HLS

Accelerating SoC Verification Through HLS
by Pawan Fangaria on 07-28-2014 at 3:00 pm

Once upon a time there was a struggle for verification completion of semiconductor designs at gate level. Today, beyond imagination, there is a struggle to verify a design with billions of gates at the RTL level which may never complete. The designs are large SoCs with complex architectures and several constraints of area, performance,… Read More


Rest in Peace CPUs, Hello FPGAs

Rest in Peace CPUs, Hello FPGAs
by Luke Miller on 07-20-2014 at 9:00 am

FPGAs in many ways are still a bit mysterious to some folk. I was at a high level summit in April, and I realized that many there had no idea what an FPGA was. They knew at least what a CPU was or meant and that their kids talk about GPUs. A good analogy I have for an FPGA when compared to a CPU is something like this. Think of the FPGA and CPU as … Read More


S-engine Moves up the Integration of IPs into SoCs

S-engine Moves up the Integration of IPs into SoCs
by Pawan Fangaria on 07-07-2014 at 8:30 am

As the semiconductor design community is seeing higher and higher levels of abstraction with standard IPs and other complex, customized IPs and sub-systems integrated together at the system level, sooner than later we will find SoCs to be just assemblies of numerous IPs selected off-the-self according to the design needs and… Read More


High Level Synthesis update from #51DAC

High Level Synthesis update from #51DAC
by Daniel Payne on 06-27-2014 at 8:00 pm

Every since Synopsys dominated the logic synthesis market in the 1980’s we’ve had something called HLS – High Level Synthesis, meaning something higher than what Design Compiler can understand as input. At DACthis year I met with Mark Milligan of Calypto to get an update on what’s new with HLS. I first… Read More


Xilinx KCU105 Evaluation board is key for your demo

Xilinx KCU105 Evaluation board is key for your demo
by Luke Miller on 06-16-2014 at 5:34 pm

I love God, my wife, kids, and FPGA boards. I know I am not alone, there are other nerds out there, don’t be shy. Friday my “Kintex® UltraScale™ FPGA KCU105 Evaluation Kit” came in. Think about this, this is real 20nm Xilinx FPGA hardware that really works. Below is a nice picture of all the swizzles the board has.

I believe this is the … Read More


Secret to Beating Your FPGA Competitor’s Design

Secret to Beating Your FPGA Competitor’s Design
by Luke Miller on 05-17-2014 at 6:00 am

Can I ask you a personal question dear reader? It is only fair, you know so much about me and all, so here goes… Why are you still hand coding you’re FPGA design? Surely you are not hand coding interfaces, like PCie, SRIO, DDR, GbE, JESD204B, HMC etc… Correct? OK, why then are you still hand coding the guts of the world’s best, super-duper… Read More


Xilinx and Red Pitaya is Tootie Fruity

Xilinx and Red Pitaya is Tootie Fruity
by Luke Miller on 04-03-2014 at 12:00 pm

Xilinx’s Zynq SoC is the best selling FPGA of all time. Zynq has brought together, at first an uncomfortable but necessary mix of software and hardware engineers. Two very different but special kind of people. Me, I’m of the hardware persuasion. Zynq is the start of the much needed open FPGA community. This will drive down the price… Read More


Calypto: the View From the Top

Calypto: the View From the Top
by Paul McLellan on 03-05-2014 at 10:37 pm

At DVCon today I talked to Sanjiv Kaul, the CEO of Calypto. Just as a reminder, Calypto have 3 products, SLEC (sequential logical equivalence checking, also called sequential formal verification), PowerPro (sequential RTL level power reduction) and Catapult High Level Synthesis (that they took over from Mentor in 2011 in a complicated… Read More