Every since Synopsys dominated the logic synthesis market in the 1980’s we’ve had something called HLS – High Level Synthesis, meaning something higher than what Design Compiler can understand as input. At DACthis year I met with Mark Milligan of Calypto to get an update on what’s new with HLS. I first met Mark when he was at Sunrise Test Systems in the 1990’s and I was at Viewlogic, so I’ve kept in touch with him over the years.
Q: What is new at DAC for you?
This year it was Google in our booth presenting their use of CatapultHLS to develop the VP9 web video acceleration IP (part of a project called WebM). They provide this C++ IP to semiconductor partners. They were looking at how do they get their semi partners to improve the IP and feed back their ideas? Can’t be done really with RTL but only feasible using C++. Similarly, we see that other companies want to share and improve their IP at least internally, so they are moving to develop and source it at the C-level, instead of at the RTL level.
Q: What is the trend for RTL engineers?
In general RTL engineers need to collaborate better with System Architects (Matlab users), so they are learning to code in C and refining it to add synthesizable details. This allows them to try out different micro-architecture choices in a few minutes, while RTL choices would take weeks, quite a time compression.
Q: What’s new for HLS in 2014?
There’s a class of design that is well-suited for HLS, like ones in image processing where the standards are changing rapidly or algorithms are updating often. Communications applications are also very algoritm-centric, which fits into the HLS flow best. You can differentiate versus competition by changing your architecture at the C or SystemC levels.
Early Adopters have used HLS, so now we’re seeing more adoption beyond that small market.
Q: Why should an engineer consider using HLS?
RTL verification takes too much time running emulation and simulation, so just moving your IP up to SystemC or C++ you can increase speeds 1,000X and be more thorough in verification. Formal verification technology has come far enough that SystemC can become the Golden model for equivalency checking, reducing the need for RTL simulation cycles. Moving the system verification up to SystemC and C++ levels.
Q: For HLS, do you care about the input language?
No, choose SystemC or C++, it’s your personal choice, either works well and fits your preference.
DSP users from Matlab will typically choose C++.
Just like simulators support both VHDL and Verilog, you want an HLS flow that supports both SystemC and C++, choose what is best for your project.
Q: Who are your HLS competitors?
Cadence had an internal tool, but had to acquire Forte in order to compete better, but it kind of validates the importance of the market.
Q: Why should I choose Calypto for HLS?
Calypto gives you access to experts, with 10 years of experience in this field. Formal verification and integrated low power with HLS, so you can know which implementation consumes the least power.
Q: Why is power reduction so important?
Now we see power as an issue for every design style, customers have maxed out on the gate-level power-savings methods and still need more power control. Dynamic power is now a leading limiter, so that is a design issue instead of a technology issue.
An RTL design can be analyzed with deep sequential methods and then create a new implementation for low power, the formal technology will verify that the new RTL matches the original RTL. HLS now has that low power techniqes.
We have really strong RTL optimization for low power, and it benchmarks very strongly. Physically-aware RTL analysis of things like clock trees is another strong point.
Q: How is your business doing?
The fiscal year ended at another records. We’re adding AEs, and in hiring mode now. Just added a new distributor in Israel, and went direct technical support in S. Korea.
Q: How does Cadence acquiring Forte effect Calypto?
Forte getting acquired really validated the HLS market.
Q: What does success look like in 2015?
New customers talking about how they used HLS, low power and formal together on their new products. How do RTL designers create the most optimal, low-power designs?
With HLS there will be more adoption and growth, beyond just key IP to all IP.
Formal will continue to be adopted at C to RTL equivalency checking, alleviating the RTL verification challenge.
lang: en_USShare this post via: