If you still think that FDSOI is for low performance IC only…

If you still think that FDSOI is for low performance IC only…
by Eric Esteve on 02-11-2014 at 11:02 am

…then you should read about this benchmark result showing how digital power varies with process corners, for high-speed data networking chip, not exactly the type of IC targeting mid-performance mobile application. Before discussing the benchmark results, we need to have some background about this kind of ASIC chip. Such a … Read More


SOI Future or Flop?

SOI Future or Flop?
by Scotten Jones on 01-31-2014 at 8:00 am

Silicon On Insulator (SOI) is a technology that has been in use by the semiconductor industry for a long time. Early technologies such as Silicon On Sapphire (SOS) were reported as early as the sixties. In the eighties technologies such as V groove dielectric isolation were used. In the nineties we saw wafer bonding become the most… Read More


Why SOI is the Future Technology of Semiconductor

Why SOI is the Future Technology of Semiconductor
by Eric Esteve on 01-14-2014 at 8:34 am

No doubt that FDSOI generate high interest these days and I found a very interesting contribution from Zvi Or-Bach, President and CEO of MonolithIC 3D, Inc. Zvi has accepted to share his wrap-up from IEDM, in a blog for Semiwiki readers. If you remember the long discussion we had in Semiwiki about cost comparison, some comments were… Read More


UTBB FDSOI Devices Featuring 20nm Gate Length

UTBB FDSOI Devices Featuring 20nm Gate Length
by Eric Esteve on 01-09-2014 at 10:33 am

Did you go to IEDM 2013 in Washington DC ? You may have attended to the “Advanced CMOS Technology Platform” chaired by TSMC, and listen to the FD-SOI related presentation “High Performance UTBB FDSOI Devices Featuring 20nm Gate Length for 14nm Node and Beyond”. According with the abstract, this paper is the first time report of “high… Read More


Is FD-SOI Really Faster, Cooler, Simpler?

Is FD-SOI Really Faster, Cooler, Simpler?
by Eric Esteve on 11-12-2013 at 5:17 am

I love the slogan associated with FD-SOI: the technology is supposed to be Faster, Cooler, Simpler. Does this slogan reflect the reality? Let’s start with Simpler. We (the semiconductor industry) have the perception that Silicon On Insulator (SOI) technology is something complex and exotic. Why? Because SOI has been used to … Read More


IP-SoC 2013 Top Class Presentations…

IP-SoC 2013 Top Class Presentations…
by Eric Esteve on 11-10-2013 at 10:41 am

… were given to an ever shrinking audience. This is IP-SoC paradox: audience has enjoyed very good presentations made by TSMC (for the first time at IP-SoC, as far as I remember), SMIC, D&R, Gartner or ST-Microelectronic, to name just a few. The event is well organized, on the morning you can listen to keynotes in the largest … Read More


Is FD-SOI Smarter than Moore?

Is FD-SOI Smarter than Moore?
by Eric Esteve on 11-01-2013 at 12:03 pm

If you have read the excellent article from Paul McLellan, you know about FDSOI as a technology, so I will not come back to FDSOI device, and the comparison with FinFET in term of device topology, doping level and so on. If you missed it, I would recommend you to read this article, as well as the many comments (all of them being relevant).… Read More


ST Endorses PowerArtist with ARM Cores & FDSOI libs

ST Endorses PowerArtist with ARM Cores & FDSOI libs
by Pawan Fangaria on 10-01-2013 at 12:00 pm

It was an interesting webinar I attended, presented by STMicroelectronicson how they are benefited in power saving and thermal dissipation by using FDSOI technology and also by using PowerArtist in their design. So, it’s an advantage from both sides – semiconductor technology and semiconductor design tool. It’s worth attending… Read More


Can “Less than Moore” FDSOI provides better ROI for Mobile IC?

Can “Less than Moore” FDSOI provides better ROI for Mobile IC?
by Eric Esteve on 03-15-2013 at 10:00 am

In this previous article, I was suggesting that certain chip makers may take a serious look at a disruptive way to look at Moore’s law, as they may get better ROI, profit and even better revenue. The idea is to select technology node and packaging technique in order to optimize the Price, Performance, Power triptych and manage chip… Read More