Atrenta did an online survey of their users. Of course Atrenta’s users are not necessarily completely representative of the whole marketplace so it is unclear how the results would generalize for the bigger picture, your mileage may vary. About half the people were design engineers, a quarter CAD engineers and the rest … Read More
Tag: eda
Challenges in 3D-IC and 2½D Design
3D IC design and what has come to be known as 2½D IC design, with active die on a silicon interposer, require new approaches to verification since the through silicon vias (TSVs) and the fact that several different semiconductor processes may be involved create a new set of design challenges
The power delivery network is a challenge… Read More
Low power techniques
There was recently a forum discussion about the best low power techniques. Not surprisingly we didn’t come up with a new technique nobody had ever thought of but it was an interesting discussion.
First there are the techniques that by now have become standard. If anyone wants more details on these then two good resources are… Read More
Improving Analog/Mixed Signal Circuit Reliability at Advanced Nodes
Preventing electrical circuit failure is a growing concern for IC designers today. Certain types of failures such as electrostatic discharge (ESD) events, have well established best practices and design rules that circuit designers should be following. Other issues have emerged more recently, such as how to check circuits… Read More
Interoperability Forum
Earlier this week I went to the Synopsys Interoperability Forum. The big news of the day turned out to be Synopsys wanting to be more than interoperable with Magma, but that only got announced after we’d all gone away.
Philippe Margashack of ST opened, reviewing his slides from a presentation at the same forum from 10 years … Read More
December 1st – Hands-on Workshop with Calibre: DRC, LVS, DFM, xRC, ERC (Fremont, California)
I’ve blogged about the Calibre family of IC design tools before:
Smart Fill replaced Dummy Fill Approach in a DFM Flow
DRC Wiki
Graphical DRC vs Text-based DRC
Getting Real time Calibre DRC Results with Custom IC Editing
Transistor-level Electrical Rule Checking
Who Needs a 3D Field Solver for IC Design?
Prevention is Better… Read More
David Liu, Kauffmann Award winner
David Liu receeived the Kaufman award for 2001 at the Kaufman award dinner a few weeks ago.
Or to be more formal about it:Dr. C. L. David Liu, the William Mong honorary chair professor of Computer Science and former president of the National Tsing Hua University in Hsinchu, Taiwan, will be presented with this year’s Phil Kaufman Award… Read More
The Power of the Platform!
The Nintendo Wii is one of the most successful gaming platforms with the most diverse set of games — from fun games that can be enjoyed by the whole family to fitness programs that can be used by adults. They beat the dominant Sony Playstation and the Microsoft Xbox by thinking outside the box and creating a platform that was really… Read More
Physical Verification of 3D-IC Designs using TSVs
3D-IC design has become a popular discussion topic in the past few years because of the integration benefits and potential cost savings, so I wanted to learn more about how the DRC and LVS flows were being adapted. My first stop was the Global Semiconductor Alliance web site where I found a presentation about how DRC and LVS flows were… Read More
Old standards never die
I just put up a blog about the EDA interoperability forum, much of which is focused on standards. Which reminded me just how long-lived some standards turn out to be.
Back in the late 1970s Calma shipped workstations (actually re-badged Data General minicomputers) with a graphic display. That was how layout was done. It’s… Read More
