Everyone in EDA is really smart. People who leave EDA and go and work in other industries, especially people who left in the late 1990s for internet startups, notice that this is not true elsewhere. Not that there aren’t smart people in internet startups, just that not everyone is. EDA is an industry where you need a master’s… Read More
Tag: eda
Cadence Announces Quantus Next Generation Extraction
Today Cadence announced their next generation extraction solution called Quantus QRC. Actually they are technically announcing it tomorrow, since it is being announced at CDNLive in Korea where it is already Tuesday morning.
As with the other recently announced tools that end in -us, Tempus (timing signoff) and Voltus (power… Read More
S-engine Moves up the Integration of IPs into SoCs
As the semiconductor design community is seeing higher and higher levels of abstraction with standard IPs and other complex, customized IPs and sub-systems integrated together at the system level, sooner than later we will find SoCs to be just assemblies of numerous IPs selected off-the-self according to the design needs and… Read More
It’s Always Good If the Customer Is Arguing
I’ve never been in sales. Never “carried a bag”. But I have run sales forces and I have spent a lot of time in marketing, guiding sales forces. Well, herding cats comes to mind, but cats don’t have commission plans. Engineers say sales people are emotional, and ego-driven, but change their commission plans… Read More
EDA for Power Management ICs at DAC
I first met Dundar Dumlugolat Barcelona Design back in 2004, so it was a pleasure to meet with him again at DAClast week and learn more about what his company Magwel has to offer IC designers of power management chips.… Read More
IoT Breakfast Panel at DAC
Tuesday morning at DAC I enjoyed a free breakfast courtesy of Synopsysand GLOBALFOUNDRIESwhere I learned more about the emerging market of IoT, and what it means to semiconductor, EDA and IP vendors. Panelists included: Semico Research, HP, Synopsys, GLOBALFOUNDRIES and Broadcom. … Read More
DAC is Next Week!
DAC starts on Sunday. If you are in San Francisco on Sunday then the first event is the normal welcome reception. This is the ultimate networking event in EDA. It is in the Intercontinental Hotel about a block from the convention center and runs from 5.30 to 7pm. This is preceded by Gary Smith’s traditional kickoff from 5pm to… Read More
Context Aware Library Models for Improved Static Analysis Accuracy
Digital semiconductor design flows predominantly use library models (typically verilog and liberty formats) for static analyses. Design sizes continue to grow and geometry continues to shrink. Demand for superior performance continue to increase. Accuracy of the library models has become more critical than ever before … Read More
A Novel Approach to IC Design in the Cloud
Migration to cloud computing for scientific and engineering applications is inevitable. More specifically for IC design, the benefits are significant:
- Common IC design infrastructure to unburden each user from setting up and maintaining a separate infrastructure
- Cloud based IC design enables global collaboration among
Jasper at DAC
Wait, didn’t Cadence just acquire Jasper. Why is there a Jasper at DAC post?
So the big event is lunch on Tuesday, on Treasure Island. For out of towners that is the island in the middle of the bay bridge (actually just half of it). Food trucks, awesome views of the bay, and really cool street performers. There will be street magic,… Read More