Mind the Gap — Overcoming the processor-memory performance gap to unlock SoC performance

Mind the Gap — Overcoming the processor-memory performance gap to unlock SoC performance
by Sundar Iyer on 07-06-2012 at 3:25 pm

Remember the processor-memory gap— a situation where the processor is forced to stall while waiting for a memory operation to complete? This was largely a result of the high latency required for off chip memory accesses. Haven’t we solved that problem now with SoCs? SoCs are typically architected with their processors … Read More


Keeping Moore’s Law Alive

Keeping Moore’s Law Alive
by Paul McLellan on 04-27-2012 at 12:37 pm

At the GSA silicon summit yesterday the first keynote was by Subramanian Iyer of IBM on Keeping Moore’s Law Alive. He started off by asking the question “Is Moore’s Law in trouble?” and answered with an equivocal “maybe.”

Like some of the other speakers during the day, he pointed out that … Read More


Channel Routing Memories

Channel Routing Memories
by Paul McLellan on 04-23-2012 at 1:12 pm

Back in the early days of ASIC when we had just two and then (wow!) three layers of metal, place and route was done by putting the standard cells in rows with gaps between them and then using a specialized router to do the interconnection. It would use one layer of metal horizontally and one vertically and avoid jogs. This was called a … Read More


Micron Races to Its Future

Micron Races to Its Future
by Ed McKernan on 12-31-2011 at 2:01 pm

Perhaps no semiconductor company took it on the chin harder the last half of 2011 than Micron. And yet, perhaps no company was racing as hard as Micron to make a radical changeover. Micron is considered a bell weather on the overall health of the semiconductor industry given that DRAM, NAND and NOR Flash are used in some combination… Read More


Intel’s Back to the Future Buy of Micron

Intel’s Back to the Future Buy of Micron
by Ed McKernan on 08-19-2011 at 5:14 am


In an interview that Gordon Moore gave in early 2000, the former co-founder of Intel recounted how they abandoned the DRAM market in the early 1980s in order to exit the increasingly unprofitable business and focus on the promising, yet still young x86 processor market. Intel was also home to EEPROM and NOR Flash, two memory technologies… Read More


DRC+, DFM, CMP, Variablility

DRC+, DFM, CMP, Variablility
by Daniel Payne on 02-10-2011 at 12:42 pm

When I worked at Intel as a circuit design engineer I could talk directly with the technology development engineers to understand how to really push my DRAM designs and get the smallest possible memory cell layout that would still yield well, provide fast access time, and long refresh cycles.

(United States Patent 6661699. Inventor:… Read More