The Impact of UCIe on Chiplet Design: Lowering Barriers and Driving Innovation

The Impact of UCIe on Chiplet Design: Lowering Barriers and Driving Innovation
by Kalar Rajendiran on 08-15-2024 at 6:00 am

Comparative Analysis of Chiplet Interconnect Standards (Physical Layer)

The semiconductor industry is experiencing a significant transformation with the advent of chiplet design, a modular approach that breaks down complex chips into smaller, functional blocks called chiplets. A chiplet-based design approach offers numerous advantages, such as improved performance, reduced development … Read More


Synopsys – TSMC Collaboration Unleashes Innovation for TSMC OIP Ecosystem

Synopsys – TSMC Collaboration Unleashes Innovation for TSMC OIP Ecosystem
by Kalar Rajendiran on 10-10-2023 at 10:00 am

L.C. OIP 2023

As the focal point of the TSMC OIP ecosystem, TSMC has been driving important initiatives over the last few years to bring multi-die systems to the mainstream. As the world is moving quickly toward Generative AI technology and AI-based systems, multi-die and chiplet-based implementations are becoming essential. TSMC recently… Read More


How to Enable High-Performance VLSI Engineering Environments

How to Enable High-Performance VLSI Engineering Environments
by Kalar Rajendiran on 04-25-2023 at 10:00 am

License Operations Figure

Very Large Scale Integration (VLSI) engineering organizations are known for their intricate workflows that require high-performance simulation software and an abundance of simulation licenses to create cutting-edge chips. These workflows involve complex dependency trees, where one task depends on the completion of another… Read More


Design to Layout Collaboration Mixed Signal

Design to Layout Collaboration Mixed Signal
by Tom Simon on 04-07-2022 at 10:00 am

Cliosoft integration with Custom Compiler

When talking about today’s sophisticated advanced node designs it’s easy to first think about the digital challenges. Yet, the effort to design the needed analog and mixed signal blocks for them should not be underestimated. The need for high speed clocks, high frequency RF circuits and high bit rate IOs makes the analog portions,… Read More


Perforce Embedded DevOps Summit 2021 and the Path to Secure Collaboration on the Cloud

Perforce Embedded DevOps Summit 2021 and the Path to Secure Collaboration on the Cloud
by Mike Gianfagna on 03-04-2021 at 10:00 am

Perforce Embedded DevOps Summit 2021 and the Path to Secure Collaboration on the Cloud

Perforce recently held their virtual Embedded DevOps Summit. There was a lot of great presentations across many disciplines. Of particular interest to me, and likely to the SemiWiki readership as well, was a presentation by Warren Savage entitled Secure Collaboration on a Cloud-based Chip Design Environment. I’ll provide … Read More


Optimizing High Performance Packages calls for Multidisciplinary 3D Modeling

Optimizing High Performance Packages calls for Multidisciplinary 3D Modeling
by Tom Simon on 10-16-2019 at 10:00 am

For all the time we spend thinking and talking about silicon design, it’s easy to forget just how important package design is. Semiconductor packages have evolved over the years from very basic containers for ICs into very specialized and highly engineered elements of finished electronic systems. They play an important role … Read More


Behind the 3DEXPERIENCE for Silicon

Behind the 3DEXPERIENCE for Silicon
by Don Dingee on 10-31-2016 at 4:00 pm

We’ve been covering the Dassault Systèmes “Silicon Thinking” platform for a while here, but, as I’m often prone to do, I wanted to explore the backstory to uncover more about the concept. With over 25M users of their product lifecycle management (PLM) solutions, why is Dassault Systèmes becoming so interested in semiconductor… Read More


Webinar Alert – Helping Mixed Signal not be Mixed Up

Webinar Alert – Helping Mixed Signal not be Mixed Up
by Don Dingee on 08-10-2016 at 4:00 pm

Today’s profound statement: “don’t fall in love with your tools, figure out the biz process change first.” Mixed-signal SoC designers are having ample challenges with their design process and are in need of design management, but don’t want another tool to do it.… Read More


10 Challenges in IP Design Collaboration

10 Challenges in IP Design Collaboration
by Don Dingee on 07-18-2016 at 4:00 pm

Enterprise design management can be summed up in one word: collaboration. Intellectual property (IP) reuse and the success of distributed system-on-chip (SoC) design efforts depend strongly on how well designers can collaborate. As time-to-market windows have shortened, the challenges around design collaboration have… Read More


Latest Pinpoint Release Tackles DRC and Trend Lines

Latest Pinpoint Release Tackles DRC and Trend Lines
by Don Dingee on 07-06-2016 at 4:00 pm

After reading previous SemiWiki coverage on Dassault Systèmes and their ENOVIA Pinpoint solution, one big item seemed missing: how does this thing actually work? With all due respect to our other bloggers who covered when Dassault Systèmes acquired Pinpoint from Tuscany Design Automation, why Qualcomm is using Pinpoint, and… Read More