CEO Interview: Anna Fontanelli of MZ Technologies

CEO Interview: Anna Fontanelli of MZ Technologies
by Daniel Nenni on 08-18-2023 at 6:00 am

ANNA (1)

Anna has more than 25 years of expertise in managing complex R&D organizations and programs, giving birth to a number of innovative EDA technologies. She has pioneered the study and development of several generations of IC and package co-design environments and has held senior positions at leading semiconductor and EDA … Read More


Alphawave Semi Visit at #60DAC

Alphawave Semi Visit at #60DAC
by Daniel Payne on 08-03-2023 at 10:00 am

Alphawavesemi, DAC 2023 3nm eye diagram

On Wednesday at #60DAC I met Sudhir Mallya, Sr. VP Corporate Marketing at Alphawave Semi to get an update about what’s been happening at their IP company and with industry trends. The tagline for their company is: Accelerating the Connected World; and they have IP for connectivity, offer chiplet solutions, and even provide… Read More


Requirements for Multi-Die System Success

Requirements for Multi-Die System Success
by Daniel Nenni on 06-16-2023 at 6:00 am

Synopsys Chiplet Report 2023

Chiplets continue to be a hot topic on SemiWiki, conferences, white papers, webinars and one of the most active chiplet enabling vendors we work with is Synopsys. Synopsys is the #1 EDA and #1 IP company so that makes complete sense.

As you may have read, I moderated a panel on Chiplets at the last SNUG which we continue to write about.

Read More

TSMC Doubles Down on Semiconductor Packaging!

TSMC Doubles Down on Semiconductor Packaging!
by Daniel Nenni on 06-14-2023 at 6:00 am

TSMC 3DFabric Integration

Last week TSMC announced the opening of an advanced backend fab for the expansion of the TSMC 3DFabric System Integration Technology. It’s a significant announcement as the chip packaging arms race with Intel and Samsung is heating up.

Fab 6 is TSMC’s first all-in-one advanced packaging and testing fab which is part of the… Read More


WEBINAR: UCIe PHY Modeling and Simulation with XMODEL

WEBINAR: UCIe PHY Modeling and Simulation with XMODEL
by Daniel Nenni on 06-05-2023 at 6:00 am

UCIe image2

Join this webinar and see UCIe in action! This webinar presents the SystemVerilog models of a Universal Chiplet Interconnect Express (UCIe) interface, including both the analog circuits in the electrical layer and digital FSMs in the logical layer. The whole physical layer (PHY) model can be efficiently simulated in SystemVerilog,… Read More


eFPGA Enabled Chiplets!

eFPGA Enabled Chiplets!
by Daniel Nenni on 05-18-2023 at 10:00 am

Achronix eFPGA IP

With our continuing chiplet coverage I found this of great interest. I have always felt that eFPGAs and chiplets are a natural fit for the next generation of chip design and this is an excellent example. As we design with chiplets one of the challenges is verification/validation in regards to performance and interoperability. … Read More


Chiplet Modeling and Workflow Standardization Through CDX

Chiplet Modeling and Workflow Standardization Through CDX
by Kalar Rajendiran on 05-15-2023 at 6:00 am

Chiplet Integration Workflow

Chiplet is a hot topic in the semiconductor world these days. So much so that if one hasn’t heard that term, the person must be living on a very isolated islet. Humor aside, products built using chiplets-based methodology have been in existence for at least some years now. Companies such as Intel, AMD, Apple and others have integrated… Read More


The Rise of the Chiplet

The Rise of the Chiplet
by Kalar Rajendiran on 03-28-2023 at 10:00 am

Open Chiplet Economy

The emergence of chiplets as a technology is an inflection point in the semiconductor industry. The potential benefits of adopting a chiplets-based approach to implementing electronic systems are not a debate. Chiplets, which are smaller, pre-manufactured components can be combined to create larger systems, offering benefits… Read More


Checklist to Ensure Silicon Interposers Don’t Kill Your Design

Checklist to Ensure Silicon Interposers Don’t Kill Your Design
by Dr. Lang Lin on 03-20-2023 at 10:00 am

Image1

Traditional methods of chip design and packaging are running out of steam to fulfill growing demands for lower power, faster data rates, and higher integration density. Designers across many industries – like 5G, AI/ML, autonomous vehicles, and high-performance computing – are striving to adopt 3D semiconductor… Read More


Speeding up Chiplet-Based Design Through Hardware Emulation

Speeding up Chiplet-Based Design Through Hardware Emulation
by Kalar Rajendiran on 02-16-2023 at 10:00 am

Barriers on the Continuum to SiP

The first chiplets focused summit took place last month. So many accomplished speakers gave keynote talks on what direction should and would the Chiplets ecosystem evolution take. Corigine presented the keynote on what direction hardware emulation should and would evolve for speeding up chiplet- based designs. During a pre-conference… Read More