Intel Ushers a New Era of Advanced Packaging with Glass Substrates

Intel Ushers a New Era of Advanced Packaging with Glass Substrates
by Mike Gianfagna on 09-18-2023 at 10:00 am

Intel Ushers a New Era of Advanced Packaging with Glass Substrates


Intel recently issued a press announcement that has significant implications for the future of semiconductors.  The release announces Intel’s new glass substrate technology. The headline states: Glass substrates help overcome limitations of organic materials by enabling an order of magnitude improvement in design rulesRead More


Webinar: UCIe-Based Chiplet Verification – from IP to SoC

Webinar: UCIe-Based Chiplet Verification – from IP to SoC
by Admin on 09-15-2023 at 12:15 pm

About

Innovative die disaggregation technologies, enable a future where a catalog of chiplets will be available to mix and match based on the end application. The industry’s fastest emerging interconnect standard called Universal Chiplet Interconnect Express (UCIe) enables end users to combine chiplets with different functionality… Read More


Interface IP in 2022: 22% YoY growth still data-centric driven

Interface IP in 2022: 22% YoY growth still data-centric driven
by Eric Esteve on 09-04-2023 at 10:00 am

IF 2018 2027no$

We have shown in the “Design IP Report” 2022 that the market share of the wired Interface IP category is a growing part of the total IP, and that this trend is confirmed year after year. The interface IP category has moved from 18% share in 2017 to 25% in 2022.

During the 2010-decade, smartphone was the strong driver for the IP industry,… Read More


Webinar: UCIe-Based Chiplet Verification – from IP to SoC

Webinar: UCIe-Based Chiplet Verification – from IP to SoC
by Admin on 08-21-2023 at 1:34 pm

Date: Wednesday, August 30, 2023

Time: 11:00am PDT | 1:00pm CDT | 2:00pm EDT

Innovative die disaggregation technologies, enable a future where a catalog of chiplets will be available to mix and match based on the end application. The industry’s fastest emerging interconnect standard called Universal Chiplet Interconnect Express… Read More


CEO Interview: Anna Fontanelli of MZ Technologies

CEO Interview: Anna Fontanelli of MZ Technologies
by Daniel Nenni on 08-18-2023 at 6:00 am

ANNA (1)

Anna has more than 25 years of expertise in managing complex R&D organizations and programs, giving birth to a number of innovative EDA technologies. She has pioneered the study and development of several generations of IC and package co-design environments and has held senior positions at leading semiconductor and EDA … Read More


Alphawave Semi Visit at #60DAC

Alphawave Semi Visit at #60DAC
by Daniel Payne on 08-03-2023 at 10:00 am

Alphawavesemi, DAC 2023 3nm eye diagram

On Wednesday at #60DAC I met Sudhir Mallya, Sr. VP Corporate Marketing at Alphawave Semi to get an update about what’s been happening at their IP company and with industry trends. The tagline for their company is: Accelerating the Connected World; and they have IP for connectivity, offer chiplet solutions, and even provide… Read More


Webinar: IP Lifecycle Management for Chiplet-Based SoCs

Webinar: IP Lifecycle Management for Chiplet-Based SoCs
by Admin on 08-02-2023 at 2:56 pm

Chiplet-based SoC architectures have seen increased interest over the past three years, and recently were made a focus of the federal CHIPS and Science Act to reduce the cost of innovation for US-based semiconductor startups, DoD projects, and academic research. Chiplet-based architectures bring their own set of challenges… Read More


Webinar: UCIe: On-Package Chiplet Innovation Opportunities

Webinar: UCIe: On-Package Chiplet Innovation Opportunities
by Admin on 07-31-2023 at 2:17 pm

Synopsys Webinar | Tuesday, August 15, 2023 | 10:00 -11:00 a.m. PDT

High-performance workloads demand on-package integration of heterogeneous processing units, on-package memory, and communication infrastructure to meet the demands of today’s data centers, autonomous vehicles, etc. On-package interconnects are a critical

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Requirements for Multi-Die System Success

Requirements for Multi-Die System Success
by Daniel Nenni on 06-16-2023 at 6:00 am

Synopsys Chiplet Report 2023

Chiplets continue to be a hot topic on SemiWiki, conferences, white papers, webinars and one of the most active chiplet enabling vendors we work with is Synopsys. Synopsys is the #1 EDA and #1 IP company so that makes complete sense.

As you may have read, I moderated a panel on Chiplets at the last SNUG which we continue to write about.

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TSMC Doubles Down on Semiconductor Packaging!

TSMC Doubles Down on Semiconductor Packaging!
by Daniel Nenni on 06-14-2023 at 6:00 am

TSMC 3DFabric Integration

Last week TSMC announced the opening of an advanced backend fab for the expansion of the TSMC 3DFabric System Integration Technology. It’s a significant announcement as the chip packaging arms race with Intel and Samsung is heating up.

Fab 6 is TSMC’s first all-in-one advanced packaging and testing fab which is part of the… Read More