Join this webinar and see UCIe in action! This webinar presents the SystemVerilog models of a Universal Chiplet Interconnect Express (UCIe) interface, including both the analog circuits in the electrical layer and digital FSMs in the logical layer. The whole physical layer (PHY) model can be efficiently simulated in SystemVerilog,… Read More
With our continuing chiplet coverage I found this of great interest. I have always felt that eFPGAs and chiplets are a natural fit for the next generation of chip design and this is an excellent example. As we design with chiplets one of the challenges is verification/validation in regards to performance and interoperability. … Read More
Chiplet is a hot topic in the semiconductor world these days. So much so that if one hasn’t heard that term, the person must be living on a very isolated islet. Humor aside, products built using chiplets-based methodology have been in existence for at least some years now. Companies such as Intel, AMD, Apple and others have integrated… Read More
Join us on May 17 for the latest 3D-IC webinar series, “Power Integrity Challenges and Solutions for Interposer Design.” The discussion will focus on interposer power analysis as an isolated case and in context with the dice instantiated in a 3D-IC device. The presentation will then explore the completed multi-chip design in
CEA-List and Menta SAS will present together the MOSAICS-LP project,
a scalable chiplet platform
The emergence of chiplets as a technology is an inflection point in the semiconductor industry. The potential benefits of adopting a chiplets-based approach to implementing electronic systems are not a debate. Chiplets, which are smaller, pre-manufactured components can be combined to create larger systems, offering benefits… Read More
Traditional methods of chip design and packaging are running out of steam to fulfill growing demands for lower power, faster data rates, and higher integration density. Designers across many industries – like 5G, AI/ML, autonomous vehicles, and high-performance computing – are striving to adopt 3D semiconductor… Read More
The first chiplets focused summit took place last month. So many accomplished speakers gave keynote talks on what direction should and would the Chiplets ecosystem evolution take. Corigine presented the keynote on what direction hardware emulation should and would evolve for speeding up chiplet- based designs. During a pre-conference… Read More
UCIe™ — Universal Chiplet Interconnect Express™ — is an open industry standard founded by the leaders in semiconductors, packaging, IP suppliers, foundries, and cloud service providers to address customer requests for more customizable package-level integration. The newly… Read More
Dan is joined by Nick Ilyadis, Senior Director of Product Planning at Achronix. With over 35 years of data and semiconductor engineering and manufacturing experience and 72 issued patents under his name, Nick is a recognized expert on software and hardware development and quality control.
Dan explores the emerging chiplet market… Read More
