The Cadence-BDA saga continues with Berkeley Design Automation today filing a motion to dismiss. You can read the full motion HERE. My previous blog “Cadence Sues Berkeley Design Automation” with 30+ comments is HERE.
The first problem BDA brings up is that the DMCA claim by Cadence is so vague that it doesn’t… Read More
Last night at Cadence was the next installment of what I have been calling Hogan University. Jim interviewed Joe Costello about how to tell a story as part of the EDAC emerging companies series of events. The main focus was how to tell a story as a small EDA company communicating with investors, although there are obviously other forms… Read More
Going to Munich in May could be a very good idea, as it will give you the opportunity to listen to the keynote talk from Lip-Bu Tan. Who knows if you will learn in direct live the name of the next acquisition from Cadence in 2013, after Tensilica and Cosmic Circuits? In fact, there may not be new acquisition announcement, then this keynote… Read More
TSMC has been investing in the fabless semiconductor ecosystem for 25+ years and that is why they are the #1 foundry and lead this industry (my opinion). I’m a big fan of joint webinars. Not only is it collaboration open to the masses, it is a close collaboration between the two sponsoring companies. Having worked on the TSMC… Read More
I won’t be able to attend Chris Rowen’s presentation here at the GlobalPress Electronic Summit since I’m going to the first day of the Linley Mobile Microprocessor conference. In fact I wonder if Chris himself will make it since he was running in the Boston marathon on Monday. He finished about 10 minutes before… Read More
We’ve blogged before about Layout Dependent Effects (LDE) on SemiWiki and how it further complicates the IC design and layout process, especially at 28nm and lower nodes because the IC layout starts to change the MOS device performance. There’s an interesting webinarfrom Cadence on Variation-aware IC Design, … Read More
Foundries and EDA vendors are cooperating at increasing levels of technical intimacy as we head to the 20nm and lower nodes. Cadence has a strong position in the EDA tools used for IC design and layout of custom and AMS (Analog Mixed-Signal) designs. They have created a series of webinars to highlight the design challenges and new… Read More
SemiWiki broke the story yesterday about the Cadence legal action against Berkeley Design Automation and today I spent time with customers of both companies in Silicon Valley getting reactions. That is the advantage of working in Silicon Valley for almost 30 years, if you don’t know the right people, you certainly know the people… Read More
Cadence has brought a suit against Berkeley Design Automation for, as far as I can see, integrating their AFS circuit simulator with the Virtuoso Analog Design Environment (ADE) without using the (licensed) Oasis product. Since BDA is (actually was) a member of the Cadence Connections program, they have to abide by the contract… Read More
As we have moved towards lower process nodes to improve performance of ICs with higher density and functionality, many manufacturing effects have appeared which can render ICs useless, even though the layout design could be correct as per traditional design rules. What is more worrisome is the variability of these effects which… Read More
