DRC+, DFM, CMP, Variablility

DRC+, DFM, CMP, Variablility
by Daniel Payne on 02-10-2011 at 12:42 pm

When I worked at Intel as a circuit design engineer I could talk directly with the technology development engineers to understand how to really push my DRAM designs and get the smallest possible memory cell layout that would still yield well, provide fast access time, and long refresh cycles.

(United States Patent 6661699. Inventor:… Read More


Semiconductor IP Companies Still in Play

Semiconductor IP Companies Still in Play
by Daniel Nenni on 07-03-2009 at 12:05 am

A recent EETimes article about memory IP vendors reminded me to follow up on my blogs about IP companies, which I believe are the best investments in semiconductor design today. It is a fluff piece, Mark LaPedus briefly mentions ARM, Synopsys, Virage Logic, and Denali, but his analysis is right on the mark. There is definitely money… Read More