As one of the world’s leading chip foundries, Samsung occupies a vital position in the semiconductor value chain. The annual Samsung Advanced Foundry Ecosystem (SAFE™) Forum is a must-go event for semiconductor and electronic design automation (EDA) professionals. Ajei Gopal, President and CEO of Ansys, has the honor of delivering… Read More
Tag: 3d-ic
Chiplet Q&A with John Lee of Ansys
At the recent Synopsys Users Group Meeting (SNUG) I had the honor of leading a panel of experts on the topic of chiplets. One of those panelists was John Lee, Head of Electronics, Semiconductors and Optics at Ansys.
How is the signoff flow evolving and what is being done to help mitigate the growing signoff complexity challenge?
With… Read More
Multiphysics Analysis from Chip to System
Multiphysics simulation is the process of computational methods to model and analyze a system to understand its response to different physical interactions like heat transfer, electromagnetic fields, and mechanical structures. Using this technique, designers can generate physics-based models and analyze the behavior… Read More
3D IC – Managing the System-level Netlist
I just did a Google search for “3D IC”, and was stunned to see it return a whopping 476,000 results. This topic is trending, because more companies are using advanced IC packaging to meet their requirements, and yet the engineers doing the 3D IC design have new challenges to overcome. One of those challenges is creating… Read More
Ansys’ Emergence as a Tier 1 EDA Player— and What That Means for 3D-IC
Over its 40+ year history, electronic design automation (EDA) has seen many companies rise, fall, and merge. In the beginning, in the 1980s, the industry was dominated by what came to be known as the big three — Daisy Systems, Mentor Graphics, and Valid Logic (the infamous “DMV”). The Big 3 has morphed over the years, eventually settling… Read More
Five Key Workflows For 3D IC Packaging Success
An earlier blog started with the topic of delivering 3D IC innovations faster. The blog covered the following foundational enablers for successful heterogeneous 3D IC implementation.
- System Co-Optimization (STCO) approach
- Transition from design-based to systems-based optimization
- Expanding the supply chain and tool
Delivering 3D IC Innovations Faster
3D IC technology development started many years ago well before the slowing down of Moore’s law benefits became a topic of discussion. The technology was originally leveraged for stacking functional blocks with high-bandwidth buses between them. Memory manufacturers and other IDMs were the ones to typically leverage this … Read More
The Lines Are Blurring Between System and Silicon. You’re Not Ready.
3D-ICs bring together multiple silicon dies into a single package that’s significantly larger and complex than traditional systems on a chip (SoCs). There’s no doubt these innovative designs are revolutionizing the semiconductor industry.
3D-ICs offer a variety of performance advantages over traditional SoCs. Because … Read More
Multiphysics, Multivariate Analysis: An Imperative for Today’s 3D-IC Designs
Semiconductor manufacturers are under constantly increasing and intense pressure to accelerate innovative new chip designs to market faster than ever in smaller package sizes while assuring signal integrity and reducing power consumption. Three-dimensional integrated circuits (3D-ICs) promise to answer all these demands… Read More
Three Key Takeaways from the 2022 TSMC Technical Symposium!
The TSMC Technical Symposium is today so I wanted to give you a brief summary of what was presented. Tom Dillinger will do a more technical review as he has done in the past. I don’t want to steal his thunder but here is what I think are the key takeaways. First a brief history lesson.
The history of TSMC Technology Development with 12 key… Read More